WIP changes

2 files changed, 2 insertions, 2 deletions

diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index b074cfa1b..c8499bdc7 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -354,7 +354,7 @@ impl<'d, T: Instance> Bus<'d, T> {
         // Configuring Vbus sense and SOF output
         match core_id {
             0x0000_1200 | 0x0000_1100 | 0x0000_1000 => self.inner.config_v1(),
-            0x0000_2000 | 0x0000_2100 | 0x0000_2300 | 0x0000_3000 | 0x0000_3100 => self.inner.config_v2v3(),
+            0x0000_2000 | 0x0000_2100 | 0x0000_2300 | 0x0000_3000 | 0x0000_3100 | 0x0000_6100 => self.inner.config_v2v3(),
             0x0000_5000 => self.inner.config_v5(),
             _ => unimplemented!("Unknown USB core id {:X}", core_id),
         }
diff --git a/examples/stm32wba/src/bin/usb_hs_serial.rs b/examples/stm32wba/src/bin/usb_hs_serial.rs
index 4684e3aa6..1ffd94906 100644
--- a/examples/stm32wba/src/bin/usb_hs_serial.rs
+++ b/examples/stm32wba/src/bin/usb_hs_serial.rs
@@ -28,7 +28,7 @@ async fn main(_spawner: Spawner) {
     config.rcc.sys = Sysclk::HSE;
     // route HSE into the USB‐OTG‐HS block
     config.rcc.mux.otghssel = mux::Otghssel::HSE;
-    config.rcc.sys = Sysclk::PLL1_R;
+    config.rcc.sys = Sysclk::HSE;
     config.rcc.voltage_scale = VoltageScale::RANGE1;
 
     let p = embassy_stm32::init(config);