Partially working USB example

3 files changed, 37 insertions, 23 deletions

diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index 4ca622614..a5e6b33ff 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -2,7 +2,7 @@ pub use crate::pac::pwr::vals::Vos as VoltageScale;
 use crate::pac::rcc::regs::Cfgr1;
 pub use crate::pac::rcc::vals::{
     Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as Sysclk, Pllsrc as PllSource,
-    Plldiv as PllDiv, Pllm, Plln as PllMul,
+    Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
 };
 use crate::pac::rcc::vals::Pllrge;
 use crate::pac::{FLASH, RCC};
@@ -32,7 +32,7 @@ pub struct Pll {
     /// The PLL pre-divider.
     ///
     /// The clock speed of the `source` divided by `m` must be between 4 and 16 MHz.
-    pub pllm: Pllm,
+    pub prediv: PllPreDiv,
     /// The PLL multiplier.
     ///
     /// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544
@@ -287,15 +287,18 @@ fn init_pll(config: Option<Pll>, input: &PllInput, voltage_range: VoltageScale)
 
     let Some(pll) = config else { return PllOutput::default() };
 
-    let src_freq = match pll.source {
+    let pre_src_freq = match pll.source {
         PllSource::DISABLE => panic!("must not select PLL source as DISABLE"),
         PllSource::HSE => unwrap!(input.hse),
         PllSource::HSI => unwrap!(input.hsi),
         PllSource::_RESERVED_1 => panic!("must not select RESERVED_1 source as DISABLE"),
     };
 
+    let hse_div = RCC.cr().read().hsepre();
+    let src_freq = pre_src_freq / hse_div;
+
     // Calculate the reference clock, which is the source divided by m
-    let ref_freq = src_freq / pll.pllm;
+    let ref_freq = src_freq / pll.prediv;
     // Check limits per RM0515 § 12.4.3
     assert!(Hertz::mhz(4) <= ref_freq && ref_freq <= Hertz::mhz(16));
 
@@ -325,7 +328,6 @@ fn init_pll(config: Option<Pll>, input: &PllInput, voltage_range: VoltageScale)
         w.set_pllp(pll.divp.unwrap_or(PllDiv::DIV1));
         w.set_pllq(pll.divq.unwrap_or(PllDiv::DIV1));
         w.set_pllr(pll.divr.unwrap_or(PllDiv::DIV1));
-        // w.set_pllfracn(pll.frac.unwrap_or(1));
     });
     RCC.pll1fracr().write(|w| {w.set_pllfracn(pll.frac.unwrap_or(1));});
 
@@ -340,7 +342,7 @@ fn init_pll(config: Option<Pll>, input: &PllInput, voltage_range: VoltageScale)
             $w.set_pllqen(pll.divq.is_some());
             $w.set_pllren(pll.divr.is_some());
             $w.set_pllfracen(pll.frac.is_some());
-            $w.set_pllm(pll.pllm);
+            $w.set_pllm(pll.prediv);
             $w.set_pllsrc(pll.source);
             $w.set_pllrge(input_range);
         };
diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index 02b27ed48..6b28ac980 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -315,30 +315,42 @@ impl<'d, T: Instance> Bus<'d, T> {
 
         #[cfg(all(stm32u5, peri_usb_otg_hs))]
         {
-            crate::pac::SYSCFG.otghsphycr().modify(|w| {
-                w.set_en(true);
-            });
-
             critical_section::with(|_| {
                 crate::pac::RCC.ahb2enr1().modify(|w| {
                     w.set_usb_otg_hsen(true);
                     w.set_usb_otg_hs_phyen(true);
                 });
             });
-        }
 
-        #[cfg(all(stm32wba, peri_usb_otg_hs))]
-        {
             crate::pac::SYSCFG.otghsphycr().modify(|w| {
                 w.set_en(true);
             });
+        }
 
+        #[cfg(all(stm32wba, peri_usb_otg_hs))]
+        {
             critical_section::with(|_| {
+                crate::pac::RCC.apb7enr().modify(|w| {
+                    w.set_syscfgen(true);
+                });
                 crate::pac::RCC.ahb2enr().modify(|w| {
                     w.set_usb_otg_hsen(true);
                     w.set_usb_otg_hs_phyen(true);
                 });
             });
+
+            // pub use crate::pac::rcc::vals::Otghssel;
+            // // select HSE
+            // crate::pac::RCC.ccipr2().modify(|w| {w.set_otghssel(Otghssel::HSE);});
+
+            crate::pac::SYSCFG.otghsphytuner2().modify(|w| {
+                w.set_compdistune(0b010);
+                w.set_sqrxtune(0b000);
+            });
+
+            crate::pac::SYSCFG.otghsphycr().modify(|w| {
+                w.set_en(true);
+            });
         }
 
         let r = T::regs();
diff --git a/examples/stm32wba/src/bin/usb_hs_serial.rs b/examples/stm32wba/src/bin/usb_hs_serial.rs
index e30f33625..bda4a5013 100644
--- a/examples/stm32wba/src/bin/usb_hs_serial.rs
+++ b/examples/stm32wba/src/bin/usb_hs_serial.rs
@@ -5,7 +5,7 @@ use defmt::{panic, *};
 use defmt_rtt as _; // global logger
 use embassy_executor::Spawner;
 use embassy_futures::join::join;
-use embassy_stm32::rcc::PllSource;
+use embassy_stm32::rcc::{PllSource, PllPreDiv, PllMul, PllDiv};
 use embassy_stm32::rcc::{mux, AHBPrescaler, APBPrescaler, Hse, HsePrescaler, Sysclk, VoltageScale};
 use embassy_stm32::usb::{Driver, Instance};
 use embassy_stm32::{bind_interrupts, peripherals, usb, Config};
@@ -26,21 +26,18 @@ async fn main(_spawner: Spawner) {
 
     // External HSE (32 MHz) setup
     config.rcc.hse = Some(Hse {
-        prescaler: HsePrescaler::DIV1,
+        prescaler: HsePrescaler::DIV2,
     });
 
-    // route HSE into the USB‐OTG‐HS block
-    config.rcc.mux.otghssel = mux::Otghssel::HSE;
-    config.rcc.sys = Sysclk::HSE;
 
     // Fine-tune PLL1 dividers/multipliers
     config.rcc.pll1 = Some(embassy_stm32::rcc::Pll {
         source: PllSource::HSE,
-        pllm: 2.into(),          // PLLM = 2 → HSE / 2 = 16 MHz input
-        mul: 12.into(),          // PLLN = 12 → 16 MHz * 12 = 192 MHz VCO
-        divp: Some(2.into()),    // PLLP = 2 → 96 MHz
-        divq: Some(2.into()),    // PLLQ = 2 → 96 MHz
-        divr: Some(2.into()),    // PLLR = 2 → 96 MHz
+        prediv: PllPreDiv::DIV2,     // PLLM = 2 → HSE / 2 = 8 MHz
+        mul: PllMul::MUL60,          // PLLN = 60 → 8 MHz * 60 = 480 MHz VCO
+        divr: Some(PllDiv::DIV5),    // PLLR = 5 → 96 MHz (Sysclk)
+        divq: Some(PllDiv::DIV10),    // PLLQ = 10 → 48 MHz (USB)
+        divp: Some(PllDiv::DIV15),    // PLLP = 15 → 32 MHz (USBOTG)
         frac: Some(4096), // Fractional part (enabled)
     });
 
@@ -51,6 +48,9 @@ async fn main(_spawner: Spawner) {
 
     // voltage scale for max performance
     config.rcc.voltage_scale = VoltageScale::RANGE1;
+    // route PLL1_P into the USB‐OTG‐HS block
+    config.rcc.mux.otghssel = mux::Otghssel::PLL1_P;
+    config.rcc.sys = Sysclk::PLL1_R;
 
     let p = embassy_stm32::init(config);