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authorxoviat <[email protected]>2025-12-13 08:57:08 -0600
committerxoviat <[email protected]>2025-12-13 08:57:08 -0600
commita8de273d61f7bfa6f521dc53f41ed419f8cdc463 (patch)
treeb47672a8ffa57e75aadfe41f0bf079111c1ac07d
parent38386c323dd3b7345d011d6775333f65c8ac3ac2 (diff)
impl. scoped block_stop for ipcc
-rw-r--r--embassy-stm32/src/hsem/mod.rs3
-rw-r--r--embassy-stm32/src/ipcc.rs5
2 files changed, 6 insertions, 2 deletions
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index e62de0454..b5fa3c897 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -148,6 +148,7 @@ impl<'a, T: Instance> HardwareSemaphoreChannel<'a, T> {
148 /// The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to 148 /// The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to
149 /// check if the lock has been successful, carried out from the HSEM_Rx register. 149 /// check if the lock has been successful, carried out from the HSEM_Rx register.
150 pub async fn lock(&mut self, process_id: u8) -> HardwareSemaphoreMutex<'a, T> { 150 pub async fn lock(&mut self, process_id: u8) -> HardwareSemaphoreMutex<'a, T> {
151 let _scoped_block_stop = T::RCC_INFO.block_stop();
151 let core_id = CoreId::current(); 152 let core_id = CoreId::current();
152 153
153 poll_fn(|cx| { 154 poll_fn(|cx| {
@@ -241,7 +242,7 @@ impl<T: Instance> HardwareSemaphore<T> {
241 _peripheral: Peri<'d, T>, 242 _peripheral: Peri<'d, T>,
242 _irq: impl interrupt::typelevel::Binding<T::Interrupt, HardwareSemaphoreInterruptHandler<T>> + 'd, 243 _irq: impl interrupt::typelevel::Binding<T::Interrupt, HardwareSemaphoreInterruptHandler<T>> + 'd,
243 ) -> Self { 244 ) -> Self {
244 rcc::enable_and_reset::<T>(); 245 rcc::enable_and_reset_without_stop::<T>();
245 246
246 HardwareSemaphore { _type: PhantomData } 247 HardwareSemaphore { _type: PhantomData }
247 } 248 }
diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
index fc0f3491e..74ce0b29e 100644
--- a/embassy-stm32/src/ipcc.rs
+++ b/embassy-stm32/src/ipcc.rs
@@ -85,6 +85,7 @@ impl<'a> IpccTxChannel<'a> {
85 85
86 /// Send data to an IPCC channel. The closure is called to write the data when appropriate. 86 /// Send data to an IPCC channel. The closure is called to write the data when appropriate.
87 pub async fn send(&mut self, f: impl FnOnce()) { 87 pub async fn send(&mut self, f: impl FnOnce()) {
88 let _scoped_block_stop = IPCC::RCC_INFO.block_stop();
88 let regs = IPCC::regs(); 89 let regs = IPCC::regs();
89 90
90 self.flush().await; 91 self.flush().await;
@@ -99,6 +100,7 @@ impl<'a> IpccTxChannel<'a> {
99 100
100 /// Wait for the tx channel to become clear 101 /// Wait for the tx channel to become clear
101 pub async fn flush(&mut self) { 102 pub async fn flush(&mut self) {
103 let _scoped_block_stop = IPCC::RCC_INFO.block_stop();
102 let regs = IPCC::regs(); 104 let regs = IPCC::regs();
103 105
104 // This is a race, but is nice for debugging 106 // This is a race, but is nice for debugging
@@ -144,6 +146,7 @@ impl<'a> IpccRxChannel<'a> {
144 146
145 /// Receive data from an IPCC channel. The closure is called to read the data when appropriate. 147 /// Receive data from an IPCC channel. The closure is called to read the data when appropriate.
146 pub async fn receive<R>(&mut self, mut f: impl FnMut() -> Option<R>) -> R { 148 pub async fn receive<R>(&mut self, mut f: impl FnMut() -> Option<R>) -> R {
149 let _scoped_block_stop = IPCC::RCC_INFO.block_stop();
147 let regs = IPCC::regs(); 150 let regs = IPCC::regs();
148 151
149 loop { 152 loop {
@@ -221,7 +224,7 @@ impl Ipcc {
221 + 'd, 224 + 'd,
222 _config: Config, 225 _config: Config,
223 ) -> Self { 226 ) -> Self {
224 rcc::enable_and_reset::<IPCC>(); 227 rcc::enable_and_reset_without_stop::<IPCC>();
225 IPCC::set_cpu2(true); 228 IPCC::set_cpu2(true);
226 229
227 // Verify rfwkpsel is set 230 // Verify rfwkpsel is set