Merge #1432

1432: Support PLLXTPRE switch. r=Dirbaio a=MrOscarLoplate

See figure 2. Clock tree page 12 DS5319 Rev 18
https://www.st.com/resource/en/datasheet/stm32f103cb.pdf

Co-authored-by: Marco Pastrello <[email protected]>

1 files changed, 7 insertions, 1 deletions

diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs
index e667dbf90..4769b7059 100644
--- a/embassy-stm32/src/rcc/f1.rs
+++ b/embassy-stm32/src/rcc/f1.rs
@@ -24,10 +24,13 @@ pub struct Config {
     pub pclk1: Option<Hertz>,
     pub pclk2: Option<Hertz>,
     pub adcclk: Option<Hertz>,
+    pub pllxtpre: bool,
 }
 
 pub(crate) unsafe fn init(config: Config) {
-    let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0 / 2);
+    let pllxtpre_div = if config.pllxtpre { 2 } else { 1 };
+    let pllsrcclk = config.hse.map(|hse| hse.0 / pllxtpre_div).unwrap_or(HSI_FREQ.0 / 2);
+
     let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
     let pllmul = sysclk / pllsrcclk;
 
@@ -143,6 +146,9 @@ pub(crate) unsafe fn init(config: Config) {
     }
 
     if let Some(pllmul_bits) = pllmul_bits {
+        let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 };
+        RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(pllctpre_flag)));
+
         // enable PLL and wait for it to be ready
         RCC.cfgr().modify(|w| {
             w.set_pllmul(Pllmul(pllmul_bits));