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authorRomain Goyet <[email protected]>2024-02-01 13:39:14 -0500
committerRomain Goyet <[email protected]>2024-02-01 13:42:48 -0500
commitaa767272a87bddc9ac7fbce3962989342390d689 (patch)
treefe01afcfef26a7e9627d23a8d8f163088e271a24
parent9769d29c222990ae12bdb9920271db6ef440257d (diff)
STM32WBA's high speed external clock has to run at 32 MHz
-rw-r--r--embassy-stm32/src/rcc/wba.rs14
1 files changed, 8 insertions, 6 deletions
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index c0cd91507..1d04d480a 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -6,26 +6,28 @@ use crate::time::Hertz;
6 6
7/// HSI speed 7/// HSI speed
8pub const HSI_FREQ: Hertz = Hertz(16_000_000); 8pub const HSI_FREQ: Hertz = Hertz(16_000_000);
9// HSE speed
10pub const HSE_FREQ: Hertz = Hertz(32_000_000);
9 11
10pub use crate::pac::pwr::vals::Vos as VoltageScale; 12pub use crate::pac::pwr::vals::Vos as VoltageScale;
11pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler}; 13pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
12 14
13#[derive(Copy, Clone)] 15#[derive(Copy, Clone)]
14pub enum ClockSrc { 16pub enum ClockSrc {
15 HSE(Hertz), 17 HSE,
16 HSI, 18 HSI,
17} 19}
18 20
19#[derive(Clone, Copy, Debug)] 21#[derive(Clone, Copy, Debug)]
20pub enum PllSource { 22pub enum PllSource {
21 HSE(Hertz), 23 HSE,
22 HSI, 24 HSI,
23} 25}
24 26
25impl Into<Pllsrc> for PllSource { 27impl Into<Pllsrc> for PllSource {
26 fn into(self) -> Pllsrc { 28 fn into(self) -> Pllsrc {
27 match self { 29 match self {
28 PllSource::HSE(..) => Pllsrc::HSE, 30 PllSource::HSE => Pllsrc::HSE,
29 PllSource::HSI => Pllsrc::HSI, 31 PllSource::HSI => Pllsrc::HSI,
30 } 32 }
31 } 33 }
@@ -34,7 +36,7 @@ impl Into<Pllsrc> for PllSource {
34impl Into<Sw> for ClockSrc { 36impl Into<Sw> for ClockSrc {
35 fn into(self) -> Sw { 37 fn into(self) -> Sw {
36 match self { 38 match self {
37 ClockSrc::HSE(..) => Sw::HSE, 39 ClockSrc::HSE => Sw::HSE,
38 ClockSrc::HSI => Sw::HSI, 40 ClockSrc::HSI => Sw::HSI,
39 } 41 }
40 } 42 }
@@ -64,11 +66,11 @@ impl Default for Config {
64 66
65pub(crate) unsafe fn init(config: Config) { 67pub(crate) unsafe fn init(config: Config) {
66 let sys_clk = match config.mux { 68 let sys_clk = match config.mux {
67 ClockSrc::HSE(freq) => { 69 ClockSrc::HSE => {
68 RCC.cr().write(|w| w.set_hseon(true)); 70 RCC.cr().write(|w| w.set_hseon(true));
69 while !RCC.cr().read().hserdy() {} 71 while !RCC.cr().read().hserdy() {}
70 72
71 freq 73 HSE_FREQ
72 } 74 }
73 ClockSrc::HSI => { 75 ClockSrc::HSI => {
74 RCC.cr().write(|w| w.set_hsion(true)); 76 RCC.cr().write(|w| w.set_hsion(true));