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authorDario Nieuwenhuis <[email protected]>2021-12-08 03:18:15 +0100
committerDario Nieuwenhuis <[email protected]>2021-12-08 03:18:15 +0100
commitb316d2620c73f7e2a5cd3c46dbc20c24b7a1c57f (patch)
tree333c77f4b8b0f9d8213b6accd5601150a17a9ac2
parent6179da6b9c3c6f20f0b0c1da8350cacb1ebb25d2 (diff)
stm32/dma: improve trait docs, seal Word.
-rw-r--r--embassy-stm32/src/dma/bdma.rs6
-rw-r--r--embassy-stm32/src/dma/dma.rs6
-rw-r--r--embassy-stm32/src/dma/mod.rs50
-rw-r--r--embassy-stm32/src/i2c/v2.rs4
-rw-r--r--embassy-stm32/src/usart/v1.rs4
-rw-r--r--embassy-stm32/src/usart/v2.rs4
6 files changed, 50 insertions, 24 deletions
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index 3d06b6351..29c9fd592 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -89,7 +89,7 @@ pac::dma_channels! {
89 ($channel_peri:ident, $dma_peri:ident, bdma, $channel_num:expr, $dmamux:tt) => { 89 ($channel_peri:ident, $dma_peri:ident, bdma, $channel_num:expr, $dmamux:tt) => {
90 impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri { 90 impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {
91 91
92 unsafe fn start_write<W: Word>(&mut self, request: Request, buf: &[W], reg_addr: *mut u32) { 92 unsafe fn start_write<W: Word>(&mut self, request: Request, buf: &[W], reg_addr: *mut W) {
93 low_level_api::reset_status(crate::pac::$dma_peri, $channel_num); 93 low_level_api::reset_status(crate::pac::$dma_peri, $channel_num);
94 low_level_api::start_transfer( 94 low_level_api::start_transfer(
95 crate::pac::$dma_peri, 95 crate::pac::$dma_peri,
@@ -110,7 +110,7 @@ pac::dma_channels! {
110 } 110 }
111 111
112 112
113 unsafe fn start_write_repeated<W: Word>(&mut self, request: Request, repeated: W, count: usize, reg_addr: *mut u32) { 113 unsafe fn start_write_repeated<W: Word>(&mut self, request: Request, repeated: W, count: usize, reg_addr: *mut W) {
114 let buf = [repeated]; 114 let buf = [repeated];
115 low_level_api::reset_status(crate::pac::$dma_peri, $channel_num); 115 low_level_api::reset_status(crate::pac::$dma_peri, $channel_num);
116 low_level_api::start_transfer( 116 low_level_api::start_transfer(
@@ -131,7 +131,7 @@ pac::dma_channels! {
131 ) 131 )
132 } 132 }
133 133
134 unsafe fn start_read<W: Word>(&mut self, request: Request, reg_addr: *mut u32, buf: &mut [W]) { 134 unsafe fn start_read<W: Word>(&mut self, request: Request, reg_addr: *mut W, buf: &mut [W]) {
135 low_level_api::reset_status(crate::pac::$dma_peri, $channel_num); 135 low_level_api::reset_status(crate::pac::$dma_peri, $channel_num);
136 low_level_api::start_transfer( 136 low_level_api::start_transfer(
137 crate::pac::$dma_peri, 137 crate::pac::$dma_peri,
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
index baed24603..05d62ef8f 100644
--- a/embassy-stm32/src/dma/dma.rs
+++ b/embassy-stm32/src/dma/dma.rs
@@ -84,7 +84,7 @@ pub(crate) unsafe fn init() {
84pac::dma_channels! { 84pac::dma_channels! {
85 ($channel_peri:ident, $dma_peri:ident, dma, $channel_num:expr, $dmamux:tt) => { 85 ($channel_peri:ident, $dma_peri:ident, dma, $channel_num:expr, $dmamux:tt) => {
86 impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri { 86 impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {
87 unsafe fn start_write<W: Word>(&mut self, request: Request, buf: &[W], reg_addr: *mut u32) { 87 unsafe fn start_write<W: Word>(&mut self, request: Request, buf: &[W], reg_addr: *mut W) {
88 let isrn = $channel_num as usize / 4; 88 let isrn = $channel_num as usize / 4;
89 let isrbit = $channel_num as usize % 4; 89 let isrbit = $channel_num as usize % 4;
90 low_level_api::reset_status(&crate::pac::$dma_peri, isrn, isrbit); 90 low_level_api::reset_status(&crate::pac::$dma_peri, isrn, isrbit);
@@ -104,7 +104,7 @@ pac::dma_channels! {
104 ) 104 )
105 } 105 }
106 106
107 unsafe fn start_write_repeated<W: Word>(&mut self, request: Request, repeated: W, count: usize, reg_addr: *mut u32) { 107 unsafe fn start_write_repeated<W: Word>(&mut self, request: Request, repeated: W, count: usize, reg_addr: *mut W) {
108 let buf = [repeated]; 108 let buf = [repeated];
109 let isrn = $channel_num as usize / 4; 109 let isrn = $channel_num as usize / 4;
110 let isrbit = $channel_num as usize % 4; 110 let isrbit = $channel_num as usize % 4;
@@ -125,7 +125,7 @@ pac::dma_channels! {
125 ) 125 )
126 } 126 }
127 127
128 unsafe fn start_read<W: Word>(&mut self, request: Request, reg_addr: *mut u32, buf: &mut [W]) { 128 unsafe fn start_read<W: Word>(&mut self, request: Request, reg_addr: *mut W, buf: &mut [W]) {
129 let isrn = $channel_num as usize / 4; 129 let isrn = $channel_num as usize / 4;
130 let isrbit = $channel_num as usize % 4; 130 let isrbit = $channel_num as usize % 4;
131 low_level_api::reset_status(&crate::pac::$dma_peri, isrn, isrbit); 131 low_level_api::reset_status(&crate::pac::$dma_peri, isrn, isrbit);
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index 5e4b5d3de..accc55653 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -30,37 +30,59 @@ pub type Request = ();
30pub(crate) mod sealed { 30pub(crate) mod sealed {
31 use super::*; 31 use super::*;
32 32
33 pub trait Word {}
34
33 pub trait Channel { 35 pub trait Channel {
34 /// Starts this channel for writing a stream of words. 36 /// Starts this channel for writing a stream of words.
35 unsafe fn start_write<W: Word>(&mut self, request: Request, buf: &[W], reg_addr: *mut u32); 37 ///
38 /// Safety:
39 /// - `buf` must be alive for the entire duration of the DMA transfer.
40 /// - `reg_addr` must be a valid peripheral register address to write to.
41 unsafe fn start_write<W: super::Word>(
42 &mut self,
43 request: Request,
44 buf: &[W],
45 reg_addr: *mut W,
46 );
36 47
37 /// Starts this channel for writing a word repeatedly. 48 /// Starts this channel for writing a word repeatedly.
38 unsafe fn start_write_repeated<W: Word>( 49 ///
50 /// Safety:
51 /// - `reg_addr` must be a valid peripheral register address to write to.
52 unsafe fn start_write_repeated<W: super::Word>(
39 &mut self, 53 &mut self,
40 request: Request, 54 request: Request,
41 repeated: W, 55 repeated: W,
42 count: usize, 56 count: usize,
43 reg_addr: *mut u32, 57 reg_addr: *mut W,
44 ); 58 );
45 59
46 /// Starts this channel for reading a stream of words. 60 /// Starts this channel for reading a stream of words.
47 unsafe fn start_read<W: Word>( 61 ///
62 /// Safety:
63 /// - `buf` must be alive for the entire duration of the DMA transfer.
64 /// - `reg_addr` must be a valid peripheral register address to write to.
65 unsafe fn start_read<W: super::Word>(
48 &mut self, 66 &mut self,
49 request: Request, 67 request: Request,
50 reg_addr: *mut u32, 68 reg_addr: *mut W,
51 buf: &mut [W], 69 buf: &mut [W],
52 ); 70 );
53 71
54 /// Stops this channel. 72 /// Requests the channel to stop.
73 /// NOTE: The channel does not immediately stop, you have to wait
74 /// for `is_running() = false`.
55 fn request_stop(&mut self); 75 fn request_stop(&mut self);
56 76
57 /// Returns whether this channel is active or stopped. 77 /// Returns whether this channel is running or stopped.
78 ///
79 /// The channel stops running when it either completes or is manually stopped.
58 fn is_running(&self) -> bool; 80 fn is_running(&self) -> bool;
59 81
60 /// Returns the total number of remaining transfers. 82 /// Returns the total number of remaining transfers.
61 fn remaining_transfers(&mut self) -> u16; 83 fn remaining_transfers(&mut self) -> u16;
62 84
63 /// Sets the waker that is called when this channel completes. 85 /// Sets the waker that is called when this channel stops (either completed or manually stopped)
64 fn set_waker(&mut self, waker: &Waker); 86 fn set_waker(&mut self, waker: &Waker);
65 } 87 }
66} 88}
@@ -70,21 +92,25 @@ pub enum WordSize {
70 TwoBytes, 92 TwoBytes,
71 FourBytes, 93 FourBytes,
72} 94}
73pub trait Word { 95pub trait Word: sealed::Word {
74 fn bits() -> WordSize; 96 fn bits() -> WordSize;
75} 97}
76 98
99impl sealed::Word for u8 {}
77impl Word for u8 { 100impl Word for u8 {
78 fn bits() -> WordSize { 101 fn bits() -> WordSize {
79 WordSize::OneByte 102 WordSize::OneByte
80 } 103 }
81} 104}
82 105
106impl sealed::Word for u16 {}
83impl Word for u16 { 107impl Word for u16 {
84 fn bits() -> WordSize { 108 fn bits() -> WordSize {
85 WordSize::TwoBytes 109 WordSize::TwoBytes
86 } 110 }
87} 111}
112
113impl sealed::Word for u32 {}
88impl Word for u32 { 114impl Word for u32 {
89 fn bits() -> WordSize { 115 fn bits() -> WordSize {
90 WordSize::FourBytes 116 WordSize::FourBytes
@@ -98,7 +124,7 @@ mod transfers {
98 pub fn read<'a, W: Word>( 124 pub fn read<'a, W: Word>(
99 channel: impl Unborrow<Target = impl Channel> + 'a, 125 channel: impl Unborrow<Target = impl Channel> + 'a,
100 request: Request, 126 request: Request,
101 reg_addr: *mut u32, 127 reg_addr: *mut W,
102 buf: &'a mut [W], 128 buf: &'a mut [W],
103 ) -> impl Future<Output = ()> + 'a { 129 ) -> impl Future<Output = ()> + 'a {
104 assert!(buf.len() <= 0xFFFF); 130 assert!(buf.len() <= 0xFFFF);
@@ -117,7 +143,7 @@ mod transfers {
117 channel: impl Unborrow<Target = impl Channel> + 'a, 143 channel: impl Unborrow<Target = impl Channel> + 'a,
118 request: Request, 144 request: Request,
119 buf: &'a [W], 145 buf: &'a [W],
120 reg_addr: *mut u32, 146 reg_addr: *mut W,
121 ) -> impl Future<Output = ()> + 'a { 147 ) -> impl Future<Output = ()> + 'a {
122 assert!(buf.len() <= 0xFFFF); 148 assert!(buf.len() <= 0xFFFF);
123 unborrow!(channel); 149 unborrow!(channel);
@@ -136,7 +162,7 @@ mod transfers {
136 request: Request, 162 request: Request,
137 repeated: W, 163 repeated: W,
138 count: usize, 164 count: usize,
139 reg_addr: *mut u32, 165 reg_addr: *mut W,
140 ) -> impl Future<Output = ()> + 'a { 166 ) -> impl Future<Output = ()> + 'a {
141 unborrow!(channel); 167 unborrow!(channel);
142 168
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index af3ac74bc..94c4d9a7c 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -415,7 +415,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
415 w.set_tcie(true); 415 w.set_tcie(true);
416 } 416 }
417 }); 417 });
418 let dst = regs.txdr().ptr() as *mut u32; 418 let dst = regs.txdr().ptr() as *mut u8;
419 419
420 let ch = &mut self.tx_dma; 420 let ch = &mut self.tx_dma;
421 let request = ch.request(); 421 let request = ch.request();
@@ -508,7 +508,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
508 w.set_rxdmaen(true); 508 w.set_rxdmaen(true);
509 w.set_tcie(true); 509 w.set_tcie(true);
510 }); 510 });
511 let src = regs.rxdr().ptr() as *mut u32; 511 let src = regs.rxdr().ptr() as *mut u8;
512 512
513 let ch = &mut self.rx_dma; 513 let ch = &mut self.rx_dma;
514 let request = ch.request(); 514 let request = ch.request();
diff --git a/embassy-stm32/src/usart/v1.rs b/embassy-stm32/src/usart/v1.rs
index 3a8c1d340..10f87f2dd 100644
--- a/embassy-stm32/src/usart/v1.rs
+++ b/embassy-stm32/src/usart/v1.rs
@@ -77,7 +77,7 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
77 }); 77 });
78 } 78 }
79 let r = self.inner.regs(); 79 let r = self.inner.regs();
80 let dst = r.dr().ptr() as *mut u32; 80 let dst = r.dr().ptr() as *mut u8;
81 crate::dma::write(ch, request, buffer, dst).await; 81 crate::dma::write(ch, request, buffer, dst).await;
82 Ok(()) 82 Ok(())
83 } 83 }
@@ -94,7 +94,7 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
94 }); 94 });
95 } 95 }
96 let r = self.inner.regs(); 96 let r = self.inner.regs();
97 let src = r.dr().ptr() as *mut u32; 97 let src = r.dr().ptr() as *mut u8;
98 crate::dma::read(ch, request, src, buffer).await; 98 crate::dma::read(ch, request, src, buffer).await;
99 Ok(()) 99 Ok(())
100 } 100 }
diff --git a/embassy-stm32/src/usart/v2.rs b/embassy-stm32/src/usart/v2.rs
index cd70afec7..697adf459 100644
--- a/embassy-stm32/src/usart/v2.rs
+++ b/embassy-stm32/src/usart/v2.rs
@@ -87,7 +87,7 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
87 }); 87 });
88 } 88 }
89 let r = self.inner.regs(); 89 let r = self.inner.regs();
90 let dst = r.tdr().ptr() as *mut u32; 90 let dst = r.tdr().ptr() as *mut u8;
91 crate::dma::write(ch, request, buffer, dst).await; 91 crate::dma::write(ch, request, buffer, dst).await;
92 Ok(()) 92 Ok(())
93 } 93 }
@@ -104,7 +104,7 @@ impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
104 }); 104 });
105 } 105 }
106 let r = self.inner.regs(); 106 let r = self.inner.regs();
107 let src = r.rdr().ptr() as *mut u32; 107 let src = r.rdr().ptr() as *mut u8;
108 108
109 crate::dma::read(ch, request, src, buffer).await; 109 crate::dma::read(ch, request, src, buffer).await;
110 Ok(()) 110 Ok(())