Add support for generating PAC for dual cores

* Chips that have multiple cores will be exposed as chipname_corename,
  i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
  and pick the first and only core from the list
* Add support for stm32wl55 chip family

12 files changed, 462 insertions, 89 deletions

diff --git a/.github/workflows/rust.yml b/.github/workflows/rust.yml
index 0585b6d3d..f4105230d 100644
--- a/.github/workflows/rust.yml
+++ b/.github/workflows/rust.yml
@@ -71,7 +71,7 @@ jobs:
             features: stm32f429zi,log
           - package: embassy-stm32
             target: thumbv7em-none-eabi
-            features: stm32h755zi,defmt
+            features: stm32h755zi_cm7,defmt
           - package: embassy-stm32
             target: thumbv7em-none-eabi
             features: stm32l476vg,defmt
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 8b9a00391..682ebaefc 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -239,23 +239,40 @@ stm32h743xg = [ "stm32-metapac/stm32h743xg",]
 stm32h743xi = [ "stm32-metapac/stm32h743xi",]
 stm32h743zg = [ "stm32-metapac/stm32h743zg",]
 stm32h743zi = [ "stm32-metapac/stm32h743zi",]
-stm32h745bg = [ "stm32-metapac/stm32h745bg",]
-stm32h745bi = [ "stm32-metapac/stm32h745bi",]
-stm32h745ig = [ "stm32-metapac/stm32h745ig",]
-stm32h745ii = [ "stm32-metapac/stm32h745ii",]
-stm32h745xg = [ "stm32-metapac/stm32h745xg",]
-stm32h745xi = [ "stm32-metapac/stm32h745xi",]
-stm32h745zg = [ "stm32-metapac/stm32h745zg",]
-stm32h745zi = [ "stm32-metapac/stm32h745zi",]
-stm32h747ag = [ "stm32-metapac/stm32h747ag",]
-stm32h747ai = [ "stm32-metapac/stm32h747ai",]
-stm32h747bg = [ "stm32-metapac/stm32h747bg",]
-stm32h747bi = [ "stm32-metapac/stm32h747bi",]
-stm32h747ig = [ "stm32-metapac/stm32h747ig",]
-stm32h747ii = [ "stm32-metapac/stm32h747ii",]
-stm32h747xg = [ "stm32-metapac/stm32h747xg",]
-stm32h747xi = [ "stm32-metapac/stm32h747xi",]
-stm32h747zi = [ "stm32-metapac/stm32h747zi",]
+stm32h745bg_cm7 = [ "stm32-metapac/stm32h745bg_cm7",]
+stm32h745bg_cm4 = [ "stm32-metapac/stm32h745bg_cm4",]
+stm32h745bi_cm7 = [ "stm32-metapac/stm32h745bi_cm7",]
+stm32h745bi_cm4 = [ "stm32-metapac/stm32h745bi_cm4",]
+stm32h745ig_cm7 = [ "stm32-metapac/stm32h745ig_cm7",]
+stm32h745ig_cm4 = [ "stm32-metapac/stm32h745ig_cm4",]
+stm32h745ii_cm7 = [ "stm32-metapac/stm32h745ii_cm7",]
+stm32h745ii_cm4 = [ "stm32-metapac/stm32h745ii_cm4",]
+stm32h745xg_cm7 = [ "stm32-metapac/stm32h745xg_cm7",]
+stm32h745xg_cm4 = [ "stm32-metapac/stm32h745xg_cm4",]
+stm32h745xi_cm7 = [ "stm32-metapac/stm32h745xi_cm7",]
+stm32h745xi_cm4 = [ "stm32-metapac/stm32h745xi_cm4",]
+stm32h745zg_cm7 = [ "stm32-metapac/stm32h745zg_cm7",]
+stm32h745zg_cm4 = [ "stm32-metapac/stm32h745zg_cm4",]
+stm32h745zi_cm7 = [ "stm32-metapac/stm32h745zi_cm7",]
+stm32h745zi_cm4 = [ "stm32-metapac/stm32h745zi_cm4",]
+stm32h747ag_cm7 = [ "stm32-metapac/stm32h747ag_cm7",]
+stm32h747ag_cm4 = [ "stm32-metapac/stm32h747ag_cm4",]
+stm32h747ai_cm7 = [ "stm32-metapac/stm32h747ai_cm7",]
+stm32h747ai_cm4 = [ "stm32-metapac/stm32h747ai_cm4",]
+stm32h747bg_cm7 = [ "stm32-metapac/stm32h747bg_cm7",]
+stm32h747bg_cm4 = [ "stm32-metapac/stm32h747bg_cm4",]
+stm32h747bi_cm7 = [ "stm32-metapac/stm32h747bi_cm7",]
+stm32h747bi_cm4 = [ "stm32-metapac/stm32h747bi_cm4",]
+stm32h747ig_cm7 = [ "stm32-metapac/stm32h747ig_cm7",]
+stm32h747ig_cm4 = [ "stm32-metapac/stm32h747ig_cm4",]
+stm32h747ii_cm7 = [ "stm32-metapac/stm32h747ii_cm7",]
+stm32h747ii_cm4 = [ "stm32-metapac/stm32h747ii_cm4",]
+stm32h747xg_cm7 = [ "stm32-metapac/stm32h747xg_cm7",]
+stm32h747xg_cm4 = [ "stm32-metapac/stm32h747xg_cm4",]
+stm32h747xi_cm7 = [ "stm32-metapac/stm32h747xi_cm7",]
+stm32h747xi_cm4 = [ "stm32-metapac/stm32h747xi_cm4",]
+stm32h747zi_cm7 = [ "stm32-metapac/stm32h747zi_cm7",]
+stm32h747zi_cm4 = [ "stm32-metapac/stm32h747zi_cm4",]
 stm32h750ib = [ "stm32-metapac/stm32h750ib",]
 stm32h750vb = [ "stm32-metapac/stm32h750vb",]
 stm32h750xb = [ "stm32-metapac/stm32h750xb",]
@@ -266,15 +283,24 @@ stm32h753ii = [ "stm32-metapac/stm32h753ii",]
 stm32h753vi = [ "stm32-metapac/stm32h753vi",]
 stm32h753xi = [ "stm32-metapac/stm32h753xi",]
 stm32h753zi = [ "stm32-metapac/stm32h753zi",]
-stm32h755bi = [ "stm32-metapac/stm32h755bi",]
-stm32h755ii = [ "stm32-metapac/stm32h755ii",]
-stm32h755xi = [ "stm32-metapac/stm32h755xi",]
-stm32h755zi = [ "stm32-metapac/stm32h755zi",]
-stm32h757ai = [ "stm32-metapac/stm32h757ai",]
-stm32h757bi = [ "stm32-metapac/stm32h757bi",]
-stm32h757ii = [ "stm32-metapac/stm32h757ii",]
-stm32h757xi = [ "stm32-metapac/stm32h757xi",]
-stm32h757zi = [ "stm32-metapac/stm32h757zi",]
+stm32h755bi_cm7 = [ "stm32-metapac/stm32h755bi_cm7",]
+stm32h755bi_cm4 = [ "stm32-metapac/stm32h755bi_cm4",]
+stm32h755ii_cm7 = [ "stm32-metapac/stm32h755ii_cm7",]
+stm32h755ii_cm4 = [ "stm32-metapac/stm32h755ii_cm4",]
+stm32h755xi_cm7 = [ "stm32-metapac/stm32h755xi_cm7",]
+stm32h755xi_cm4 = [ "stm32-metapac/stm32h755xi_cm4",]
+stm32h755zi_cm7 = [ "stm32-metapac/stm32h755zi_cm7",]
+stm32h755zi_cm4 = [ "stm32-metapac/stm32h755zi_cm4",]
+stm32h757ai_cm7 = [ "stm32-metapac/stm32h757ai_cm7",]
+stm32h757ai_cm4 = [ "stm32-metapac/stm32h757ai_cm4",]
+stm32h757bi_cm7 = [ "stm32-metapac/stm32h757bi_cm7",]
+stm32h757bi_cm4 = [ "stm32-metapac/stm32h757bi_cm4",]
+stm32h757ii_cm7 = [ "stm32-metapac/stm32h757ii_cm7",]
+stm32h757ii_cm4 = [ "stm32-metapac/stm32h757ii_cm4",]
+stm32h757xi_cm7 = [ "stm32-metapac/stm32h757xi_cm7",]
+stm32h757xi_cm4 = [ "stm32-metapac/stm32h757xi_cm4",]
+stm32h757zi_cm7 = [ "stm32-metapac/stm32h757zi_cm7",]
+stm32h757zi_cm4 = [ "stm32-metapac/stm32h757zi_cm4",]
 stm32h7a3ag = [ "stm32-metapac/stm32h7a3ag",]
 stm32h7a3ai = [ "stm32-metapac/stm32h7a3ai",]
 stm32h7a3ig = [ "stm32-metapac/stm32h7a3ig",]
@@ -554,4 +580,10 @@ stm32wb55vc = [ "stm32-metapac/stm32wb55vc",]
 stm32wb55ve = [ "stm32-metapac/stm32wb55ve",]
 stm32wb55vg = [ "stm32-metapac/stm32wb55vg",]
 stm32wb55vy = [ "stm32-metapac/stm32wb55vy",]
+stm32wl55cc_cm4 = [ "stm32-metapac/stm32wl55cc_cm4",]
+stm32wl55cc_cm0p = [ "stm32-metapac/stm32wl55cc_cm0p",]
+stm32wl55jc_cm4 = [ "stm32-metapac/stm32wl55jc_cm4",]
+stm32wl55jc_cm0p = [ "stm32-metapac/stm32wl55jc_cm0p",]
+stm32wl55uc_cm4 = [ "stm32-metapac/stm32wl55uc_cm4",]
+stm32wl55uc_cm0p = [ "stm32-metapac/stm32wl55uc_cm0p",]
 # END GENERATED FEATURES
diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py
index 779389cac..b9391d309 100644
--- a/embassy-stm32/gen.py
+++ b/embassy-stm32/gen.py
@@ -19,10 +19,17 @@ data_path = '../stm32-data/data'
 try:
     _, chip_name, output_file = sys.argv
 except:
-    raise Exception("Usage: gen.py STM32F429ZI path/to/generated.rs")
+    raise Exception("Usage: gen.py STM32F429ZI_CM0 path/to/generated.rs")
+
+c = chip_name.split('_', 1)
+
+chip_name = c[0].upper()
+core_name = None
+
+if len(c) > 1:
+    core_name = c[1].lower()
 
 # ======= load chip
-chip_name = chip_name.upper()
 with open(f'{data_path}/chips/{chip_name}.yaml', 'r') as f:
     chip = yaml.load(f, Loader=SafeLoader)
 
@@ -41,7 +48,13 @@ with open(output_file, 'w') as f:
     singletons.extend((f'EXTI{x}' for x in range(16)))
     num_dmas = 0
 
-    for (name, peri) in chip['peripherals'].items():
+    core = chip['cores'][0]
+    if core_name != None:
+        for c in chip['cores']:
+            if core_name == c['name']:
+                core = c
+
+    for (name, peri) in core['peripherals'].items():
         if 'block' not in peri:
             continue
 
diff --git a/embassy-stm32/gen_features.py b/embassy-stm32/gen_features.py
index 4c46d602e..10dfd7884 100644
--- a/embassy-stm32/gen_features.py
+++ b/embassy-stm32/gen_features.py
@@ -1,7 +1,13 @@
 import os
 import toml
+import yaml
 from glob import glob
 
+try:
+    from yaml import CSafeLoader as SafeLoader
+except ImportError:
+    from yaml import SafeLoader
+
 abspath = os.path.abspath(__file__)
 dname = os.path.dirname(abspath)
 os.chdir(dname)
@@ -12,6 +18,7 @@ supported_families = [
     'STM32L4',
     'STM32H7',
     'STM32WB55',
+    'STM32WL55',
 ]
 
 # ======= load chip list
@@ -21,7 +28,15 @@ for f in sorted(glob('../stm32-data/data/chips/*.yaml')):
     name = os.path.splitext(os.path.basename(f))[0]
     if any((family in name for family in supported_families)):
         name = name.lower()
-        features[name] = ['stm32-metapac/' + name]
+        # ======= load chip
+        with open(f, 'r') as f:
+            chip = yaml.load(f, Loader=SafeLoader)
+
+        if len(chip['cores']) > 1:
+            for core in chip['cores']:
+                features[name + "_" + core['name']] = ['stm32-metapac/' + name + '_' + core['name']]
+        else:
+            features[name] = ['stm32-metapac/' + name]
 
 # ========= Update Cargo features
 
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 7721c2857..70bf675aa 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -16,13 +16,13 @@ pub struct Clocks {
     #[cfg(any(rcc_l0))]
     pub ahb: Hertz,
 
-    #[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb55))]
+    #[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb55, rcc_wl55))]
     pub ahb1: Hertz,
 
-    #[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb55))]
+    #[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb55, rcc_wl55))]
     pub ahb2: Hertz,
 
-    #[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb55))]
+    #[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb55, rcc_wl55))]
     pub ahb3: Hertz,
 
     #[cfg(any(rcc_h7))]
@@ -62,6 +62,9 @@ cfg_if::cfg_if! {
     } else if #[cfg(rcc_wb55)] {
         mod wb55;
         pub use wb55::*;
+    } else if #[cfg(rcc_wl55)] {
+        mod wl55;
+        pub use wl55::*;
     }
 }
 
diff --git a/embassy-stm32/src/rcc/wl55/mod.rs b/embassy-stm32/src/rcc/wl55/mod.rs
new file mode 100644
index 000000000..2170b7b72
--- /dev/null
+++ b/embassy-stm32/src/rcc/wl55/mod.rs
@@ -0,0 +1,213 @@
+pub use super::types::*;
+use crate::pac;
+use crate::peripherals::{self, RCC};
+use crate::rcc::{get_freqs, set_freqs, Clocks};
+use crate::time::Hertz;
+use crate::time::U32Ext;
+use core::marker::PhantomData;
+use embassy::util::Unborrow;
+use embassy_extras::unborrow;
+
+/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
+/// and with the addition of the init function to configure a system clock.
+
+/// Only the basic setup using the HSE and HSI clocks are supported as of now.
+
+/// HSI speed
+pub const HSI_FREQ: u32 = 16_000_000;
+
+/// System clock mux source
+#[derive(Clone, Copy)]
+pub enum ClockSrc {
+    HSE(Hertz),
+    HSI16,
+}
+
+impl Into<u8> for APBPrescaler {
+    fn into(self) -> u8 {
+        match self {
+            APBPrescaler::NotDivided => 1,
+            APBPrescaler::Div2 => 0x04,
+            APBPrescaler::Div4 => 0x05,
+            APBPrescaler::Div8 => 0x06,
+            APBPrescaler::Div16 => 0x07,
+        }
+    }
+}
+
+impl Into<u8> for AHBPrescaler {
+    fn into(self) -> u8 {
+        match self {
+            AHBPrescaler::NotDivided => 1,
+            AHBPrescaler::Div2 => 0x08,
+            AHBPrescaler::Div4 => 0x09,
+            AHBPrescaler::Div8 => 0x0a,
+            AHBPrescaler::Div16 => 0x0b,
+            AHBPrescaler::Div64 => 0x0c,
+            AHBPrescaler::Div128 => 0x0d,
+            AHBPrescaler::Div256 => 0x0e,
+            AHBPrescaler::Div512 => 0x0f,
+        }
+    }
+}
+
+/// Clocks configutation
+pub struct Config {
+    mux: ClockSrc,
+    ahb_pre: AHBPrescaler,
+    apb1_pre: APBPrescaler,
+    apb2_pre: APBPrescaler,
+}
+
+impl Default for Config {
+    #[inline]
+    fn default() -> Config {
+        Config {
+            mux: ClockSrc::HSI16,
+            ahb_pre: AHBPrescaler::NotDivided,
+            apb1_pre: APBPrescaler::NotDivided,
+            apb2_pre: APBPrescaler::NotDivided,
+        }
+    }
+}
+
+impl Config {
+    #[inline]
+    pub fn clock_src(mut self, mux: ClockSrc) -> Self {
+        self.mux = mux;
+        self
+    }
+
+    #[inline]
+    pub fn ahb_pre(mut self, pre: AHBPrescaler) -> Self {
+        self.ahb_pre = pre;
+        self
+    }
+
+    #[inline]
+    pub fn apb1_pre(mut self, pre: APBPrescaler) -> Self {
+        self.apb1_pre = pre;
+        self
+    }
+
+    #[inline]
+    pub fn apb2_pre(mut self, pre: APBPrescaler) -> Self {
+        self.apb2_pre = pre;
+        self
+    }
+}
+
+/// RCC peripheral
+pub struct Rcc<'d> {
+    _rb: peripherals::RCC,
+    phantom: PhantomData<&'d mut peripherals::RCC>,
+}
+
+impl<'d> Rcc<'d> {
+    pub fn new(rcc: impl Unborrow<Target = peripherals::RCC> + 'd) -> Self {
+        unborrow!(rcc);
+        Self {
+            _rb: rcc,
+            phantom: PhantomData,
+        }
+    }
+
+    // Safety: RCC init must have been called
+    pub fn clocks(&self) -> &'static Clocks {
+        unsafe { get_freqs() }
+    }
+}
+
+/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
+pub trait RccExt {
+    fn freeze(self, config: Config) -> Clocks;
+}
+
+impl RccExt for RCC {
+    #[inline]
+    fn freeze(self, cfgr: Config) -> Clocks {
+        let rcc = pac::RCC;
+        let (sys_clk, sw) = match cfgr.mux {
+            ClockSrc::HSI16 => {
+                // Enable HSI16
+                unsafe {
+                    rcc.cr().write(|w| w.set_hsion(true));
+                    while !rcc.cr().read().hsirdy() {}
+                }
+
+                (HSI_FREQ, 0x01)
+            }
+            ClockSrc::HSE(freq) => {
+                // Enable HSE
+                unsafe {
+                    rcc.cr().write(|w| w.set_hseon(true));
+                    while !rcc.cr().read().hserdy() {}
+                }
+
+                (freq.0, 0x02)
+            }
+        };
+
+        unsafe {
+            rcc.cfgr().modify(|w| {
+                w.set_sw(sw.into());
+                w.set_hpre(cfgr.ahb_pre.into());
+                w.set_ppre1(cfgr.apb1_pre.into());
+                w.set_ppre2(cfgr.apb2_pre.into());
+            });
+        }
+
+        let ahb_freq: u32 = match cfgr.ahb_pre {
+            AHBPrescaler::NotDivided => sys_clk,
+            pre => {
+                let pre: u8 = pre.into();
+                let pre = 1 << (pre as u32 - 7);
+                sys_clk / pre
+            }
+        };
+
+        let (apb1_freq, apb1_tim_freq) = match cfgr.apb1_pre {
+            APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
+            pre => {
+                let pre: u8 = pre.into();
+                let pre: u8 = 1 << (pre - 3);
+                let freq = ahb_freq / pre as u32;
+                (freq, freq * 2)
+            }
+        };
+
+        let (apb2_freq, apb2_tim_freq) = match cfgr.apb2_pre {
+            APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
+            pre => {
+                let pre: u8 = pre.into();
+                let pre: u8 = 1 << (pre - 3);
+                let freq = ahb_freq / (1 << (pre as u8 - 3));
+                (freq, freq * 2)
+            }
+        };
+
+        Clocks {
+            sys: sys_clk.hz(),
+            ahb1: ahb_freq.hz(),
+            ahb2: ahb_freq.hz(),
+            ahb3: ahb_freq.hz(),
+            apb1: apb1_freq.hz(),
+            apb2: apb2_freq.hz(),
+            apb1_tim: apb1_tim_freq.hz(),
+            apb2_tim: apb2_tim_freq.hz(),
+        }
+    }
+}
+
+pub unsafe fn init(config: Config) {
+    let r = <peripherals::RCC as embassy::util::Steal>::steal();
+    let rcc = pac::RCC;
+    rcc.ahb2enr().write(|w| {
+        w.set_gpioaen(true);
+        w.set_gpioben(true);
+        w.set_gpiocen(true);
+        w.set_gpiohen(true);
+    });
+    let clocks = r.freeze(config);
+    set_freqs(clocks);
+}
diff --git a/examples/stm32l0/src/bin/blinky.rs b/examples/stm32l0/src/bin/blinky.rs
index e7433c26f..ab0a2bdb2 100644
--- a/examples/stm32l0/src/bin/blinky.rs
+++ b/examples/stm32l0/src/bin/blinky.rs
@@ -8,7 +8,10 @@
 
 #[path = "../example_common.rs"]
 mod example_common;
-use embassy_stm32::{rcc::*, gpio::{Level, Output}};
+use embassy_stm32::{
+    gpio::{Level, Output},
+    rcc::*,
+};
 use embedded_hal::digital::v2::OutputPin;
 use example_common::*;
 
diff --git a/examples/stm32l0/src/bin/button.rs b/examples/stm32l0/src/bin/button.rs
index 1a2e20b14..04c48112a 100644
--- a/examples/stm32l0/src/bin/button.rs
+++ b/examples/stm32l0/src/bin/button.rs
@@ -8,13 +8,15 @@
 
 #[path = "../example_common.rs"]
 mod example_common;
-use embassy_stm32::{rcc::*, gpio::{Input, Level, Output, Pull}};
+use embassy_stm32::{
+    gpio::{Input, Level, Output, Pull},
+    rcc::*,
+};
 use embedded_hal::digital::v2::{InputPin, OutputPin};
 use example_common::*;
 
 use cortex_m_rt::entry;
 
-
 #[entry]
 fn main() -> ! {
     info!("Hello World!");
diff --git a/stm32-data b/stm32-data
-Subproject 67b2029a7f203e52f6e1f68c71c7d0aacfef579
+Subproject e104fc21fea271a5d407086ac7ff19e448ac1b3
diff --git a/stm32-metapac/Cargo.toml b/stm32-metapac/Cargo.toml
index 4a434b17e..bed772c81 100644
--- a/stm32-metapac/Cargo.toml
+++ b/stm32-metapac/Cargo.toml
@@ -778,23 +778,40 @@ stm32h743xg = []
 stm32h743xi = []
 stm32h743zg = []
 stm32h743zi = []
-stm32h745bg = []
-stm32h745bi = []
-stm32h745ig = []
-stm32h745ii = []
-stm32h745xg = []
-stm32h745xi = []
-stm32h745zg = []
-stm32h745zi = []
-stm32h747ag = []
-stm32h747ai = []
-stm32h747bg = []
-stm32h747bi = []
-stm32h747ig = []
-stm32h747ii = []
-stm32h747xg = []
-stm32h747xi = []
-stm32h747zi = []
+stm32h745bg_cm7 = []
+stm32h745bg_cm4 = []
+stm32h745bi_cm7 = []
+stm32h745bi_cm4 = []
+stm32h745ig_cm7 = []
+stm32h745ig_cm4 = []
+stm32h745ii_cm7 = []
+stm32h745ii_cm4 = []
+stm32h745xg_cm7 = []
+stm32h745xg_cm4 = []
+stm32h745xi_cm7 = []
+stm32h745xi_cm4 = []
+stm32h745zg_cm7 = []
+stm32h745zg_cm4 = []
+stm32h745zi_cm7 = []
+stm32h745zi_cm4 = []
+stm32h747ag_cm7 = []
+stm32h747ag_cm4 = []
+stm32h747ai_cm7 = []
+stm32h747ai_cm4 = []
+stm32h747bg_cm7 = []
+stm32h747bg_cm4 = []
+stm32h747bi_cm7 = []
+stm32h747bi_cm4 = []
+stm32h747ig_cm7 = []
+stm32h747ig_cm4 = []
+stm32h747ii_cm7 = []
+stm32h747ii_cm4 = []
+stm32h747xg_cm7 = []
+stm32h747xg_cm4 = []
+stm32h747xi_cm7 = []
+stm32h747xi_cm4 = []
+stm32h747zi_cm7 = []
+stm32h747zi_cm4 = []
 stm32h750ib = []
 stm32h750vb = []
 stm32h750xb = []
@@ -805,15 +822,24 @@ stm32h753ii = []
 stm32h753vi = []
 stm32h753xi = []
 stm32h753zi = []
-stm32h755bi = []
-stm32h755ii = []
-stm32h755xi = []
-stm32h755zi = []
-stm32h757ai = []
-stm32h757bi = []
-stm32h757ii = []
-stm32h757xi = []
-stm32h757zi = []
+stm32h755bi_cm7 = []
+stm32h755bi_cm4 = []
+stm32h755ii_cm7 = []
+stm32h755ii_cm4 = []
+stm32h755xi_cm7 = []
+stm32h755xi_cm4 = []
+stm32h755zi_cm7 = []
+stm32h755zi_cm4 = []
+stm32h757ai_cm7 = []
+stm32h757ai_cm4 = []
+stm32h757bi_cm7 = []
+stm32h757bi_cm4 = []
+stm32h757ii_cm7 = []
+stm32h757ii_cm4 = []
+stm32h757xi_cm7 = []
+stm32h757xi_cm4 = []
+stm32h757zi_cm7 = []
+stm32h757zi_cm4 = []
 stm32h7a3ag = []
 stm32h7a3ai = []
 stm32h7a3ig = []
@@ -1204,11 +1230,16 @@ stm32wb55ve = []
 stm32wb55vg = []
 stm32wb55vy = []
 stm32wb5mmg = []
-stm32wl54cc = []
-stm32wl54jc = []
-stm32wl55cc = []
-stm32wl55jc = []
-stm32wl55uc = []
+stm32wl54cc_cm4 = []
+stm32wl54cc_cm0p = []
+stm32wl54jc_cm4 = []
+stm32wl54jc_cm0p = []
+stm32wl55cc_cm4 = []
+stm32wl55cc_cm0p = []
+stm32wl55jc_cm4 = []
+stm32wl55jc_cm0p = []
+stm32wl55uc_cm4 = []
+stm32wl55uc_cm0p = []
 stm32wle4c8 = []
 stm32wle4cb = []
 stm32wle4cc = []
diff --git a/stm32-metapac/gen/src/lib.rs b/stm32-metapac/gen/src/lib.rs
index 5a021569c..a5c061009 100644
--- a/stm32-metapac/gen/src/lib.rs
+++ b/stm32-metapac/gen/src/lib.rs
@@ -16,11 +16,16 @@ pub struct Chip {
     pub name: String,
     pub family: String,
     pub line: String,
-    pub core: String,
+    pub cores: Vec<Core>,
     pub flash: u32,
     pub ram: u32,
     pub gpio_af: String,
     pub packages: Vec<Package>,
+}
+
+#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
+pub struct Core {
+    pub name: String,
     pub peripherals: HashMap<String, Peripheral>,
     pub interrupts: HashMap<String, u32>,
 }
@@ -153,13 +158,41 @@ pub fn gen(options: Options) {
     println!("cwd: {:?}", env::current_dir());
 
     let mut all_peripheral_versions: HashSet<(String, String)> = HashSet::new();
+    let mut chip_cores: HashMap<String, Option<String>> = HashMap::new();
 
     for chip_name in &options.chips {
+        let mut s = chip_name.split('_');
+        let chip_name: &str = s.next().unwrap();
+        let core_name: Option<&str> = s.next();
+
+        chip_cores.insert(
+            chip_name.to_string(),
+            core_name.map(|s| s.to_ascii_lowercase().to_string()),
+        );
+
         let chip_path = data_dir.join("chips").join(&format!("{}.yaml", chip_name));
         println!("chip_path: {:?}", chip_path);
         let chip = fs::read(chip_path).unwrap();
         let chip: Chip = serde_yaml::from_slice(&chip).unwrap();
 
+        println!("looking for core {:?}", core_name);
+        let core: Option<&Core> = if let Some(core_name) = core_name {
+            let core_name = core_name.to_ascii_lowercase();
+            let mut c = None;
+            for core in chip.cores.iter() {
+                if core.name == core_name {
+                    c = Some(core);
+                    break;
+                }
+            }
+            c
+        } else {
+            Some(&chip.cores[0])
+        };
+
+        let core = core.unwrap();
+        let core_name = &core.name;
+
         let mut ir = ir::IR::new();
 
         let mut dev = ir::Device {
@@ -168,7 +201,7 @@ pub fn gen(options: Options) {
         };
 
         // Load RCC register for chip
-        let rcc = chip.peripherals.iter().find_map(|(name, p)| {
+        let rcc = core.peripherals.iter().find_map(|(name, p)| {
             if name == "RCC" {
                 p.block.as_ref().map(|block| {
                     let bi = BlockInfo::parse(block);
@@ -189,17 +222,17 @@ pub fn gen(options: Options) {
         let mut peripheral_pins_table: Vec<Vec<String>> = Vec::new();
         let mut peripheral_rcc_table: Vec<Vec<String>> = Vec::new();
 
-        let dma_base = chip
+        let dma_base = core
             .peripherals
             .get(&"DMA".to_string())
-            .unwrap_or_else(|| chip.peripherals.get(&"DMA1".to_string()).unwrap())
+            .unwrap_or_else(|| core.peripherals.get(&"DMA1".to_string()).unwrap())
             .address;
         let dma_stride = 0x400;
 
-        let gpio_base = chip.peripherals.get(&"GPIOA".to_string()).unwrap().address;
+        let gpio_base = core.peripherals.get(&"GPIOA".to_string()).unwrap().address;
         let gpio_stride = 0x400;
 
-        for (name, p) in &chip.peripherals {
+        for (name, p) in &core.peripherals {
             let mut ir_peri = ir::Peripheral {
                 name: name.clone(),
                 array: None,
@@ -338,7 +371,7 @@ pub fn gen(options: Options) {
             dev.peripherals.push(ir_peri);
         }
 
-        for (name, &num) in &chip.interrupts {
+        for (name, &num) in &core.interrupts {
             dev.interrupts.push(ir::Interrupt {
                 name: name.clone(),
                 description: None,
@@ -386,9 +419,17 @@ pub fn gen(options: Options) {
         transform::sort::Sort {}.run(&mut ir).unwrap();
         transform::Sanitize {}.run(&mut ir).unwrap();
 
-        let chip_dir = out_dir
-            .join("src/chips")
-            .join(chip_name.to_ascii_lowercase());
+        let chip_dir = if chip.cores.len() > 1 {
+            out_dir.join("src/chips").join(format!(
+                "{}_{}",
+                chip_name.to_ascii_lowercase(),
+                core_name.to_ascii_lowercase()
+            ))
+        } else {
+            out_dir
+                .join("src/chips")
+                .join(chip_name.to_ascii_lowercase())
+        };
         fs::create_dir_all(&chip_dir).unwrap();
 
         let items = generate::render(&ir, &generate_opts).unwrap();
@@ -403,7 +444,7 @@ pub fn gen(options: Options) {
 
         let mut device_x = String::new();
 
-        for (name, _) in &chip.interrupts {
+        for (name, _) in &core.interrupts {
             write!(
                 &mut device_x,
                 "PROVIDE({} = DefaultHandler);\n",
@@ -462,14 +503,24 @@ pub fn gen(options: Options) {
     let librs = include_bytes!("assets/lib_inner.rs");
     let i = bytes_find(librs, PATHS_MARKER).unwrap();
     let mut paths = String::new();
-    for chip_name in &options.chips {
-        let x = chip_name.to_ascii_lowercase();
-        write!(
-            &mut paths,
-            "#[cfg_attr(feature=\"{}\", path = \"chips/{}/pac.rs\")]",
-            x, x
-        )
-        .unwrap();
+
+    for (chip, cores) in chip_cores.iter() {
+        let x = chip.to_ascii_lowercase();
+        if let Some(c) = cores {
+            write!(
+                &mut paths,
+                "#[cfg_attr(feature=\"{}_{}\", path = \"chips/{}_{}/pac.rs\")]",
+                x, c, x, c
+            )
+            .unwrap();
+        } else {
+            write!(
+                &mut paths,
+                "#[cfg_attr(feature=\"{}\", path = \"chips/{}/pac.rs\")]",
+                x, x
+            )
+            .unwrap();
+        }
     }
     let mut contents: Vec<u8> = Vec::new();
     contents.extend(&librs[..i]);
diff --git a/stm32-metapac/gen_features.py b/stm32-metapac/gen_features.py
index ee92bd763..29cbd85a0 100644
--- a/stm32-metapac/gen_features.py
+++ b/stm32-metapac/gen_features.py
@@ -8,6 +8,11 @@ import toml
 from collections import OrderedDict
 from glob import glob
 
+try:
+    from yaml import CSafeLoader as SafeLoader
+except ImportError:
+    from yaml import SafeLoader
+
 abspath = os.path.abspath(__file__)
 dname = os.path.dirname(abspath)
 os.chdir(dname)
@@ -19,8 +24,13 @@ features = {}
 for f in sorted(glob('../stm32-data/data/chips/*.yaml')):
     # Use the filename to get the chip name. Ultra fast, we don't have to read YAML!
     name = os.path.splitext(os.path.basename(f))[0].lower()
-    features[name] = []
-
+    with open(f, 'r') as f:
+        chip = yaml.load(f, Loader=SafeLoader)
+    if len(chip['cores']) > 1:
+        for core in chip['cores']:
+            features[name + "_" + core['name']] = []
+    else:
+        features[name] = []
 
 # ========= Update Cargo features