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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2023-04-12 01:09:41 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-04-12 01:09:41 +0000 |
| commit | ba8cafb20c2458a2016c7db3efd91d718f1a91b6 (patch) | |
| tree | 8ebbc3930c30533ed85a83addc4fdc04f24ec243 | |
| parent | 201a038134a7863700c3e1c1f55a03b52504d0b2 (diff) | |
| parent | f3699e67b913618276dfec90e6cbf59925f80015 (diff) | |
Merge #1358
1358: Fix typo in derivation of PLLP divisor for STM32F2 family r=Dirbaio a=sgoll
This PR fixes a typo in the derivation of the PLLP divisor for the STM32F2 family.
Fixes #1357
Co-authored-by: Sebastian Goll <[email protected]>
| -rw-r--r-- | embassy-stm32/src/rcc/f2.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-stm32/src/rcc/f2.rs b/embassy-stm32/src/rcc/f2.rs index d543888c1..bcae64d0f 100644 --- a/embassy-stm32/src/rcc/f2.rs +++ b/embassy-stm32/src/rcc/f2.rs | |||
| @@ -148,7 +148,7 @@ impl Into<Pllp> for PLLMainDiv { | |||
| 148 | match self { | 148 | match self { |
| 149 | PLLMainDiv::Div2 => Pllp::DIV2, | 149 | PLLMainDiv::Div2 => Pllp::DIV2, |
| 150 | PLLMainDiv::Div4 => Pllp::DIV4, | 150 | PLLMainDiv::Div4 => Pllp::DIV4, |
| 151 | PLLMainDiv::Div6 => Pllp::DIV8, | 151 | PLLMainDiv::Div6 => Pllp::DIV6, |
| 152 | PLLMainDiv::Div8 => Pllp::DIV8, | 152 | PLLMainDiv::Div8 => Pllp::DIV8, |
| 153 | } | 153 | } |
| 154 | } | 154 | } |
