diff options
| author | xoviat <[email protected]> | 2023-07-31 17:55:25 -0500 |
|---|---|---|
| committer | xoviat <[email protected]> | 2023-07-31 17:55:25 -0500 |
| commit | bbc8424a5b502187d62cb0ff607e1ac0a719c1c4 (patch) | |
| tree | d1422e4559033e9f876b1532f48e5de7812842ba | |
| parent | ffa0c08140be6c90bde9f11e797eda95e4b8331b (diff) | |
stm32/dma: remove trace
| -rw-r--r-- | embassy-stm32/src/dma/ringbuffer.rs | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/embassy-stm32/src/dma/ringbuffer.rs b/embassy-stm32/src/dma/ringbuffer.rs index c3e4f20c0..945c7508c 100644 --- a/embassy-stm32/src/dma/ringbuffer.rs +++ b/embassy-stm32/src/dma/ringbuffer.rs | |||
| @@ -229,14 +229,6 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { | |||
| 229 | pub fn write(&mut self, mut dma: impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), OverrunError> { | 229 | pub fn write(&mut self, mut dma: impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), OverrunError> { |
| 230 | let start = self.pos(dma.get_remaining_transfers()); | 230 | let start = self.pos(dma.get_remaining_transfers()); |
| 231 | if start > self.end { | 231 | if start > self.end { |
| 232 | trace!( | ||
| 233 | "[1]: start, end, len, complete_count: {}, {}, {}, {}", | ||
| 234 | start, | ||
| 235 | self.end, | ||
| 236 | buf.len(), | ||
| 237 | dma.get_complete_count() | ||
| 238 | ); | ||
| 239 | |||
| 240 | // The occupied portion in the ring buffer DOES wrap | 232 | // The occupied portion in the ring buffer DOES wrap |
| 241 | let len = self.copy_from(buf, self.end..start); | 233 | let len = self.copy_from(buf, self.end..start); |
| 242 | 234 | ||
| @@ -253,24 +245,8 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { | |||
| 253 | Ok((len, self.cap() - (start - self.end))) | 245 | Ok((len, self.cap() - (start - self.end))) |
| 254 | } | 246 | } |
| 255 | } else if start == self.end && dma.get_complete_count() == 0 { | 247 | } else if start == self.end && dma.get_complete_count() == 0 { |
| 256 | trace!( | ||
| 257 | "[2]: start, end, len, complete_count: {}, {}, {}, {}", | ||
| 258 | start, | ||
| 259 | self.end, | ||
| 260 | buf.len(), | ||
| 261 | dma.get_complete_count() | ||
| 262 | ); | ||
| 263 | |||
| 264 | Ok((0, 0)) | 248 | Ok((0, 0)) |
| 265 | } else if start <= self.end && self.end + buf.len() < self.cap() { | 249 | } else if start <= self.end && self.end + buf.len() < self.cap() { |
| 266 | trace!( | ||
| 267 | "[3]: start, end, len, complete_count: {}, {}, {}, {}", | ||
| 268 | start, | ||
| 269 | self.end, | ||
| 270 | buf.len(), | ||
| 271 | dma.get_complete_count() | ||
| 272 | ); | ||
| 273 | |||
| 274 | // The occupied portion in the ring buffer DOES NOT wrap | 250 | // The occupied portion in the ring buffer DOES NOT wrap |
| 275 | // and copying elements into the buffer WILL NOT cause it to | 251 | // and copying elements into the buffer WILL NOT cause it to |
| 276 | 252 | ||
| @@ -289,14 +265,6 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { | |||
| 289 | Ok((len, self.cap() - (self.end - start))) | 265 | Ok((len, self.cap() - (self.end - start))) |
| 290 | } | 266 | } |
| 291 | } else { | 267 | } else { |
| 292 | trace!( | ||
| 293 | "[4]: start, end, len, complete_count: {}, {}, {}, {}", | ||
| 294 | start, | ||
| 295 | self.end, | ||
| 296 | buf.len(), | ||
| 297 | dma.get_complete_count() | ||
| 298 | ); | ||
| 299 | |||
| 300 | // The occupied portion in the ring buffer DOES NOT wrap | 268 | // The occupied portion in the ring buffer DOES NOT wrap |
| 301 | // and copying elements into the buffer WILL cause it to | 269 | // and copying elements into the buffer WILL cause it to |
| 302 | 270 | ||
