Merge pull request #4647 from WyliodrinEmbeddedIoT/embassy-dev

lpc55: move to nxp-pac

11 files changed, 462 insertions, 989 deletions

diff --git a/embassy-nxp/CHANGELOG.md b/embassy-nxp/CHANGELOG.md
index 7042ad14c..ab97c4185 100644
--- a/embassy-nxp/CHANGELOG.md
+++ b/embassy-nxp/CHANGELOG.md
@@ -7,5 +7,5 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 <!-- next-header -->
 ## Unreleased - ReleaseDate
-
+- Moved NXP LPC55S69 from `lpc55-pac` to `nxp-pac`
 - First release with changelog.
diff --git a/embassy-nxp/Cargo.toml b/embassy-nxp/Cargo.toml
index ab0bfbfd7..455915f29 100644
--- a/embassy-nxp/Cargo.toml
+++ b/embassy-nxp/Cargo.toml
@@ -7,7 +7,7 @@ publish = false
 
 [package.metadata.embassy]
 build = [
-    {target = "thumbv8m.main-none-eabihf", features = ["defmt", "lpc55"]},
+    {target = "thumbv8m.main-none-eabihf", features = ["defmt", "lpc55-core0"]},
     {target = "thumbv7em-none-eabihf", features = ["defmt", "mimxrt1011", "rt", "time-driver-pit"]},
     {target = "thumbv7em-none-eabihf", features = ["defmt", "mimxrt1062", "rt", "time-driver-pit"]},
 ]
@@ -18,7 +18,7 @@ src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-nxp/s
 features = ["defmt", "unstable-pac" ] # TODO: Add time-driver-any, as both lpc55 and mimxrt1xxx use different drivers.
 
 flavors = [
-    { regex_feature = "lpc55", target = "thumbv8m.main-none-eabihf" },
+    { regex_feature = "lpc55-core0", target = "thumbv8m.main-none-eabihf" },
     { regex_feature = "mimxrt.*", target = "thumbv7em-none-eabihf" },
 ]
 
@@ -36,21 +36,20 @@ embassy-time-queue-utils = { version = "0.3.0", path = "../embassy-time-queue-ut
 embedded-io = "0.6.1"
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
 ## Chip dependencies
-lpc55-pac = { version = "0.5.0", optional = true }
-nxp-pac = { version = "0.1.0", optional = true, git = "https://github.com/i509VCB/nxp-pac", rev = "be4dd0936c20d5897364a381b1d95a99514c1e7e" }
+nxp-pac = { version = "0.1.0", optional = true, git = "https://github.com/i509VCB/nxp-pac", rev = "b736e3038254d593024aaa1a5a7b1f95a5728538"}
 
 imxrt-rt = { version = "0.1.7", optional = true, features = ["device"] }
 
 [build-dependencies]
 cfg_aliases = "0.2.1"
-nxp-pac = { version = "0.1.0", git = "https://github.com/i509VCB/nxp-pac", rev = "be4dd0936c20d5897364a381b1d95a99514c1e7e", features = ["metadata"], optional = true }
+nxp-pac = { version = "0.1.0", git = "https://github.com/i509VCB/nxp-pac", rev = "b736e3038254d593024aaa1a5a7b1f95a5728538", features = ["metadata"], optional = true }
 proc-macro2 = "1.0.95"
 quote = "1.0.15"
 
 [features]
 default = ["rt"]
 # Enable PACs as optional dependencies, since some chip families will use different pac crates (temporarily).
-rt = ["lpc55-pac?/rt", "nxp-pac?/rt"]
+rt = ["nxp-pac?/rt"]
 
 ## Enable [defmt support](https://docs.rs/defmt) and enables `defmt` debug-log messages and formatting in embassy drivers.
 defmt = ["dep:defmt", "embassy-hal-internal/defmt", "embassy-sync/defmt"]
@@ -79,6 +78,6 @@ _rt1xxx = []
 _time_driver = ["dep:embassy-time-driver", "dep:embassy-time-queue-utils"]
 
 #! ### Chip selection features
-lpc55 = ["dep:lpc55-pac"]
+lpc55-core0 = ["nxp-pac/lpc55s69_cm33_core0"]
 mimxrt1011 = ["nxp-pac/mimxrt1011", "_rt1xxx", "dep:imxrt-rt"]
 mimxrt1062 = ["nxp-pac/mimxrt1062", "_rt1xxx", "dep:imxrt-rt"]
diff --git a/embassy-nxp/src/chips/lpc55.rs b/embassy-nxp/src/chips/lpc55.rs
index e168ced00..711bff3e7 100644
--- a/embassy-nxp/src/chips/lpc55.rs
+++ b/embassy-nxp/src/chips/lpc55.rs
@@ -1,4 +1,4 @@
-pub use lpc55_pac as pac;
+pub use nxp_pac as pac;
 
 embassy_hal_internal::peripherals! {
     // External pins. These are not only GPIOs, they are multi-purpose pins and can be used by other
diff --git a/embassy-nxp/src/gpio.rs b/embassy-nxp/src/gpio.rs
index 3049cc12d..717b38d96 100644
--- a/embassy-nxp/src/gpio.rs
+++ b/embassy-nxp/src/gpio.rs
@@ -1,7 +1,7 @@
 //! General purpose input/output (GPIO) driver.
 #![macro_use]
 
-#[cfg_attr(feature = "lpc55", path = "./gpio/lpc55.rs")]
+#[cfg_attr(feature = "lpc55-core0", path = "./gpio/lpc55.rs")]
 #[cfg_attr(rt1xxx, path = "./gpio/rt1xxx.rs")]
 mod inner;
 pub use inner::*;
diff --git a/embassy-nxp/src/gpio/lpc55.rs b/embassy-nxp/src/gpio/lpc55.rs
index 8f407bb3a..36ea99d21 100644
--- a/embassy-nxp/src/gpio/lpc55.rs
+++ b/embassy-nxp/src/gpio/lpc55.rs
@@ -1,12 +1,17 @@
 use embassy_hal_internal::{impl_peripheral, PeripheralType};
 
+use crate::pac::iocon::vals::{PioDigimode, PioMode};
+use crate::pac::{GPIO, IOCON, SYSCON};
 use crate::{peripherals, Peri};
 
 pub(crate) fn init() {
     // Enable clocks for GPIO, PINT, and IOCON
-    syscon_reg()
-        .ahbclkctrl0
-        .modify(|_, w| w.gpio0().enable().gpio1().enable().mux().enable().iocon().enable());
+    SYSCON.ahbclkctrl0().modify(|w| {
+        w.set_gpio0(true);
+        w.set_gpio1(true);
+        w.set_mux(true);
+        w.set_iocon(true);
+    });
     info!("GPIO initialized");
 }
 
@@ -59,21 +64,24 @@ impl<'d> Output<'d> {
     }
 
     pub fn set_high(&mut self) {
-        gpio_reg().set[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
+        GPIO.set(self.pin.pin_bank() as usize)
+            .write(|w| w.set_setp(self.pin.bit()));
     }
 
     pub fn set_low(&mut self) {
-        gpio_reg().clr[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
+        GPIO.clr(self.pin.pin_bank() as usize)
+            .write(|w| w.set_clrp(self.pin.bit()));
     }
 
     pub fn toggle(&mut self) {
-        gpio_reg().not[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
+        GPIO.not(self.pin.pin_bank() as usize)
+            .write(|w| w.set_notp(self.pin.bit()));
     }
 
     /// Get the current output level of the pin. Note that the value returned by this function is
     /// the voltage level reported by the pin, not the value set by the output driver.
     pub fn level(&self) -> Level {
-        let bits = gpio_reg().pin[self.pin.pin_bank() as usize].read().bits();
+        let bits = GPIO.pin(self.pin.pin_bank() as usize).read().port();
         if bits & self.pin.bit() != 0 {
             Level::High
         } else {
@@ -101,18 +109,18 @@ impl<'d> Input<'d> {
 
     /// Set the pull configuration for the pin. To disable the pull, use [Pull::None].
     pub fn set_pull(&mut self, pull: Pull) {
-        match_iocon!(register, iocon_reg(), self.pin.pin_bank(), self.pin.pin_number(), {
-            register.modify(|_, w| match pull {
-                Pull::None => w.mode().inactive(),
-                Pull::Up => w.mode().pull_up(),
-                Pull::Down => w.mode().pull_down(),
+        match_iocon!(register, self.pin.pin_bank(), self.pin.pin_number(), {
+            register.modify(|w| match pull {
+                Pull::None => w.set_mode(PioMode::INACTIVE),
+                Pull::Up => w.set_mode(PioMode::PULL_UP),
+                Pull::Down => w.set_mode(PioMode::PULL_DOWN),
             });
         });
     }
 
     /// Get the current input level of the pin.
     pub fn read(&self) -> Level {
-        let bits = gpio_reg().pin[self.pin.pin_bank() as usize].read().bits();
+        let bits = GPIO.pin(self.pin.pin_bank() as usize).read().port();
         if bits & self.pin.bit() != 0 {
             Level::High
         } else {
@@ -188,8 +196,8 @@ impl<'d> Flex<'d> {
     /// Set the pin to digital mode. This is required for using a pin as a GPIO pin. The default
     /// setting for pins is (usually) non-digital.
     fn set_as_digital(&mut self) {
-        match_iocon!(register, iocon_reg(), self.pin_bank(), self.pin_number(), {
-            register.modify(|_, w| w.digimode().digital());
+        match_iocon!(register, self.pin_bank(), self.pin_number(), {
+            register.modify(|w| w.set_digimode(PioDigimode::DIGITAL));
         });
     }
 
@@ -197,12 +205,14 @@ impl<'d> Flex<'d> {
     /// function handles itself.
     pub fn set_as_output(&mut self) {
         self.set_as_digital();
-        gpio_reg().dirset[self.pin.pin_bank() as usize].write(|w| unsafe { w.dirsetp().bits(self.bit()) })
+        GPIO.dirset(self.pin.pin_bank() as usize)
+            .write(|w| w.set_dirsetp(self.bit()))
     }
 
     pub fn set_as_input(&mut self) {
         self.set_as_digital();
-        gpio_reg().dirclr[self.pin.pin_bank() as usize].write(|w| unsafe { w.dirclrp().bits(self.bit()) })
+        GPIO.dirclr(self.pin.pin_bank() as usize)
+            .write(|w| w.set_dirclrp(self.bit()))
     }
 }
 
@@ -262,52 +272,6 @@ impl SealedPin for AnyPin {
     }
 }
 
-/// Get the GPIO register block. This is used to configure all GPIO pins.
-///
-/// # Safety
-/// Due to the type system of peripherals, access to the settings of a single pin is possible only
-/// by a single thread at a time. Read/Write operations on a single registers are NOT atomic. You
-/// must ensure that the GPIO registers are not accessed concurrently by multiple threads.
-pub(crate) fn gpio_reg() -> &'static lpc55_pac::gpio::RegisterBlock {
-    unsafe { &*lpc55_pac::GPIO::ptr() }
-}
-
-/// Get the IOCON register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn iocon_reg() -> &'static lpc55_pac::iocon::RegisterBlock {
-    unsafe { &*lpc55_pac::IOCON::ptr() }
-}
-
-/// Get the INPUTMUX register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn inputmux_reg() -> &'static lpc55_pac::inputmux::RegisterBlock {
-    unsafe { &*lpc55_pac::INPUTMUX::ptr() }
-}
-
-/// Get the SYSCON register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn syscon_reg() -> &'static lpc55_pac::syscon::RegisterBlock {
-    unsafe { &*lpc55_pac::SYSCON::ptr() }
-}
-
-/// Get the PINT register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn pint_reg() -> &'static lpc55_pac::pint::RegisterBlock {
-    unsafe { &*lpc55_pac::PINT::ptr() }
-}
-
 /// Match the pin bank and number of a pin to the corresponding IOCON register.
 ///
 /// # Example
@@ -316,270 +280,26 @@ pub(crate) fn pint_reg() -> &'static lpc55_pac::pint::RegisterBlock {
 /// use embassy_nxp::pac_utils::{iocon_reg, match_iocon};
 ///
 /// // Make pin PIO1_6 digital and set it to pull-down mode.
-/// match_iocon!(register, iocon_reg(), Bank::Bank1, 6, {
-///     register.modify(|_, w| w.mode().pull_down().digimode().digital());
+/// match_iocon!(register, Bank::Bank1, 6, {
+///     register.modify(|w|{
+///         w.set_mode(PioMode::PULL_DOWN);
+///         w.set_digimode(PioDigimode::DIGITAL);
+///
+///     }
 /// });
 /// ```
 macro_rules! match_iocon {
-    ($register:ident, $iocon_register:expr, $pin_bank:expr, $pin_number:expr, $action:expr) => {
-        match ($pin_bank, $pin_number) {
-            (Bank::Bank0, 0) => {
-                let $register = &($iocon_register).pio0_0;
-                $action;
-            }
-            (Bank::Bank0, 1) => {
-                let $register = &($iocon_register).pio0_1;
-                $action;
-            }
-            (Bank::Bank0, 2) => {
-                let $register = &($iocon_register).pio0_2;
-                $action;
-            }
-            (Bank::Bank0, 3) => {
-                let $register = &($iocon_register).pio0_3;
-                $action;
-            }
-            (Bank::Bank0, 4) => {
-                let $register = &($iocon_register).pio0_4;
-                $action;
-            }
-            (Bank::Bank0, 5) => {
-                let $register = &($iocon_register).pio0_5;
-                $action;
-            }
-            (Bank::Bank0, 6) => {
-                let $register = &($iocon_register).pio0_6;
-                $action;
-            }
-            (Bank::Bank0, 7) => {
-                let $register = &($iocon_register).pio0_7;
-                $action;
-            }
-            (Bank::Bank0, 8) => {
-                let $register = &($iocon_register).pio0_8;
-                $action;
-            }
-            (Bank::Bank0, 9) => {
-                let $register = &($iocon_register).pio0_9;
-                $action;
-            }
-            (Bank::Bank0, 10) => {
-                let $register = &($iocon_register).pio0_10;
+    ($register:ident, $pin_bank:expr, $pin_number:expr, $action:expr) => {
+        match $pin_bank {
+            Bank::Bank0 => {
+                let $register = IOCON.pio0($pin_number as usize);
                 $action;
             }
-            (Bank::Bank0, 11) => {
-                let $register = &($iocon_register).pio0_11;
-                $action;
-            }
-            (Bank::Bank0, 12) => {
-                let $register = &($iocon_register).pio0_12;
-                $action;
-            }
-            (Bank::Bank0, 13) => {
-                let $register = &($iocon_register).pio0_13;
-                $action;
-            }
-            (Bank::Bank0, 14) => {
-                let $register = &($iocon_register).pio0_14;
-                $action;
-            }
-            (Bank::Bank0, 15) => {
-                let $register = &($iocon_register).pio0_15;
-                $action;
-            }
-            (Bank::Bank0, 16) => {
-                let $register = &($iocon_register).pio0_16;
-                $action;
-            }
-            (Bank::Bank0, 17) => {
-                let $register = &($iocon_register).pio0_17;
-                $action;
-            }
-            (Bank::Bank0, 18) => {
-                let $register = &($iocon_register).pio0_18;
-                $action;
-            }
-            (Bank::Bank0, 19) => {
-                let $register = &($iocon_register).pio0_19;
-                $action;
-            }
-            (Bank::Bank0, 20) => {
-                let $register = &($iocon_register).pio0_20;
-                $action;
-            }
-            (Bank::Bank0, 21) => {
-                let $register = &($iocon_register).pio0_21;
-                $action;
-            }
-            (Bank::Bank0, 22) => {
-                let $register = &($iocon_register).pio0_22;
-                $action;
-            }
-            (Bank::Bank0, 23) => {
-                let $register = &($iocon_register).pio0_23;
-                $action;
-            }
-            (Bank::Bank0, 24) => {
-                let $register = &($iocon_register).pio0_24;
-                $action;
-            }
-            (Bank::Bank0, 25) => {
-                let $register = &($iocon_register).pio0_25;
-                $action;
-            }
-            (Bank::Bank0, 26) => {
-                let $register = &($iocon_register).pio0_26;
-                $action;
-            }
-            (Bank::Bank0, 27) => {
-                let $register = &($iocon_register).pio0_27;
-                $action;
-            }
-            (Bank::Bank0, 28) => {
-                let $register = &($iocon_register).pio0_28;
-                $action;
-            }
-            (Bank::Bank0, 29) => {
-                let $register = &($iocon_register).pio0_29;
-                $action;
-            }
-            (Bank::Bank0, 30) => {
-                let $register = &($iocon_register).pio0_30;
-                $action;
-            }
-            (Bank::Bank0, 31) => {
-                let $register = &($iocon_register).pio0_31;
-                $action;
-            }
-            (Bank::Bank1, 0) => {
-                let $register = &($iocon_register).pio1_0;
-                $action;
-            }
-            (Bank::Bank1, 1) => {
-                let $register = &($iocon_register).pio1_1;
-                $action;
-            }
-            (Bank::Bank1, 2) => {
-                let $register = &($iocon_register).pio1_2;
-                $action;
-            }
-            (Bank::Bank1, 3) => {
-                let $register = &($iocon_register).pio1_3;
-                $action;
-            }
-            (Bank::Bank1, 4) => {
-                let $register = &($iocon_register).pio1_4;
-                $action;
-            }
-            (Bank::Bank1, 5) => {
-                let $register = &($iocon_register).pio1_5;
-                $action;
-            }
-            (Bank::Bank1, 6) => {
-                let $register = &($iocon_register).pio1_6;
-                $action;
-            }
-            (Bank::Bank1, 7) => {
-                let $register = &($iocon_register).pio1_7;
-                $action;
-            }
-            (Bank::Bank1, 8) => {
-                let $register = &($iocon_register).pio1_8;
-                $action;
-            }
-            (Bank::Bank1, 9) => {
-                let $register = &($iocon_register).pio1_9;
-                $action;
-            }
-            (Bank::Bank1, 10) => {
-                let $register = &($iocon_register).pio1_10;
-                $action;
-            }
-            (Bank::Bank1, 11) => {
-                let $register = &($iocon_register).pio1_11;
-                $action;
-            }
-            (Bank::Bank1, 12) => {
-                let $register = &($iocon_register).pio1_12;
-                $action;
-            }
-            (Bank::Bank1, 13) => {
-                let $register = &($iocon_register).pio1_13;
-                $action;
-            }
-            (Bank::Bank1, 14) => {
-                let $register = &($iocon_register).pio1_14;
-                $action;
-            }
-            (Bank::Bank1, 15) => {
-                let $register = &($iocon_register).pio1_15;
-                $action;
-            }
-            (Bank::Bank1, 16) => {
-                let $register = &($iocon_register).pio1_16;
-                $action;
-            }
-            (Bank::Bank1, 17) => {
-                let $register = &($iocon_register).pio1_17;
-                $action;
-            }
-            (Bank::Bank1, 18) => {
-                let $register = &($iocon_register).pio1_18;
-                $action;
-            }
-            (Bank::Bank1, 19) => {
-                let $register = &($iocon_register).pio1_19;
-                $action;
-            }
-            (Bank::Bank1, 20) => {
-                let $register = &($iocon_register).pio1_20;
-                $action;
-            }
-            (Bank::Bank1, 21) => {
-                let $register = &($iocon_register).pio1_21;
-                $action;
-            }
-            (Bank::Bank1, 22) => {
-                let $register = &($iocon_register).pio1_22;
-                $action;
-            }
-            (Bank::Bank1, 23) => {
-                let $register = &($iocon_register).pio1_23;
-                $action;
-            }
-            (Bank::Bank1, 24) => {
-                let $register = &($iocon_register).pio1_24;
-                $action;
-            }
-            (Bank::Bank1, 25) => {
-                let $register = &($iocon_register).pio1_25;
-                $action;
-            }
-            (Bank::Bank1, 26) => {
-                let $register = &($iocon_register).pio1_26;
-                $action;
-            }
-            (Bank::Bank1, 27) => {
-                let $register = &($iocon_register).pio1_27;
-                $action;
-            }
-            (Bank::Bank1, 28) => {
-                let $register = &($iocon_register).pio1_28;
-                $action;
-            }
-            (Bank::Bank1, 29) => {
-                let $register = &($iocon_register).pio1_29;
-                $action;
-            }
-            (Bank::Bank1, 30) => {
-                let $register = &($iocon_register).pio1_30;
-                $action;
-            }
-            (Bank::Bank1, 31) => {
-                let $register = &($iocon_register).pio1_31;
+
+            Bank::Bank1 => {
+                let $register = IOCON.pio1($pin_number as usize);
                 $action;
             }
-            _ => unreachable!(),
         }
     };
 }
diff --git a/embassy-nxp/src/lib.rs b/embassy-nxp/src/lib.rs
index 3fcb14b7e..74142a10b 100644
--- a/embassy-nxp/src/lib.rs
+++ b/embassy-nxp/src/lib.rs
@@ -4,9 +4,9 @@
 pub(crate) mod fmt;
 
 pub mod gpio;
-#[cfg(feature = "lpc55")]
+#[cfg(feature = "lpc55-core0")]
 pub mod pint;
-#[cfg(feature = "lpc55")]
+#[cfg(feature = "lpc55-core0")]
 pub mod usart;
 
 #[cfg(feature = "_time_driver")]
@@ -15,7 +15,7 @@ pub mod usart;
 mod time_driver;
 
 // This mod MUST go last, so that it sees all the `impl_foo!` macros
-#[cfg_attr(feature = "lpc55", path = "chips/lpc55.rs")]
+#[cfg_attr(feature = "lpc55-core0", path = "chips/lpc55.rs")]
 #[cfg_attr(feature = "mimxrt1011", path = "chips/mimxrt1011.rs")]
 #[cfg_attr(feature = "mimxrt1062", path = "chips/mimxrt1062.rs")]
 mod chip;
@@ -83,10 +83,10 @@ pub fn init(_config: config::Config) -> Peripherals {
         pac::CCM.ccgr6().modify(|v| v.set_cg0(1));
     }
 
-    #[cfg(any(feature = "lpc55", rt1xxx))]
+    #[cfg(any(feature = "lpc55-core0", rt1xxx))]
     gpio::init();
 
-    #[cfg(feature = "lpc55")]
+    #[cfg(feature = "lpc55-core0")]
     pint::init();
 
     #[cfg(feature = "_time_driver")]
diff --git a/embassy-nxp/src/pint.rs b/embassy-nxp/src/pint.rs
index ff414b4e6..e594aaa6a 100644
--- a/embassy-nxp/src/pint.rs
+++ b/embassy-nxp/src/pint.rs
@@ -5,10 +5,11 @@ use core::pin::Pin as FuturePin;
 use core::task::{Context, Poll};
 
 use critical_section::Mutex;
+use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_sync::waitqueue::AtomicWaker;
 
-use crate::gpio::{self, inputmux_reg, pint_reg, syscon_reg, AnyPin, Level, SealedPin};
-use crate::pac::interrupt;
+use crate::gpio::{self, AnyPin, Level, SealedPin};
+use crate::pac::{interrupt, INPUTMUX, PINT, SYSCON};
 use crate::Peri;
 
 struct PinInterrupt {
@@ -88,18 +89,18 @@ enum InterruptOn {
 }
 
 pub(crate) fn init() {
-    syscon_reg().ahbclkctrl0.modify(|_, w| w.pint().enable());
+    SYSCON.ahbclkctrl0().modify(|w| w.set_pint(true));
 
     // Enable interrupts
     unsafe {
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT0);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT1);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT2);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT3);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT4);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT5);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT6);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT7);
+        interrupt::PIN_INT0.enable();
+        interrupt::PIN_INT1.enable();
+        interrupt::PIN_INT2.enable();
+        interrupt::PIN_INT3.enable();
+        interrupt::PIN_INT4.enable();
+        interrupt::PIN_INT5.enable();
+        interrupt::PIN_INT6.enable();
+        interrupt::PIN_INT7.enable();
     };
 
     info!("Pin interrupts initialized");
@@ -119,24 +120,19 @@ impl<'d> InputFuture<'d> {
         let interrupt_number = next_available_interrupt()?;
 
         // Clear interrupt, just in case
-        pint_reg()
-            .rise
-            .write(|w| unsafe { w.rdet().bits(1 << interrupt_number) });
-        pint_reg()
-            .fall
-            .write(|w| unsafe { w.fdet().bits(1 << interrupt_number) });
+        PINT.rise().write(|w| w.set_rdet(1 << interrupt_number));
+        PINT.fall().write(|w| w.set_fdet(1 << interrupt_number));
 
         // Enable input multiplexing on pin interrupt register 0 for pin (32*bank + pin_number)
-        inputmux_reg().pintsel[interrupt_number]
-            .write(|w| unsafe { w.intpin().bits(32 * pin.pin_bank() as u8 + pin.pin_number()) });
+        INPUTMUX
+            .pintsel(interrupt_number as usize)
+            .write(|w| w.set_intpin(32 * pin.pin_bank() as u8 + pin.pin_number()));
 
         match interrupt_on {
             InterruptOn::Level(level) => {
                 // Set pin interrupt register to edge sensitive or level sensitive
                 // 0 = edge sensitive, 1 = level sensitive
-                pint_reg()
-                    .isel
-                    .modify(|r, w| unsafe { w.bits(r.bits() | (1 << interrupt_number)) });
+                PINT.isel().modify(|w| w.set_pmode(w.pmode() | (1 << interrupt_number)));
 
                 // Enable level interrupt.
                 //
@@ -144,63 +140,44 @@ impl<'d> InputFuture<'d> {
                 // is activated.
 
                 // 0 = no-op, 1 = enable
-                pint_reg()
-                    .sienr
-                    .write(|w| unsafe { w.setenrl().bits(1 << interrupt_number) });
+                PINT.sienr().write(|w| w.set_setenrl(1 << interrupt_number));
 
                 // Set active level
                 match level {
                     Level::Low => {
                         // 0 = no-op, 1 = select LOW
-                        pint_reg()
-                            .cienf
-                            .write(|w| unsafe { w.cenaf().bits(1 << interrupt_number) });
+                        PINT.cienf().write(|w| w.set_cenaf(1 << interrupt_number));
                     }
                     Level::High => {
                         // 0 = no-op, 1 = select HIGH
-                        pint_reg()
-                            .sienf
-                            .write(|w| unsafe { w.setenaf().bits(1 << interrupt_number) });
+                        PINT.sienf().write(|w| w.set_setenaf(1 << interrupt_number));
                     }
                 }
             }
             InterruptOn::Edge(edge) => {
                 // Set pin interrupt register to edge sensitive or level sensitive
                 // 0 = edge sensitive, 1 = level sensitive
-                pint_reg()
-                    .isel
-                    .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << interrupt_number)) });
+                PINT.isel()
+                    .modify(|w| w.set_pmode(w.pmode() & !(1 << interrupt_number)));
 
                 // Enable rising/falling edge detection
                 match edge {
                     Edge::Rising => {
                         // 0 = no-op, 1 = enable rising edge
-                        pint_reg()
-                            .sienr
-                            .write(|w| unsafe { w.setenrl().bits(1 << interrupt_number) });
+                        PINT.sienr().write(|w| w.set_setenrl(1 << interrupt_number));
                         // 0 = no-op, 1 = disable falling edge
-                        pint_reg()
-                            .cienf
-                            .write(|w| unsafe { w.cenaf().bits(1 << interrupt_number) });
+                        PINT.cienf().write(|w| w.set_cenaf(1 << interrupt_number));
                     }
                     Edge::Falling => {
                         // 0 = no-op, 1 = enable falling edge
-                        pint_reg()
-                            .sienf
-                            .write(|w| unsafe { w.setenaf().bits(1 << interrupt_number) });
+                        PINT.sienf().write(|w| w.set_setenaf(1 << interrupt_number));
                         // 0 = no-op, 1 = disable rising edge
-                        pint_reg()
-                            .cienr
-                            .write(|w| unsafe { w.cenrl().bits(1 << interrupt_number) });
+                        PINT.cienr().write(|w| w.set_cenrl(1 << interrupt_number));
                     }
                     Edge::Both => {
                         // 0 = no-op, 1 = enable
-                        pint_reg()
-                            .sienr
-                            .write(|w| unsafe { w.setenrl().bits(1 << interrupt_number) });
-                        pint_reg()
-                            .sienf
-                            .write(|w| unsafe { w.setenaf().bits(1 << interrupt_number) });
+                        PINT.sienr().write(|w| w.set_setenrl(1 << interrupt_number));
+                        PINT.sienf().write(|w| w.set_setenaf(1 << interrupt_number));
                     }
                 }
             }
@@ -239,12 +216,8 @@ impl<'d> Drop for InputFuture<'d> {
 
         // Disable pin interrupt
         // 0 = no-op, 1 = disable
-        pint_reg()
-            .cienr
-            .write(|w| unsafe { w.cenrl().bits(1 << interrupt_number) });
-        pint_reg()
-            .cienf
-            .write(|w| unsafe { w.cenaf().bits(1 << interrupt_number) });
+        PINT.cienr().write(|w| w.set_cenrl(1 << interrupt_number));
+        PINT.cienf().write(|w| w.set_cenaf(1 << interrupt_number));
 
         critical_section::with(|cs| {
             let mut pin_interrupts = PIN_INTERRUPTS.borrow(cs).borrow_mut();
@@ -277,12 +250,8 @@ impl<'d> Future for InputFuture<'d> {
 }
 
 fn handle_interrupt(interrupt_number: usize) {
-    pint_reg()
-        .rise
-        .write(|w| unsafe { w.rdet().bits(1 << interrupt_number) });
-    pint_reg()
-        .fall
-        .write(|w| unsafe { w.fdet().bits(1 << interrupt_number) });
+    PINT.rise().write(|w| w.set_rdet(1 << interrupt_number));
+    PINT.fall().write(|w| w.set_fdet(1 << interrupt_number));
 
     critical_section::with(|cs| {
         let mut pin_interrupts = PIN_INTERRUPTS.borrow(cs).borrow_mut();
diff --git a/embassy-nxp/src/time_driver/rtc.rs b/embassy-nxp/src/time_driver/rtc.rs
index 94272e9c2..fb6de6a5e 100644
--- a/embassy-nxp/src/time_driver/rtc.rs
+++ b/embassy-nxp/src/time_driver/rtc.rs
@@ -6,7 +6,9 @@ use embassy_hal_internal::interrupt::{InterruptExt, Priority};
 use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex;
 use embassy_time_driver::{time_driver_impl, Driver};
 use embassy_time_queue_utils::Queue;
-use lpc55_pac::{interrupt, PMC, RTC, SYSCON};
+
+use crate::pac::{interrupt, pmc, rtc, PMC, RTC, SYSCON};
+
 struct AlarmState {
     timestamp: Cell<u64>,
 }
@@ -32,33 +34,32 @@ time_driver_impl!(static DRIVER: RtcDriver = RtcDriver {
 });
 impl RtcDriver {
     fn init(&'static self) {
-        let syscon = unsafe { &*SYSCON::ptr() };
-        let pmc = unsafe { &*PMC::ptr() };
-        let rtc = unsafe { &*RTC::ptr() };
+        let syscon = SYSCON;
+        let pmc = PMC;
+        let rtc = RTC;
 
-        syscon.ahbclkctrl0.modify(|_, w| w.rtc().enable());
+        syscon.ahbclkctrl0().modify(|w| w.set_rtc(true));
 
         // By default the RTC enters software reset. If for some reason it is
         // not in reset, we enter and them promptly leave.q
-        rtc.ctrl.modify(|_, w| w.swreset().set_bit());
-        rtc.ctrl.modify(|_, w| w.swreset().clear_bit());
+        rtc.ctrl().modify(|w| w.set_swreset(true));
+        rtc.ctrl().modify(|w| w.set_swreset(false));
 
         // Select clock source - either XTAL or FRO
-        // pmc.rtcosc32k.write(|w| w.sel().xtal32k());
-        pmc.rtcosc32k.write(|w| w.sel().fro32k());
+        // pmc.rtcosc32k().write(|w| w.set_sel(pmc::vals::Sel::XTAL32K));
+        pmc.rtcosc32k().write(|w| w.set_sel(pmc::vals::Sel::FRO32K));
 
         // Start the RTC peripheral
-        rtc.ctrl.modify(|_, w| w.rtc_osc_pd().power_up());
-
-        // rtc.ctrl.modify(|_, w| w.rtc_en().clear_bit()); // EXTRA
+        rtc.ctrl().modify(|w| w.set_rtc_osc_pd(rtc::vals::RtcOscPd::POWER_UP));
 
         //reset/clear(?) counter
-        rtc.count.reset();
+        rtc.count().modify(|w| w.set_val(0));
         //en rtc main counter
-        rtc.ctrl.modify(|_, w| w.rtc_en().set_bit());
-        rtc.ctrl.modify(|_, w| w.rtc1khz_en().set_bit());
+        rtc.ctrl().modify(|w| w.set_rtc_en(true));
+        rtc.ctrl().modify(|w| w.set_rtc1khz_en(true));
         // subsec counter enable
-        rtc.ctrl.modify(|_, w| w.rtc_subsec_ena().set_bit());
+        rtc.ctrl()
+            .modify(|w| w.set_rtc_subsec_ena(rtc::vals::RtcSubsecEna::POWER_UP));
 
         // enable irq
         unsafe {
@@ -68,7 +69,7 @@ impl RtcDriver {
     }
 
     fn set_alarm(&self, cs: CriticalSection, timestamp: u64) -> bool {
-        let rtc = unsafe { &*RTC::ptr() };
+        let rtc = RTC;
         let alarm = &self.alarms.borrow(cs);
         alarm.timestamp.set(timestamp);
         let now = self.now();
@@ -83,33 +84,38 @@ impl RtcDriver {
         let sec = (diff / 32768) as u32;
         let subsec = (diff % 32768) as u32;
 
-        let current_sec = rtc.count.read().val().bits();
+        let current_sec = rtc.count().read().val();
         let target_sec = current_sec.wrapping_add(sec as u32);
 
-        rtc.match_.write(|w| unsafe { w.matval().bits(target_sec) });
-        rtc.wake.write(|w| unsafe {
+        rtc.match_().write(|w| w.set_matval(target_sec));
+        rtc.wake().write(|w| {
             let ms = (subsec * 1000) / 32768;
-            w.val().bits(ms as u16)
+            w.set_val(ms as u16)
         });
+
         if subsec > 0 {
             let ms = (subsec * 1000) / 32768;
-            rtc.wake.write(|w| unsafe { w.val().bits(ms as u16) });
+            rtc.wake().write(|w| w.set_val(ms as u16));
         }
-        rtc.ctrl.modify(|_, w| w.alarm1hz().clear_bit().wake1khz().clear_bit());
+
+        rtc.ctrl().modify(|w| {
+            w.set_alarm1hz(false);
+            w.set_wake1khz(rtc::vals::Wake1khz::RUN)
+        });
         true
     }
 
     fn on_interrupt(&self) {
         critical_section::with(|cs| {
-            let rtc = unsafe { &*RTC::ptr() };
-            let flags = rtc.ctrl.read();
-            if flags.alarm1hz().bit_is_clear() {
-                rtc.ctrl.modify(|_, w| w.alarm1hz().set_bit());
+            let rtc = RTC;
+            let flags = rtc.ctrl().read();
+            if flags.alarm1hz() == false {
+                rtc.ctrl().modify(|w| w.set_alarm1hz(true));
                 self.trigger_alarm(cs);
             }
 
-            if flags.wake1khz().bit_is_clear() {
-                rtc.ctrl.modify(|_, w| w.wake1khz().set_bit());
+            if flags.wake1khz() == rtc::vals::Wake1khz::RUN {
+                rtc.ctrl().modify(|w| w.set_wake1khz(rtc::vals::Wake1khz::TIMEOUT));
                 self.trigger_alarm(cs);
             }
         });
@@ -135,13 +141,13 @@ impl RtcDriver {
 
 impl Driver for RtcDriver {
     fn now(&self) -> u64 {
-        let rtc = unsafe { &*RTC::ptr() };
+        let rtc = RTC;
 
         loop {
-            let sec1 = rtc.count.read().val().bits() as u64;
-            let sub1 = rtc.subsec.read().subsec().bits() as u64;
-            let sec2 = rtc.count.read().val().bits() as u64;
-            let sub2 = rtc.subsec.read().subsec().bits() as u64;
+            let sec1 = rtc.count().read().val() as u64;
+            let sub1 = rtc.subsec().read().subsec() as u64;
+            let sec2 = rtc.count().read().val() as u64;
+            let sub2 = rtc.subsec().read().subsec() as u64;
 
             if sec1 == sec2 && sub1 == sub2 {
                 return sec1 * 32768 + sub1;
@@ -162,7 +168,7 @@ impl Driver for RtcDriver {
         })
     }
 }
-#[cortex_m_rt::interrupt]
+#[interrupt]
 fn RTC() {
     DRIVER.on_interrupt();
 }
diff --git a/embassy-nxp/src/usart.rs b/embassy-nxp/src/usart.rs
index 009c251e2..1d8886f24 100644
--- a/embassy-nxp/src/usart.rs
+++ b/embassy-nxp/src/usart.rs
@@ -1,6 +1,5 @@
 //! Universal Synchronous/Asynchronous Receiver/Transmitter (USART) driver.
-#![macro_use]
 
-#[cfg_attr(feature = "lpc55", path = "./usart/lpc55.rs")]
+#[cfg_attr(feature = "lpc55-core0", path = "./usart/lpc55.rs")]
 mod inner;
 pub use inner::*;
diff --git a/embassy-nxp/src/usart/lpc55.rs b/embassy-nxp/src/usart/lpc55.rs
index 3f7456a2e..428b80c4b 100644
--- a/embassy-nxp/src/usart/lpc55.rs
+++ b/embassy-nxp/src/usart/lpc55.rs
@@ -2,9 +2,12 @@ use core::marker::PhantomData;
 
 use embassy_hal_internal::{Peri, PeripheralType};
 use embedded_io::{self, ErrorKind};
-pub use sealed::SealedInstance;
 
-use crate::gpio::AnyPin;
+use crate::gpio::{match_iocon, AnyPin, Bank, SealedPin};
+use crate::pac::flexcomm::Flexcomm as FlexcommReg;
+use crate::pac::iocon::vals::PioFunc;
+use crate::pac::usart::Usart as UsartReg;
+use crate::pac::*;
 use crate::{Blocking, Mode};
 
 /// Serial error
@@ -47,16 +50,6 @@ pub enum DataBits {
     DataBits9,
 }
 
-impl DataBits {
-    fn bits(&self) -> u8 {
-        match self {
-            Self::DataBits7 => 0b00,
-            Self::DataBits8 => 0b01,
-            Self::DataBits9 => 0b10,
-        }
-    }
-}
-
 /// Parity bit.
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
 pub enum Parity {
@@ -68,16 +61,6 @@ pub enum Parity {
     ParityOdd,
 }
 
-impl Parity {
-    fn bits(&self) -> u8 {
-        match self {
-            Self::ParityNone => 0b00,
-            Self::ParityEven => 0b10,
-            Self::ParityOdd => 0b11,
-        }
-    }
-}
-
 /// Stop bits.
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
 pub enum StopBits {
@@ -87,15 +70,6 @@ pub enum StopBits {
     Stop2,
 }
 
-impl StopBits {
-    fn bits(&self) -> bool {
-        return match self {
-            Self::Stop1 => false,
-            Self::Stop2 => true,
-        };
-    }
-}
-
 /// UART config.
 #[non_exhaustive]
 #[derive(Clone, Debug)]
@@ -117,7 +91,7 @@ pub struct Config {
 impl Default for Config {
     fn default() -> Self {
         Self {
-            baudrate: 9600,
+            baudrate: 115200,
             data_bits: DataBits::DataBits8,
             stop_bits: StopBits::Stop1,
             parity: Parity::ParityNone,
@@ -131,59 +105,72 @@ impl Default for Config {
 /// 'd: the lifetime marker ensuring correct borrow checking for peripherals used at compile time
 /// T: the peripheral instance type allowing usage of peripheral specific registers
 /// M: the operating mode of USART peripheral
-pub struct Usart<'d, T: Instance, M: Mode> {
-    tx: UsartTx<'d, T, M>,
-    rx: UsartRx<'d, T, M>,
+pub struct Usart<'d, M: Mode> {
+    tx: UsartTx<'d, M>,
+    rx: UsartRx<'d, M>,
 }
 
-pub struct UsartTx<'d, T: Instance, M: Mode> {
-    phantom: PhantomData<(&'d (), T, M)>,
+pub struct UsartTx<'d, M: Mode> {
+    info: &'static Info,
+    phantom: PhantomData<(&'d (), M)>,
 }
 
-pub struct UsartRx<'d, T: Instance, M: Mode> {
-    phantom: PhantomData<(&'d (), T, M)>,
+pub struct UsartRx<'d, M: Mode> {
+    info: &'static Info,
+    phantom: PhantomData<(&'d (), M)>,
 }
 
-impl<'d, T: Instance, M: Mode> UsartTx<'d, T, M> {
-    pub fn new(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self {
-        Usart::<T, M>::init(Some(tx.into()), None, config);
-        Self::new_inner()
+impl<'d, M: Mode> UsartTx<'d, M> {
+    pub fn new<T: Instance>(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self {
+        Usart::<M>::init::<T>(Some(tx.into()), None, config);
+        Self::new_inner(T::info())
     }
 
     #[inline]
-    fn new_inner() -> Self {
-        Self { phantom: PhantomData }
+    fn new_inner(info: &'static Info) -> Self {
+        Self {
+            info,
+            phantom: PhantomData,
+        }
     }
 
     pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
-        T::blocking_write(buffer)
+        for &b in buffer {
+            while !(self.info.usart_reg.fifostat().read().txnotfull()) {}
+            self.info.usart_reg.fifowr().write(|w| w.set_txdata(b as u16));
+        }
+        Ok(())
     }
 
     pub fn blocking_flush(&mut self) -> Result<(), Error> {
-        T::blocking_flush()
+        while !(self.info.usart_reg.fifostat().read().txempty()) {}
+        Ok(())
     }
 
     pub fn tx_busy(&self) -> bool {
-        T::tx_busy()
+        !(self.info.usart_reg.fifostat().read().txempty())
     }
 }
 
-impl<'d, T: Instance> UsartTx<'d, T, Blocking> {
-    pub fn new_blocking(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self {
-        Usart::<T, Blocking>::init(Some(tx.into()), None, config);
-        Self::new_inner()
+impl<'d> UsartTx<'d, Blocking> {
+    pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self {
+        Usart::<Blocking>::init::<T>(Some(tx.into()), None, config);
+        Self::new_inner(T::info())
     }
 }
 
-impl<'d, T: Instance, M: Mode> UsartRx<'d, T, M> {
-    pub fn new(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self {
-        Usart::<T, M>::init(None, Some(rx.into()), config);
-        Self::new_inner()
+impl<'d, M: Mode> UsartRx<'d, M> {
+    pub fn new<T: Instance>(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self {
+        Usart::<M>::init::<T>(None, Some(rx.into()), config);
+        Self::new_inner(T::info())
     }
 
     #[inline]
-    fn new_inner() -> Self {
-        Self { phantom: PhantomData }
+    fn new_inner(info: &'static Info) -> Self {
+        Self {
+            info,
+            phantom: PhantomData,
+        }
     }
 
     pub fn blocking_read(&mut self, mut buffer: &mut [u8]) -> Result<(), Error> {
@@ -201,19 +188,35 @@ impl<'d, T: Instance, M: Mode> UsartRx<'d, T, M> {
     /// - Ok(n) -> read n bytes
     /// - Err(n, Error) -> read n-1 bytes, but encountered an error while reading nth byte
     fn drain_fifo(&mut self, buffer: &mut [u8]) -> Result<usize, (usize, Error)> {
-        T::drain_fifo(buffer)
+        for (i, b) in buffer.iter_mut().enumerate() {
+            while !(self.info.usart_reg.fifostat().read().rxnotempty()) {}
+            if self.info.usart_reg.fifostat().read().rxerr() {
+                return Err((i, Error::Overrun));
+            } else if self.info.usart_reg.fifordnopop().read().parityerr() {
+                return Err((i, Error::Parity));
+            } else if self.info.usart_reg.fifordnopop().read().framerr() {
+                return Err((i, Error::Framing));
+            } else if self.info.usart_reg.fifordnopop().read().rxnoise() {
+                return Err((i, Error::Noise));
+            } else if self.info.usart_reg.intstat().read().deltarxbrk() {
+                return Err((i, Error::Break));
+            }
+            let dr = self.info.usart_reg.fiford().read().rxdata() as u8;
+            *b = dr;
+        }
+        Ok(buffer.len())
     }
 }
 
-impl<'d, T: Instance> UsartRx<'d, T, Blocking> {
-    pub fn new_blocking(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self {
-        Usart::<T, Blocking>::init(None, Some(rx.into()), config);
-        Self::new_inner()
+impl<'d> UsartRx<'d, Blocking> {
+    pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self {
+        Usart::<Blocking>::init::<T>(None, Some(rx.into()), config);
+        Self::new_inner(T::info())
     }
 }
 
-impl<'d, T: Instance> Usart<'d, T, Blocking> {
-    pub fn new_blocking(
+impl<'d> Usart<'d, Blocking> {
+    pub fn new_blocking<T: Instance>(
         usart: Peri<'d, T>,
         tx: Peri<'d, impl TxPin<T>>,
         rx: Peri<'d, impl RxPin<T>>,
@@ -223,29 +226,70 @@ impl<'d, T: Instance> Usart<'d, T, Blocking> {
     }
 }
 
-impl<'d, T: Instance, M: Mode> Usart<'d, T, M> {
-    fn new_inner(_usart: Peri<'d, T>, mut tx: Peri<'d, AnyPin>, mut rx: Peri<'d, AnyPin>, config: Config) -> Self {
-        Self::init(Some(tx.reborrow()), Some(rx.reborrow()), config);
+impl<'d, M: Mode> Usart<'d, M> {
+    fn new_inner<T: Instance>(
+        _usart: Peri<'d, T>,
+        mut tx: Peri<'d, AnyPin>,
+        mut rx: Peri<'d, AnyPin>,
+        config: Config,
+    ) -> Self {
+        Self::init::<T>(Some(tx.reborrow()), Some(rx.reborrow()), config);
         Self {
-            tx: UsartTx::new_inner(),
-            rx: UsartRx::new_inner(),
+            tx: UsartTx::new_inner(T::info()),
+            rx: UsartRx::new_inner(T::info()),
         }
     }
 
-    fn init(_tx: Option<Peri<'_, AnyPin>>, _rx: Option<Peri<'_, AnyPin>>, config: Config) {
-        T::enable_clock();
-        T::reset_flexcomm();
-        let source_clock: u32 = T::select_clock(config.baudrate);
-        T::configure_flexcomm();
-        T::tx_pin_config();
-        T::rx_pin_config();
-        Self::set_baudrate(source_clock, config.baudrate);
-        T::configure_usart(config);
-        T::disable_dma();
-        T::enable_usart();
+    fn init<T: Instance>(tx: Option<Peri<'_, AnyPin>>, rx: Option<Peri<'_, AnyPin>>, config: Config) {
+        Self::configure_flexcomm(T::info().fc_reg, T::instance_number());
+        Self::configure_clock::<T>(&config);
+        Self::pin_config::<T>(tx, rx);
+        Self::configure_usart(T::info(), &config);
     }
 
-    fn set_baudrate(source_clock: u32, baudrate: u32) {
+    fn configure_clock<T: Instance>(config: &Config) {
+        // Select source clock
+
+        // Adaptive clock choice based on baud rate
+        // To get the desired baud rate, it is essential to choose the clock bigger than baud rate so that it can be 'chiseled'
+        // There are two types of dividers: integer divider (baud rate generator register and oversample selection value)
+        // and fractional divider (fractional rate divider).
+
+        // By default, oversampling rate is 16 which is an industry standard.
+        // That means 16 clocks are used to deliver the byte to recipient.
+        // In this way the probability of getting correct bytes instead of noise directly increases as oversampling increases as well.
+
+        // Minimum and maximum values were computed taking these formulas into account:
+        // For minimum value, MULT = 0, BRGVAL = 0
+        // For maximum value, MULT = 255, BRGVAL = 255
+        // Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1 + MULT / DIV)
+        // By default, OSRVAL = 15 (see above)
+        // Baud rate = [FCLK / (OSRVAL+1)] / (BRGVAL + 1)
+        let source_clock = match config.baudrate {
+            750_001..=6_000_000 => {
+                SYSCON
+                    .fcclksel(T::instance_number())
+                    .modify(|w| w.set_sel(syscon::vals::FcclkselSel::ENUM_0X3)); // 96 MHz
+                96_000_000
+            }
+            1501..=750_000 => {
+                SYSCON
+                    .fcclksel(T::instance_number())
+                    .modify(|w| w.set_sel(syscon::vals::FcclkselSel::ENUM_0X2)); // 12 MHz
+                12_000_000
+            }
+            121..=1500 => {
+                SYSCON
+                    .fcclksel(T::instance_number())
+                    .modify(|w| w.set_sel(syscon::vals::FcclkselSel::ENUM_0X4)); // 1 MHz
+                1_000_000
+            }
+            _ => {
+                panic!("{} baudrate is not permitted in this mode", config.baudrate);
+            }
+        };
+        // Calculate MULT and BRG values based on baudrate
+
         // There are two types of dividers: integer divider (baud rate generator register and oversample selection value)
         // and fractional divider (fractional rate divider).
         // For oversampling, the default is industry standard 16x oversampling, i.e. OSRVAL = 15
@@ -274,14 +318,167 @@ impl<'d, T: Instance, M: Mode> Usart<'d, T, M> {
         // Secondly, MULT is calculated to ultimately 'chisel' the clock to get the baud rate.
         // The deduced formulas are written below.
 
-        let brg_value = (source_clock / (16 * baudrate)).min(255);
+        let brg_value = (source_clock / (16 * config.baudrate)).min(255);
         let raw_clock = source_clock / (16 * brg_value);
-        let mult_value = ((raw_clock * 256 / baudrate) - 256).min(255);
-        T::set_baudrate(mult_value as u8, brg_value as u8);
+        let mult_value = ((raw_clock * 256 / config.baudrate) - 256).min(255);
+
+        // Write values to the registers
+
+        // FCLK =  (clock selected via FCCLKSEL) / (1+ MULT / DIV)
+        // Remark: To use the fractional baud rate generator, 0xFF must be wirtten to the DIV value
+        // to yield a denominator vale of 256. All other values are not supported
+        SYSCON.flexfrgctrl(T::instance_number()).modify(|w| {
+            w.set_div(0xFF);
+            w.set_mult(mult_value as u8);
+        });
+
+        // Baud rate = [FCLK / (OSRVAL+1)] / (BRGVAL + 1)
+        // By default, oversampling is 16x, i.e. OSRVAL = 15
+
+        // Typical industry standard USARTs use a 16x oversample clock to transmit and receive
+        // asynchronous data. This is the number of BRG clocks used for one data bit. The
+        // Oversample Select Register (OSR) allows this USART to use a 16x down to a 5x
+        // oversample clock. There is no oversampling in synchronous modes.
+        T::info()
+            .usart_reg
+            .brg()
+            .modify(|w| w.set_brgval((brg_value - 1) as u16));
+    }
+
+    fn pin_config<T: Instance>(tx: Option<Peri<'_, AnyPin>>, rx: Option<Peri<'_, AnyPin>>) {
+        if let Some(tx_pin) = tx {
+            match_iocon!(register, tx_pin.pin_bank(), tx_pin.pin_number(), {
+                register.modify(|w| {
+                    w.set_func(T::tx_pin_func());
+                    w.set_mode(iocon::vals::PioMode::INACTIVE);
+                    w.set_slew(iocon::vals::PioSlew::STANDARD);
+                    w.set_invert(false);
+                    w.set_digimode(iocon::vals::PioDigimode::DIGITAL);
+                    w.set_od(iocon::vals::PioOd::NORMAL);
+                });
+            })
+        }
+
+        if let Some(rx_pin) = rx {
+            match_iocon!(register, rx_pin.pin_bank(), rx_pin.pin_number(), {
+                register.modify(|w| {
+                    w.set_func(T::rx_pin_func());
+                    w.set_mode(iocon::vals::PioMode::INACTIVE);
+                    w.set_slew(iocon::vals::PioSlew::STANDARD);
+                    w.set_invert(false);
+                    w.set_digimode(iocon::vals::PioDigimode::DIGITAL);
+                    w.set_od(iocon::vals::PioOd::NORMAL);
+                });
+            })
+        };
+    }
+
+    fn configure_flexcomm(flexcomm_register: crate::pac::flexcomm::Flexcomm, instance_number: usize) {
+        critical_section::with(|_cs| {
+            if !(SYSCON.ahbclkctrl0().read().iocon()) {
+                SYSCON.ahbclkctrl0().modify(|w| w.set_iocon(true));
+            }
+        });
+        critical_section::with(|_cs| {
+            if !(SYSCON.ahbclkctrl1().read().fc(instance_number)) {
+                SYSCON.ahbclkctrl1().modify(|w| w.set_fc(instance_number, true));
+            }
+        });
+        SYSCON
+            .presetctrl1()
+            .modify(|w| w.set_fc_rst(instance_number, syscon::vals::FcRst::ASSERTED));
+        SYSCON
+            .presetctrl1()
+            .modify(|w| w.set_fc_rst(instance_number, syscon::vals::FcRst::RELEASED));
+        flexcomm_register
+            .pselid()
+            .modify(|w| w.set_persel(flexcomm::vals::Persel::USART));
+    }
+
+    fn configure_usart(info: &'static Info, config: &Config) {
+        let registers = info.usart_reg;
+        // See section 34.6.1
+        registers.cfg().modify(|w| {
+            // LIN break mode enable
+            // Disabled. Break detect and generate is configured for normal operation.
+            w.set_linmode(false);
+            //CTS Enable. Determines whether CTS is used for flow control. CTS can be from the
+            //input pin, or from the USART’s own RTS if loopback mode is enabled.
+            // No flow control. The transmitter does not receive any automatic flow control signal.
+            w.set_ctsen(false);
+            // Selects synchronous or asynchronous operation.
+            w.set_syncen(usart::vals::Syncen::ASYNCHRONOUS_MODE);
+            // Selects the clock polarity and sampling edge of received data in synchronous mode.
+            w.set_clkpol(usart::vals::Clkpol::RISING_EDGE);
+            // Synchronous mode Master select.
+            // When synchronous mode is enabled, the USART is a master.
+            w.set_syncmst(usart::vals::Syncmst::MASTER);
+            // Selects data loopback mode
+            w.set_loop_(usart::vals::Loop::NORMAL);
+            // Output Enable Turnaround time enable for RS-485 operation.
+            // Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of
+            // the last stop bit of a transmission.
+            w.set_oeta(false);
+            // Output enable select.
+            // Standard. The RTS signal is used as the standard flow control function.
+            w.set_oesel(usart::vals::Oesel::STANDARD);
+            // Automatic address matching enable.
+            // Disabled. When addressing is enabled by ADDRDET, address matching is done by
+            // software. This provides the possibility of versatile addressing (e.g. respond to more
+            // than one address)
+            w.set_autoaddr(false);
+            // Output enable polarity.
+            // Low. If selected by OESEL, the output enable is active low.
+            w.set_oepol(usart::vals::Oepol::LOW);
+        });
+
+        // Configurations based on the config written by a user
+        registers.cfg().modify(|w| {
+            w.set_datalen(match config.data_bits {
+                DataBits::DataBits7 => usart::vals::Datalen::BIT_7,
+                DataBits::DataBits8 => usart::vals::Datalen::BIT_8,
+                DataBits::DataBits9 => usart::vals::Datalen::BIT_9,
+            });
+            w.set_paritysel(match config.parity {
+                Parity::ParityNone => usart::vals::Paritysel::NO_PARITY,
+                Parity::ParityEven => usart::vals::Paritysel::EVEN_PARITY,
+                Parity::ParityOdd => usart::vals::Paritysel::ODD_PARITY,
+            });
+            w.set_stoplen(match config.stop_bits {
+                StopBits::Stop1 => usart::vals::Stoplen::BIT_1,
+                StopBits::Stop2 => usart::vals::Stoplen::BITS_2,
+            });
+            w.set_rxpol(match config.invert_rx {
+                false => usart::vals::Rxpol::STANDARD,
+                true => usart::vals::Rxpol::INVERTED,
+            });
+            w.set_txpol(match config.invert_tx {
+                false => usart::vals::Txpol::STANDARD,
+                true => usart::vals::Txpol::INVERTED,
+            });
+        });
+
+        // DMA-related settings
+        registers.fifocfg().modify(|w| {
+            w.set_dmatx(false);
+            w.set_dmatx(false);
+        });
+
+        // Enabling USART
+        registers.fifocfg().modify(|w| {
+            w.set_enabletx(true);
+            w.set_enablerx(true);
+        });
+        registers.cfg().modify(|w| w.set_enable(true));
+
+        // Drain RX FIFO in case it still has some unrelevant data
+        while registers.fifostat().read().rxnotempty() {
+            let _ = registers.fiford().read().0;
+        }
     }
 }
 
-impl<'d, T: Instance, M: Mode> Usart<'d, T, M> {
+impl<'d, M: Mode> Usart<'d, M> {
     /// Transmit the provided buffer blocking execution until done.
     pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
         self.tx.blocking_write(buffer)
@@ -304,19 +501,19 @@ impl<'d, T: Instance, M: Mode> Usart<'d, T, M> {
 
     /// Split the Usart into a transmitter and receiver, which is particularly
     /// useful when having two tasks correlating to transmitting and receiving.
-    pub fn split(self) -> (UsartTx<'d, T, M>, UsartRx<'d, T, M>) {
+    pub fn split(self) -> (UsartTx<'d, M>, UsartRx<'d, M>) {
         (self.tx, self.rx)
     }
 
     /// Split the Usart into a transmitter and receiver by mutable reference,
     /// which is particularly useful when having two tasks correlating to
     /// transmitting and receiving.
-    pub fn split_ref(&mut self) -> (&mut UsartTx<'d, T, M>, &mut UsartRx<'d, T, M>) {
+    pub fn split_ref(&mut self) -> (&mut UsartTx<'d, M>, &mut UsartRx<'d, M>) {
         (&mut self.tx, &mut self.rx)
     }
 }
 
-impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for UsartTx<'d, T, M> {
+impl<'d, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for UsartTx<'d, M> {
     type Error = Error;
 
     fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
@@ -328,7 +525,7 @@ impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for
     }
 }
 
-impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for Usart<'d, T, M> {
+impl<'d, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for Usart<'d, M> {
     type Error = Error;
 
     fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
@@ -340,11 +537,11 @@ impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write<u8> for
     }
 }
 
-impl<'d, T: Instance> embedded_io::ErrorType for UsartTx<'d, T, Blocking> {
+impl<'d> embedded_io::ErrorType for UsartTx<'d, Blocking> {
     type Error = Error;
 }
 
-impl<'d, T: Instance> embedded_io::Write for UsartTx<'d, T, Blocking> {
+impl<'d> embedded_io::Write for UsartTx<'d, Blocking> {
     fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
         self.blocking_write(buf).map(|_| buf.len())
     }
@@ -354,21 +551,21 @@ impl<'d, T: Instance> embedded_io::Write for UsartTx<'d, T, Blocking> {
     }
 }
 
-impl<'d, T: Instance> embedded_io::ErrorType for UsartRx<'d, T, Blocking> {
+impl<'d> embedded_io::ErrorType for UsartRx<'d, Blocking> {
     type Error = Error;
 }
 
-impl<'d, T: Instance> embedded_io::Read for UsartRx<'d, T, Blocking> {
+impl<'d> embedded_io::Read for UsartRx<'d, Blocking> {
     fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
         self.blocking_read(buf).map(|_| buf.len())
     }
 }
 
-impl<'d, T: Instance> embedded_io::ErrorType for Usart<'d, T, Blocking> {
+impl<'d> embedded_io::ErrorType for Usart<'d, Blocking> {
     type Error = Error;
 }
 
-impl<'d, T: Instance> embedded_io::Write for Usart<'d, T, Blocking> {
+impl<'d> embedded_io::Write for Usart<'d, Blocking> {
     fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
         self.blocking_write(buf).map(|_| buf.len())
     }
@@ -378,468 +575,69 @@ impl<'d, T: Instance> embedded_io::Write for Usart<'d, T, Blocking> {
     }
 }
 
-impl<'d, T: Instance> embedded_io::Read for Usart<'d, T, Blocking> {
+impl<'d> embedded_io::Read for Usart<'d, Blocking> {
     fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
         self.blocking_read(buf).map(|_| buf.len())
     }
 }
 
-type UsartRegBlock = crate::pac::usart0::RegisterBlock;
-
-mod sealed {
-    use crate::usart::inner::UsartRegBlock;
-    use crate::usart::{Config, Error};
-    pub trait SealedInstance {
-        fn usart_reg() -> &'static UsartRegBlock;
-        fn enable_clock();
-        fn select_clock(baudrate: u32) -> u32;
-        fn configure_flexcomm();
-        fn set_baudrate(mult_value: u8, brg_value: u8);
-        fn reset_flexcomm();
-        fn tx_pin_config();
-        fn rx_pin_config();
-
-        fn configure_usart(config: Config) {
-            // See section 34.6.1
-            Self::usart_reg().cfg.modify(|_, w| {
-                // LIN break mode enable
-                w.linmode()
-                    // Disabled. Break detect and generate is configured for normal operation.
-                    .disabled()
-                    //CTS Enable. Determines whether CTS is used for flow control. CTS can be from the
-                    //input pin, or from the USART’s own RTS if loopback mode is enabled.
-                    .ctsen()
-                    // No flow control. The transmitter does not receive any automatic flow control signal.
-                    .disabled()
-                    // Selects synchronous or asynchronous operation.
-                    .syncen()
-                    .asynchronous_mode()
-                    // Selects the clock polarity and sampling edge of received data in synchronous mode.
-                    .clkpol()
-                    .rising_edge()
-                    // Synchronous mode Master select.
-                    .syncmst()
-                    // When synchronous mode is enabled, the USART is a master.
-                    .master()
-                    // Selects data loopback mode
-                    .loop_()
-                    // Normal operation
-                    .normal()
-                    // Output Enable Turnaround time enable for RS-485 operation.
-                    .oeta()
-                    // Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of
-                    // the last stop bit of a transmission.
-                    .disabled()
-                    // Output enable select.
-                    .oesel()
-                    // Standard. The RTS signal is used as the standard flow control function.
-                    .standard()
-                    // Automatic address matching enable.
-                    .autoaddr()
-                    // Disabled. When addressing is enabled by ADDRDET, address matching is done by
-                    // software. This provides the possibility of versatile addressing (e.g. respond to more
-                    // than one address)
-                    .disabled()
-                    // Output enable polarity.
-                    .oepol()
-                    // Low. If selected by OESEL, the output enable is active low.
-                    .low()
-            });
+struct Info {
+    usart_reg: UsartReg,
+    fc_reg: FlexcommReg,
+}
 
-            Self::usart_reg().cfg.modify(|_, w| unsafe {
-                w.datalen()
-                    .bits(config.data_bits.bits())
-                    .paritysel()
-                    .bits(config.parity.bits())
-                    .stoplen()
-                    .bit(config.stop_bits.bits())
-                    .rxpol()
-                    .bit(config.invert_rx)
-                    .txpol()
-                    .bit(config.invert_tx)
-            });
-        }
-        fn disable_dma() {
-            Self::usart_reg()
-                .fifocfg
-                .modify(|_, w| w.dmatx().disabled().dmarx().disabled());
-        }
-        fn enable_usart() {
-            Self::usart_reg()
-                .fifocfg
-                .modify(|_, w| w.enabletx().enabled().enablerx().enabled());
-            Self::usart_reg().cfg.modify(|_, w| w.enable().enabled());
-            while Self::usart_reg().fifostat.read().rxnotempty().bit_is_set() {
-                let _ = Self::usart_reg().fiford.read().bits();
-            }
-        }
-        fn blocking_write(buffer: &[u8]) -> Result<(), Error> {
-            for &b in buffer {
-                while Self::usart_reg().fifostat.read().txnotfull().bit_is_clear() {}
-                Self::usart_reg()
-                    .fifowr
-                    .modify(|_, w| unsafe { w.txdata().bits(b as u16) });
-            }
-            Ok(())
-        }
-        fn blocking_flush() -> Result<(), Error> {
-            while Self::usart_reg().fifostat.read().txempty().bit_is_clear() {}
-            Ok(())
-        }
-        fn tx_busy() -> bool {
-            Self::usart_reg().fifostat.read().txempty().bit_is_clear()
-        }
-        fn drain_fifo(buffer: &mut [u8]) -> Result<usize, (usize, Error)> {
-            for (i, b) in buffer.iter_mut().enumerate() {
-                while Self::usart_reg().fifostat.read().rxnotempty().bit_is_clear() {}
-
-                if Self::usart_reg().fifostat.read().rxerr().bit_is_set() {
-                    return Err((i, Error::Overrun));
-                } else if Self::usart_reg().fifordnopop.read().parityerr().bit_is_set() {
-                    return Err((i, Error::Parity));
-                } else if Self::usart_reg().fifordnopop.read().framerr().bit_is_set() {
-                    return Err((i, Error::Framing));
-                } else if Self::usart_reg().fifordnopop.read().rxnoise().bit_is_set() {
-                    return Err((i, Error::Noise));
-                } else if Self::usart_reg().intstat.read().deltarxbrk().bit_is_set() {
-                    return Err((i, Error::Break));
-                }
-                let dr = Self::usart_reg().fiford.read().bits() as u8;
-                *b = dr;
-            }
-            Ok(buffer.len())
-        }
-    }
+trait SealedInstance {
+    fn info() -> &'static Info;
+    fn instance_number() -> usize;
+    fn tx_pin_func() -> PioFunc;
+    fn rx_pin_func() -> PioFunc;
 }
 
 /// UART instance.
 #[allow(private_bounds)]
-pub trait Instance: sealed::SealedInstance + PeripheralType {}
+pub trait Instance: SealedInstance + PeripheralType {}
 
-#[macro_export]
 macro_rules! impl_instance {
-    (
-        $inst:ident,
-        usart_peripheral: $USARTX:ident,
-        usart_crate: $usartX:ident,
-
-        flexcomm: {
-          field: $FLEXCOMM_FIELD:ident,
-          clock_field: $FLEXCOMM_CLK_FIELD:ident
-        },
-
-        reset: {
-            bit: $RESET_BIT:ident
-        },
-
-        clock: {
-            sel_field: $CLKSEL_FIELD:ident,
-            frg_field: $FRG_FIELD:ident
-        },
-
-        pins: {
-            tx: $TX_IOCON:ident => $TX_FUNC:expr,
-            rx: $RX_IOCON:ident => $RX_FUNC:expr
-        }
-
-    ) => {
-        impl $crate::usart::SealedInstance for $crate::peripherals::$inst {
-            fn usart_reg() -> &'static UsartRegBlock {
-                unsafe { &*$crate::pac::$USARTX::ptr() }
-            }
-
-            fn enable_clock() {
-                critical_section::with(|_cs| {
-                    if syscon_reg().ahbclkctrl0.read().iocon().is_disable() {
-                        syscon_reg().ahbclkctrl0.modify(|_, w| w.iocon().enable());
-                    }
-                    if syscon_reg().ahbclkctrl1.read().$FLEXCOMM_CLK_FIELD().is_disable() {
-                        syscon_reg()
-                            .ahbclkctrl1
-                            .modify(|_, w| w.$FLEXCOMM_CLK_FIELD().enable());
-                    }
-                });
-            }
-
-            fn configure_flexcomm() {
-                let flexcomm = unsafe { &*$crate::pac::$FLEXCOMM_FIELD::ptr() };
-                flexcomm.pselid.modify(|_, w| w.persel().usart());
-            }
-
-            fn reset_flexcomm() {
-                syscon_reg().presetctrl1.modify(|_, w| w.$RESET_BIT().set_bit());
-                syscon_reg().presetctrl1.modify(|_, w| w.$RESET_BIT().clear_bit());
-            }
-
-            fn select_clock(baudrate: u32) -> u32 {
-                // Adaptive clock choice based on baud rate
-                // To get the desired baud rate, it is essential to choose the clock bigger than baud rate so that it can be 'chiseled'
-                // There are two types of dividers: integer divider (baud rate generator register and oversample selection value)
-                // and fractional divider (fractional rate divider).
-
-                // By default, oversampling rate is 16 which is an industry standard.
-                // That means 16 clocks are used to deliver the byte to recipient.
-                // In this way the probability of getting correct bytes instead of noise directly increases as oversampling increases as well.
-
-                // Minimum and maximum values were computed taking these formulas into account:
-                // For minimum value, MULT = 0, BRGVAL = 0
-                // For maximum value, MULT = 255, BRGVAL = 255
-                // Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1 + MULT / DIV)
-                // By default, OSRVAL = 15 (see above)
-                // Baud rate = [FCLK / (OSRVAL+1)] / (BRGVAL + 1)
-                return match baudrate {
-                    750_001..=6000000 => {
-                        syscon_reg().$CLKSEL_FIELD().write(|w| w.sel().enum_0x3()); // 96 MHz
-                        96_000_000
-                    }
-                    1501..=750_000 => {
-                        syscon_reg().$CLKSEL_FIELD().write(|w| w.sel().enum_0x2()); // 12 MHz
-                        12_000_000
-                    }
-                    121..=1500 => {
-                        syscon_reg().$CLKSEL_FIELD().write(|w| w.sel().enum_0x4()); // 1 MHz
-                        1_000_000
-                    }
-                    _ => {
-                        panic!("{} baudrate is not permitted in this mode", baudrate);
-                    }
+    ($inst:ident, $fc:ident, $tx_pin:ident, $rx_pin:ident, $fc_num:expr) => {
+        impl $crate::usart::inner::SealedInstance for $crate::peripherals::$inst {
+            fn info() -> &'static Info {
+                static INFO: Info = Info {
+                    usart_reg: crate::pac::$inst,
+                    fc_reg: crate::pac::$fc,
                 };
+                &INFO
             }
-
-            fn set_baudrate(mult_value: u8, brg_value: u8) {
-                // FCLK =  (clock selected via FCCLKSEL) / (1+ MULT / DIV)
-                // Remark: To use the fractional baud rate generator, 0xFF must be wirtten to the DIV value
-                // to yield a denominator vale of 256. All other values are not supported
-                syscon_reg()
-                    .$FRG_FIELD()
-                    .modify(|_, w| unsafe { w.div().bits(0xFF).mult().bits(mult_value as u8) });
-
-                // Baud rate = [FCLK / (OSRVAL+1)] / (BRGVAL + 1)
-                // By default, oversampling is 16x, i.e. OSRVAL = 15
-
-                // Typical industry standard USARTs use a 16x oversample clock to transmit and receive
-                // asynchronous data. This is the number of BRG clocks used for one data bit. The
-                // Oversample Select Register (OSR) allows this USART to use a 16x down to a 5x
-                // oversample clock. There is no oversampling in synchronous modes.
-                Self::usart_reg()
-                    .brg
-                    .modify(|_, w| unsafe { w.brgval().bits((brg_value - 1) as u16) });
+            #[inline]
+            fn instance_number() -> usize {
+                $fc_num
             }
-
-            fn tx_pin_config() {
-                iocon_reg().$TX_IOCON.modify(|_, w| unsafe {
-                    w.func()
-                        .bits($TX_FUNC)
-                        .digimode()
-                        .digital()
-                        .slew()
-                        .standard()
-                        .mode()
-                        .inactive()
-                        .invert()
-                        .disabled()
-                        .od()
-                        .normal()
-                });
+            #[inline]
+            fn tx_pin_func() -> PioFunc {
+                PioFunc::$tx_pin
             }
-
-            fn rx_pin_config() {
-                iocon_reg().$RX_IOCON.modify(|_, w| unsafe {
-                    w.func()
-                        .bits($RX_FUNC)
-                        .digimode()
-                        .digital()
-                        .slew()
-                        .standard()
-                        .mode()
-                        .inactive()
-                        .invert()
-                        .disabled()
-                        .od()
-                        .normal()
-                });
+            #[inline]
+            fn rx_pin_func() -> PioFunc {
+                PioFunc::$rx_pin
             }
         }
-
         impl $crate::usart::Instance for $crate::peripherals::$inst {}
     };
 }
 
-impl_instance!(USART0, usart_peripheral: USART0, usart_crate: usart0,
-    flexcomm: {
-        field: FLEXCOMM0,
-        clock_field: fc0
-    },
-
-    reset: {
-        bit: fc0_rst
-    },
-
-    clock: {
-        sel_field: fcclksel0,
-        frg_field: flexfrg0ctrl
-    },
-
-    pins: {
-        tx: pio1_6 => 1,
-        rx: pio1_5 => 1
-    }
-);
-
-impl_instance!(USART1, usart_peripheral: USART1, usart_crate: usart1,
-    flexcomm: {
-        field: FLEXCOMM1,
-        clock_field: fc1
-    },
-
-    reset: {
-        bit: fc1_rst
-    },
-
-    clock: {
-        sel_field: fcclksel1,
-        frg_field: flexfrg1ctrl
-    },
-
-    pins: {
-        tx: pio1_11 => 2,
-        rx: pio1_10 => 2
-    }
-);
-
-impl_instance!(USART2, usart_peripheral: USART2, usart_crate: usart2,
-    flexcomm: {
-        field: FLEXCOMM2,
-        clock_field: fc2
-    },
-
-    reset: {
-        bit: fc2_rst
-    },
-
-    clock: {
-        sel_field: fcclksel2,
-        frg_field: flexfrg2ctrl
-    },
-
-    pins: {
-        tx: pio0_27 => 1,
-        rx: pio1_24 => 1
-    }
-);
-
-impl_instance!(USART3, usart_peripheral: USART3, usart_crate: usart3,
-    flexcomm: {
-        field: FLEXCOMM3,
-        clock_field: fc3
-    },
-
-    reset: {
-        bit: fc3_rst
-    },
-
-    clock: {
-        sel_field: fcclksel3,
-        frg_field: flexfrg3ctrl
-    },
-
-    pins: {
-        tx: pio0_2 => 1,
-        rx: pio0_3 => 1
-    }
-);
-
-impl_instance!(USART4, usart_peripheral: USART4, usart_crate: usart4,
-    flexcomm: {
-        field: FLEXCOMM4,
-        clock_field: fc4
-    },
-
-    reset: {
-        bit: fc4_rst
-    },
-
-    clock: {
-        sel_field: fcclksel4,
-        frg_field: flexfrg4ctrl
-    },
-
-    pins: {
-        tx: pio0_16 => 1,
-        rx: pio0_5 => 2
-    }
-);
-
-impl_instance!(USART5, usart_peripheral: USART5, usart_crate: usart5,
-    flexcomm: {
-        field: FLEXCOMM5,
-        clock_field: fc5
-    },
-
-    reset: {
-        bit: fc5_rst
-    },
-
-    clock: {
-        sel_field: fcclksel5,
-        frg_field: flexfrg5ctrl
-    },
-
-    pins: {
-        tx: pio0_9 => 3,
-        rx: pio0_8 => 3
-    }
-);
-
-impl_instance!(USART6, usart_peripheral: USART6, usart_crate: usart6,
-    flexcomm: {
-        field: FLEXCOMM6,
-        clock_field: fc6
-    },
-
-    reset: {
-        bit: fc6_rst
-    },
-
-    clock: {
-        sel_field: fcclksel6,
-        frg_field: flexfrg6ctrl
-    },
-
-    pins: {
-        tx: pio1_16 => 2,
-        rx: pio1_13 => 2
-    }
-);
-
-impl_instance!(USART7, usart_peripheral: USART7, usart_crate: usart7,
-    flexcomm: {
-        field: FLEXCOMM7,
-        clock_field: fc7
-    },
-
-    reset: {
-        bit: fc7_rst
-    },
-
-    clock: {
-        sel_field: fcclksel7,
-        frg_field: flexfrg7ctrl
-    },
-
-    pins: {
-        tx: pio0_19 => 7,
-        rx: pio0_20 => 7
-    }
-);
+impl_instance!(USART0, FLEXCOMM0, ALT1, ALT1, 0);
+impl_instance!(USART1, FLEXCOMM1, ALT2, ALT2, 1);
+impl_instance!(USART2, FLEXCOMM2, ALT1, ALT1, 2);
+impl_instance!(USART3, FLEXCOMM3, ALT1, ALT1, 3);
+impl_instance!(USART4, FLEXCOMM4, ALT1, ALT2, 4);
+impl_instance!(USART5, FLEXCOMM5, ALT3, ALT3, 5);
+impl_instance!(USART6, FLEXCOMM6, ALT2, ALT2, 6);
+impl_instance!(USART7, FLEXCOMM7, ALT7, ALT7, 7);
 
 /// Trait for TX pins.
 pub trait TxPin<T: Instance>: crate::gpio::Pin {}
 /// Trait for RX pins.
 pub trait RxPin<T: Instance>: crate::gpio::Pin {}
 
-// TODO: Add RTS, CTS and CLK pin traits
-
 macro_rules! impl_pin {
     ($pin:ident, $instance:ident, Tx) => {
         impl TxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
@@ -849,37 +647,19 @@ macro_rules! impl_pin {
     };
 }
 
-impl_pin!(PIO1_5, USART0, Rx);
 impl_pin!(PIO1_6, USART0, Tx);
-impl_pin!(PIO1_10, USART1, Rx);
+impl_pin!(PIO1_5, USART0, Rx);
 impl_pin!(PIO1_11, USART1, Tx);
+impl_pin!(PIO1_10, USART1, Rx);
 impl_pin!(PIO0_27, USART2, Tx);
 impl_pin!(PIO1_24, USART2, Rx);
 impl_pin!(PIO0_2, USART3, Tx);
 impl_pin!(PIO0_3, USART3, Rx);
 impl_pin!(PIO0_16, USART4, Tx);
 impl_pin!(PIO0_5, USART4, Rx);
-impl_pin!(PIO0_8, USART5, Rx);
 impl_pin!(PIO0_9, USART5, Tx);
+impl_pin!(PIO0_8, USART5, Rx);
 impl_pin!(PIO1_16, USART6, Tx);
 impl_pin!(PIO1_13, USART6, Rx);
-impl_pin!(PIO0_20, USART7, Rx);
 impl_pin!(PIO0_19, USART7, Tx);
-
-/// Get the SYSCON register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn syscon_reg() -> &'static crate::pac::syscon::RegisterBlock {
-    unsafe { &*crate::pac::SYSCON::ptr() }
-}
-
-/// Get the IOCON register block.
-///
-/// # Safety
-/// Read/Write operations on a single registers are NOT atomic. You must ensure that the GPIO
-/// registers are not accessed concurrently by multiple threads.
-pub(crate) fn iocon_reg() -> &'static crate::pac::iocon::RegisterBlock {
-    unsafe { &*crate::pac::IOCON::ptr() }
-}
+impl_pin!(PIO0_20, USART7, Rx);
diff --git a/examples/lpc55s69/Cargo.toml b/examples/lpc55s69/Cargo.toml
index 79b27f269..579748595 100644
--- a/examples/lpc55s69/Cargo.toml
+++ b/examples/lpc55s69/Cargo.toml
@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
 publish = false
 
 [dependencies]
-embassy-nxp = { version = "0.1.0", path = "../../embassy-nxp", features = ["lpc55", "rt", "defmt", "time-driver-rtc"] }
+embassy-nxp = { version = "0.1.0", path = "../../embassy-nxp", features = ["lpc55-core0", "rt", "defmt", "time-driver-rtc"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt"] }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "tick-hz-32_768"] }