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authorThales Fragoso <[email protected]>2021-07-26 20:13:23 -0300
committerThales Fragoso <[email protected]>2021-08-01 19:10:42 -0300
commitc1bb83d29d7615e12cab6589a0e9629895fbb316 (patch)
tree50b6c300dda2995e7a2048a300bf614dec99c458
parent6ddc83029a6024692dd632029f0aadef776b5ef3 (diff)
i2c-v2: Deref interrupt enabling in write_dma_internal
-rw-r--r--embassy-stm32/src/i2c/v2.rs6
1 files changed, 4 insertions, 2 deletions
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 805265d22..8a9369557 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -407,7 +407,9 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
407 let regs = T::regs(); 407 let regs = T::regs();
408 regs.cr1().modify(|w| { 408 regs.cr1().modify(|w| {
409 w.set_txdmaen(true); 409 w.set_txdmaen(true);
410 w.set_tcie(true); 410 if first_slice {
411 w.set_tcie(true);
412 }
411 }); 413 });
412 let dst = regs.txdr().ptr() as *mut u8; 414 let dst = regs.txdr().ptr() as *mut u8;
413 415
@@ -442,9 +444,9 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
442 ); 444 );
443 } 445 }
444 } else { 446 } else {
445 // NOTE(unsafe) self.tx_dma does not fiddle with the i2c registers
446 unsafe { 447 unsafe {
447 Self::master_continue(total_len.min(255), (total_chunks != 1) || !last_slice); 448 Self::master_continue(total_len.min(255), (total_chunks != 1) || !last_slice);
449 T::regs().cr1().modify(|w| w.set_tcie(true));
448 } 450 }
449 } 451 }
450 452