Add `pll1_p_mul_2` clock.

1 files changed, 5 insertions, 0 deletions

diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index de209272d..bbc76d086 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -209,6 +209,9 @@ pub(crate) unsafe fn init(config: Config) {
         out_freq
     });
 
+    #[cfg(stm32f3)]
+    let pll_mul_2 = pll.map(|pll| { pll * 2u32 });
+
     #[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
     let usb = match pll {
         Some(Hertz(72_000_000)) => Some(crate::pac::rcc::vals::Usbpre::DIV1_5),
@@ -374,6 +377,8 @@ pub(crate) unsafe fn init(config: Config) {
         hsi: hsi,
         hse: hse,
         pll1_p: pll,
+        #[cfg(stm32f3)]
+        pll1_p_mul_2: pll_mul_2,
         sys: Some(sys),
         pclk1: Some(pclk1),
         pclk2: Some(pclk2),