diff options
| author | xoviat <[email protected]> | 2023-07-30 19:39:17 -0500 |
|---|---|---|
| committer | xoviat <[email protected]> | 2023-07-30 19:39:17 -0500 |
| commit | c38c85ef1fef86a5fc73d1329616df17afb3d385 (patch) | |
| tree | f36ef3b7a2308019d7fb1924178b45e1ba69955d | |
| parent | 538cf2bc24c6c9b299b01a63f775fa37d66c635b (diff) | |
stm32/dma: add traces
| -rw-r--r-- | embassy-stm32/src/dma/ringbuffer.rs | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/embassy-stm32/src/dma/ringbuffer.rs b/embassy-stm32/src/dma/ringbuffer.rs index 1235e5327..8056a7c3a 100644 --- a/embassy-stm32/src/dma/ringbuffer.rs +++ b/embassy-stm32/src/dma/ringbuffer.rs | |||
| @@ -229,6 +229,13 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { | |||
| 229 | pub fn write(&mut self, mut dma: impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), OverrunError> { | 229 | pub fn write(&mut self, mut dma: impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), OverrunError> { |
| 230 | let start = self.pos(dma.get_remaining_transfers()); | 230 | let start = self.pos(dma.get_remaining_transfers()); |
| 231 | if start > self.end { | 231 | if start > self.end { |
| 232 | trace!( | ||
| 233 | "[1]: start, end, complete_count: {}, {}, {}", | ||
| 234 | start, | ||
| 235 | self.end, | ||
| 236 | dma.get_complete_count() | ||
| 237 | ); | ||
| 238 | |||
| 232 | // The occupied portion in the ring buffer DOES wrap | 239 | // The occupied portion in the ring buffer DOES wrap |
| 233 | let len = self.copy_from(buf, self.end..start); | 240 | let len = self.copy_from(buf, self.end..start); |
| 234 | 241 | ||
| @@ -244,8 +251,22 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { | |||
| 244 | Ok((len, self.cap() - (start - self.end))) | 251 | Ok((len, self.cap() - (start - self.end))) |
| 245 | } | 252 | } |
| 246 | } else if start == self.end && dma.get_complete_count() == 0 { | 253 | } else if start == self.end && dma.get_complete_count() == 0 { |
| 254 | trace!( | ||
| 255 | "[2]: start, end, complete_count: {}, {}, {}", | ||
| 256 | start, | ||
| 257 | self.end, | ||
| 258 | dma.get_complete_count() | ||
| 259 | ); | ||
| 260 | |||
| 247 | Ok((0, 0)) | 261 | Ok((0, 0)) |
| 248 | } else if start <= self.end && self.end + buf.len() < self.cap() { | 262 | } else if start <= self.end && self.end + buf.len() < self.cap() { |
| 263 | trace!( | ||
| 264 | "[3]: start, end, complete_count: {}, {}, {}", | ||
| 265 | start, | ||
| 266 | self.end, | ||
| 267 | dma.get_complete_count() | ||
| 268 | ); | ||
| 269 | |||
| 249 | // The occupied portion in the ring buffer DOES NOT wrap | 270 | // The occupied portion in the ring buffer DOES NOT wrap |
| 250 | // and copying elements into the buffer WILL NOT cause it to | 271 | // and copying elements into the buffer WILL NOT cause it to |
| 251 | 272 | ||
| @@ -264,6 +285,13 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { | |||
| 264 | Ok((len, self.cap() - (self.end - start))) | 285 | Ok((len, self.cap() - (self.end - start))) |
| 265 | } | 286 | } |
| 266 | } else { | 287 | } else { |
| 288 | trace!( | ||
| 289 | "[4]: start, end, complete_count: {}, {}, {}", | ||
| 290 | start, | ||
| 291 | self.end, | ||
| 292 | dma.get_complete_count() | ||
| 293 | ); | ||
| 294 | |||
| 267 | // The occupied portion in the ring buffer DOES NOT wrap | 295 | // The occupied portion in the ring buffer DOES NOT wrap |
| 268 | // and copying elements into the buffer WILL cause it to | 296 | // and copying elements into the buffer WILL cause it to |
| 269 | 297 | ||
