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authorThales Fragoso <[email protected]>2021-08-10 20:40:02 -0300
committerThales Fragoso <[email protected]>2021-08-10 20:45:41 -0300
commitc7ae2d2a3a55ca32c43aea177371fea744a154e0 (patch)
tree6641d585bfe1f80dd2bbb54fc89dead3735469b1
parent0be5e323bbec8a12a6953edea21e3e5c959d8e69 (diff)
stm32: Add fences to DMA code
-rw-r--r--embassy-stm32/src/dma/bdma.rs7
-rw-r--r--embassy-stm32/src/dma/dma.rs7
2 files changed, 14 insertions, 0 deletions
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index d262caeb6..fbd753a71 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -1,6 +1,7 @@
1#![macro_use] 1#![macro_use]
2 2
3use core::future::Future; 3use core::future::Future;
4use core::sync::atomic::{fence, Ordering};
4use core::task::Poll; 5use core::task::Poll;
5 6
6use embassy::interrupt::{Interrupt, InterruptExt}; 7use embassy::interrupt::{Interrupt, InterruptExt};
@@ -61,6 +62,9 @@ pub(crate) unsafe fn do_transfer(
61 62
62 // Wait for the transfer to complete when it was ongoing. 63 // Wait for the transfer to complete when it was ongoing.
63 while ch.cr().read().en() {} 64 while ch.cr().read().en() {}
65
66 // "Subsequent reads and writes cannot be moved ahead of preceding reads."
67 fence(Ordering::Acquire);
64 }); 68 });
65 69
66 #[cfg(dmamux)] 70 #[cfg(dmamux)]
@@ -72,6 +76,9 @@ pub(crate) unsafe fn do_transfer(
72 .modify(|w| w.set_cs(channel_number as _, request)) 76 .modify(|w| w.set_cs(channel_number as _, request))
73 }); 77 });
74 78
79 // "Preceding reads and writes cannot be moved past subsequent writes."
80 fence(Ordering::Release);
81
75 ch.par().write_value(peri_addr as u32); 82 ch.par().write_value(peri_addr as u32);
76 ch.mar().write_value(mem_addr as u32); 83 ch.mar().write_value(mem_addr as u32);
77 ch.ndtr().write(|w| w.set_ndt(mem_len as u16)); 84 ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
index 9bf083de4..bce9656d1 100644
--- a/embassy-stm32/src/dma/dma.rs
+++ b/embassy-stm32/src/dma/dma.rs
@@ -1,4 +1,5 @@
1use core::future::Future; 1use core::future::Future;
2use core::sync::atomic::{fence, Ordering};
2use core::task::Poll; 3use core::task::Poll;
3 4
4use embassy::interrupt::{Interrupt, InterruptExt}; 5use embassy::interrupt::{Interrupt, InterruptExt};
@@ -64,11 +65,17 @@ pub(crate) unsafe fn do_transfer(
64 65
65 // Wait for the transfer to complete when it was ongoing. 66 // Wait for the transfer to complete when it was ongoing.
66 while ch.cr().read().en() {} 67 while ch.cr().read().en() {}
68
69 // "Subsequent reads and writes cannot be moved ahead of preceding reads."
70 fence(Ordering::Acquire);
67 }); 71 });
68 72
69 #[cfg(dmamux)] 73 #[cfg(dmamux)]
70 super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request); 74 super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
71 75
76 // "Preceding reads and writes cannot be moved past subsequent writes."
77 fence(Ordering::Release);
78
72 unsafe { 79 unsafe {
73 ch.par().write_value(peri_addr as u32); 80 ch.par().write_value(peri_addr as u32);
74 ch.m0ar().write_value(mem_addr as u32); 81 ch.m0ar().write_value(mem_addr as u32);