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authorelagil <[email protected]>2025-03-29 22:01:54 +0100
committerelagil <[email protected]>2025-03-29 22:01:54 +0100
commitca8be1c976b82a368622899fdf7192294bd81363 (patch)
tree0515327d692270b53a381a7cbf0a580a7d8d264e
parentcae954a87ec3c5ece520b6a44168b36e79f3f86a (diff)
fix: stm32g4 calibration delays
-rw-r--r--embassy-stm32/src/adc/g4.rs6
1 files changed, 5 insertions, 1 deletions
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 6a00e788e..6b9182ad6 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -171,7 +171,7 @@ impl<'d, T: Instance> Adc<'d, T> {
171 reg.set_advregen(true); 171 reg.set_advregen(true);
172 }); 172 });
173 173
174 blocking_delay_us(10); 174 blocking_delay_us(20);
175 } 175 }
176 176
177 fn configure_differential_inputs(&mut self) { 177 fn configure_differential_inputs(&mut self) {
@@ -191,6 +191,8 @@ impl<'d, T: Instance> Adc<'d, T> {
191 191
192 while T::regs().cr().read().adcal() {} 192 while T::regs().cr().read().adcal() {}
193 193
194 blocking_delay_us(20);
195
194 T::regs().cr().modify(|w| { 196 T::regs().cr().modify(|w| {
195 w.set_adcaldif(Adcaldif::DIFFERENTIAL); 197 w.set_adcaldif(Adcaldif::DIFFERENTIAL);
196 }); 198 });
@@ -198,6 +200,8 @@ impl<'d, T: Instance> Adc<'d, T> {
198 T::regs().cr().modify(|w| w.set_adcal(true)); 200 T::regs().cr().modify(|w| w.set_adcal(true));
199 201
200 while T::regs().cr().read().adcal() {} 202 while T::regs().cr().read().adcal() {}
203
204 blocking_delay_us(20);
201 } 205 }
202 206
203 fn enable(&mut self) { 207 fn enable(&mut self) {