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authorFelipe Balbi <[email protected]>2025-11-07 10:06:55 -0800
committerFelipe Balbi <[email protected]>2025-11-07 10:06:55 -0800
commitcb2ac2790f4b037056f9571abeb4d62360199426 (patch)
treef9f163e4340d11ddc54c24ab8cf7624e83f1fd18
parenta71eff2e1cea55b393e793c023b8e51e5cc369a1 (diff)
Reduce number of features
We don't need features for drivers that always exist. Signed-off-by: Felipe Balbi <[email protected]>
-rw-r--r--Cargo.toml45
-rw-r--r--examples/adc_interrupt.rs54
-rw-r--r--examples/adc_polling.rs47
-rw-r--r--examples/blink.rs6
-rw-r--r--examples/hello.rs14
-rw-r--r--examples/lpuart_buffered.rs6
-rw-r--r--examples/lpuart_polling.rs16
-rw-r--r--examples/ostimer_alarm.rs16
-rw-r--r--examples/ostimer_async.rs20
-rw-r--r--examples/ostimer_counter.rs16
-rw-r--r--examples/ostimer_race_test.rs17
-rw-r--r--examples/rtc_alarm.rs25
-rw-r--r--examples/uart_interrupt.rs21
-rw-r--r--src/adc.rs155
-rw-r--r--src/clocks.rs9
-rw-r--r--src/gpio.rs2
-rw-r--r--src/interrupt.rs2
-rw-r--r--src/lib.rs59
-rw-r--r--src/lpuart/buffered.rs2
-rw-r--r--src/lpuart/mod.rs2
-rw-r--r--src/ostimer.rs8
-rw-r--r--src/pins.rs1
-rw-r--r--src/rtc.rs28
-rw-r--r--src/uart.rs9
24 files changed, 211 insertions, 369 deletions
diff --git a/Cargo.toml b/Cargo.toml
index cf7ba854e..8ec547494 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -13,22 +13,18 @@ name = "embassy_mcxa276"
13[dependencies] 13[dependencies]
14cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 14cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
15cortex-m-rt = { version = "0.7", features = ["device"] } 15cortex-m-rt = { version = "0.7", features = ["device"] }
16mcxa276-pac = { git = "https://github.com/bogdan-petru/mcxa-pac", features = ["rt"], rev = "a9dd330149912c26f252f0f3c419f6435c1216e2", version = "0.1.0" } 16critical-section = "1.2.0"
17embedded-io = "0.6" 17defmt = { version = "1.0", optional = true }
18# Optional defmt support 18embassy-embedded-hal = "0.5.0"
19defmt = { version = "0.3", optional = true }
20defmt-rtt = { version = "0.4", optional = true }
21rtt-target = { version = "0.4", optional = true }
22panic-probe = { version = "0.3", features = ["print-defmt"], optional = true }
23embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false } 19embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false }
20embassy-hal-internal = { version = "0.3.0", features = ["cortex-m", "prio-bits-3"] }
21embassy-sync = "0.7.2"
24embassy-time = "0.5.0" 22embassy-time = "0.5.0"
25embassy-time-driver = "0.2.1" 23embassy-time-driver = "0.2.1"
26embassy-sync = "0.7.2" 24embedded-io = "0.6"
27embassy-embedded-hal = "0.5.0"
28embassy-hal-internal = { version = "0.3.0", features = ["cortex-m", "prio-bits-3"] }
29critical-section = "1.2.0"
30paste = "1.0.15"
31heapless = "0.8" 25heapless = "0.8"
26mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt"], rev = "f0281344c605ab24c38979553b41a1655c50625c", version = "0.1.0" }
27paste = "1.0.15"
32 28
33embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = [ 29embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = [
34 "unproven", 30 "unproven",
@@ -39,25 +35,20 @@ embedded-hal-nb = { version = "1.0" }
39embedded-io-async = { version = "0.6.1" } 35embedded-io-async = { version = "0.6.1" }
40nb = "1.1.0" 36nb = "1.1.0"
41 37
38[dev-dependencies]
39defmt-rtt = "1.0"
40panic-probe = { version = "1.0", features = ["print-defmt"] }
41
42[features] 42[features]
43default = [] 43default = []
44uart-debug = [] 44
45gpio = []
46lpuart2 = []
47ostimer0 = []
48rtc0 = []
49adc1 = []
50rt = []
51# Base defmt feature enables core + panic handler 45# Base defmt feature enables core + panic handler
52# Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback) 46# Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback)
53defmt = ["dep:defmt", "dep:panic-probe"] 47defmt = ["dep:defmt"]
54# RTT logger 48
55# Usage: cargo embed --features "defmt defmt-rtt lpuart2" --example hello 49rt = []
56# or: PROBE_RS_PROBE=<id> cargo embed --features "defmt defmt-rtt lpuart2" --example hello
57defmt-rtt = ["dep:defmt-rtt", "dep:rtt-target"]
58# Optional: UART-based defmt (no RTT). Enable with `--features defmt-uart defmt`.
59# defmt-uart = [] # Removed - no longer needed
60 50
51unstable-pac = []
61 52
62[[example]] 53[[example]]
63name = "hello" 54name = "hello"
@@ -116,6 +107,4 @@ opt-level = "s"
116debug = 2 107debug = 2
117opt-level = 1 108opt-level = 1
118 109
119[dev-dependencies]
120
121 110
diff --git a/examples/adc_interrupt.rs b/examples/adc_interrupt.rs
index 452eaae01..26afd70b4 100644
--- a/examples/adc_interrupt.rs
+++ b/examples/adc_interrupt.rs
@@ -1,28 +1,23 @@
1#![no_std] 1#![no_std]
2#![no_main] 2#![no_main]
3 3
4use embassy_mcxa276 as hal;
5use cortex_m; 4use cortex_m;
6use embassy_executor::Spawner; 5use embassy_executor::Spawner;
6use embassy_mcxa276 as hal;
7 7
8use hal::adc::{TriggerPriorityPolicy, LpadcConfig}; 8use hal::adc::{LpadcConfig, TriggerPriorityPolicy};
9use hal::pac::adc1::cfg::{Refsel, Pwrsel}; 9use hal::pac::adc1::cfg::{Pwrsel, Refsel};
10use hal::pac::adc1::tctrl::{Tcmd};
11use hal::pac::adc1::cmdl1::{Adch, Mode}; 10use hal::pac::adc1::cmdl1::{Adch, Mode};
12use hal::pac::adc1::ctrl::{CalAvgs}; 11use hal::pac::adc1::ctrl::CalAvgs;
12use hal::pac::adc1::tctrl::Tcmd;
13 13
14use hal::uart; 14use hal::uart;
15mod common; 15mod common;
16 16
17#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] 17use {defmt_rtt as _, panic_probe as _};
18use defmt_rtt as _;
19#[cfg(feature = "defmt")]
20use panic_probe as _;
21#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
22use rtt_target as _;
23 18
24use hal::bind_interrupts;
25use hal::InterruptExt; 19use hal::InterruptExt;
20use hal::bind_interrupts;
26 21
27bind_interrupts!(struct Irqs { 22bind_interrupts!(struct Irqs {
28 ADC1 => hal::adc::AdcHandler; 23 ADC1 => hal::adc::AdcHandler;
@@ -40,7 +35,7 @@ async fn main(_spawner: Spawner) {
40 common::init_uart2(hal::pac()); 35 common::init_uart2(hal::pac());
41 } 36 }
42 37
43 let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; 38 let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) };
44 let uart = uart::Uart::<uart::Lpuart2>::new(p.LPUART2, uart::Config::new(src)); 39 let uart = uart::Uart::<uart::Lpuart2>::new(p.LPUART2, uart::Config::new(src));
45 40
46 uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n"); 41 uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n");
@@ -48,19 +43,18 @@ async fn main(_spawner: Spawner) {
48 unsafe { 43 unsafe {
49 common::init_adc(hal::pac()); 44 common::init_adc(hal::pac());
50 } 45 }
51 46
52
53 let adc_config = LpadcConfig { 47 let adc_config = LpadcConfig {
54 enable_in_doze_mode: true, 48 enable_in_doze_mode: true,
55 conversion_average_mode: CalAvgs::Average128, 49 conversion_average_mode: CalAvgs::Average128,
56 enable_analog_preliminary: true, 50 enable_analog_preliminary: true,
57 power_up_delay: 0x80, 51 power_up_delay: 0x80,
58 reference_voltage_source: Refsel::Option3, 52 reference_voltage_source: Refsel::Option3,
59 power_level_mode: Pwrsel::Lowest, 53 power_level_mode: Pwrsel::Lowest,
60 trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, 54 trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed,
61 enable_conv_pause: false, 55 enable_conv_pause: false,
62 conv_pause_delay: 0, 56 conv_pause_delay: 0,
63 fifo_watermark: 0, 57 fifo_watermark: 0,
64 }; 58 };
65 let adc = hal::adc::Adc::<hal::adc::Adc1>::new(p.ADC1, adc_config); 59 let adc = hal::adc::Adc::<hal::adc::Adc1>::new(p.ADC1, adc_config);
66 60
@@ -78,7 +72,7 @@ async fn main(_spawner: Spawner) {
78 adc.set_conv_trigger_config(0, &conv_trigger_config); 72 adc.set_conv_trigger_config(0, &conv_trigger_config);
79 73
80 uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); 74 uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n");
81 75
82 adc.enable_interrupt(0x1); 76 adc.enable_interrupt(0x1);
83 77
84 unsafe { 78 unsafe {
@@ -92,15 +86,9 @@ async fn main(_spawner: Spawner) {
92 loop { 86 loop {
93 adc.do_software_trigger(1); 87 adc.do_software_trigger(1);
94 while !adc.is_interrupt_triggered() { 88 while !adc.is_interrupt_triggered() {
95 // Wait until the interrupt is triggered 89 // Wait until the interrupt is triggered
96 } 90 }
97 uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n"); 91 uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n");
98 //TBD need to print the value 92 //TBD need to print the value
99 } 93 }
100} 94}
101
102#[cfg(not(feature = "defmt"))]
103#[panic_handler]
104fn panic(_info: &core::panic::PanicInfo) -> ! {
105 loop {}
106} \ No newline at end of file
diff --git a/examples/adc_polling.rs b/examples/adc_polling.rs
index 7cb728e91..90be87c3f 100644
--- a/examples/adc_polling.rs
+++ b/examples/adc_polling.rs
@@ -5,27 +5,21 @@ use embassy_mcxa276 as hal;
5 5
6use embassy_executor::Spawner; 6use embassy_executor::Spawner;
7 7
8use hal::adc::{TriggerPriorityPolicy, LpadcConfig, ConvResult}; 8use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy};
9use hal::pac::adc1::cfg::{Refsel, Pwrsel}; 9use hal::pac::adc1::cfg::{Pwrsel, Refsel};
10use hal::pac::adc1::tctrl::{Tcmd};
11use hal::pac::adc1::cmdl1::{Adch, Mode}; 10use hal::pac::adc1::cmdl1::{Adch, Mode};
12use hal::pac::adc1::ctrl::{CalAvgs}; 11use hal::pac::adc1::ctrl::CalAvgs;
12use hal::pac::adc1::tctrl::Tcmd;
13 13
14use hal::uart; 14use hal::uart;
15 15
16mod common; 16mod common;
17 17
18#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] 18use {defmt_rtt as _, panic_probe as _};
19use defmt_rtt as _;
20#[cfg(feature = "defmt")]
21use panic_probe as _;
22#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
23use rtt_target as _;
24 19
25use core::fmt::Write; 20use core::fmt::Write;
26use heapless::String; 21use heapless::String;
27 22
28
29const G_LPADC_RESULT_SHIFT: u32 = 0; 23const G_LPADC_RESULT_SHIFT: u32 = 0;
30 24
31#[embassy_executor::main] 25#[embassy_executor::main]
@@ -44,19 +38,18 @@ async fn main(_spawner: Spawner) {
44 unsafe { 38 unsafe {
45 common::init_adc(hal::pac()); 39 common::init_adc(hal::pac());
46 } 40 }
47 41
48
49 let adc_config = LpadcConfig { 42 let adc_config = LpadcConfig {
50 enable_in_doze_mode: true, 43 enable_in_doze_mode: true,
51 conversion_average_mode: CalAvgs::Average128, 44 conversion_average_mode: CalAvgs::Average128,
52 enable_analog_preliminary: true, 45 enable_analog_preliminary: true,
53 power_up_delay: 0x80, 46 power_up_delay: 0x80,
54 reference_voltage_source: Refsel::Option3, 47 reference_voltage_source: Refsel::Option3,
55 power_level_mode: Pwrsel::Lowest, 48 power_level_mode: Pwrsel::Lowest,
56 trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed, 49 trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed,
57 enable_conv_pause: false, 50 enable_conv_pause: false,
58 conv_pause_delay: 0, 51 conv_pause_delay: 0,
59 fifo_watermark: 0, 52 fifo_watermark: 0,
60 }; 53 };
61 let adc = hal::adc::Adc::<hal::adc::Adc1>::new(p.ADC1, adc_config); 54 let adc = hal::adc::Adc::<hal::adc::Adc1>::new(p.ADC1, adc_config);
62 55
@@ -74,7 +67,7 @@ async fn main(_spawner: Spawner) {
74 adc.set_conv_trigger_config(0, &conv_trigger_config); 67 adc.set_conv_trigger_config(0, &conv_trigger_config);
75 68
76 uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n"); 69 uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n");
77 70
78 loop { 71 loop {
79 adc.do_software_trigger(1); 72 adc.do_software_trigger(1);
80 let mut result: Option<ConvResult> = None; 73 let mut result: Option<ConvResult> = None;
@@ -87,9 +80,3 @@ async fn main(_spawner: Spawner) {
87 uart.write_str_blocking(&buf); 80 uart.write_str_blocking(&buf);
88 } 81 }
89} 82}
90
91#[cfg(not(feature = "defmt"))]
92#[panic_handler]
93fn panic(_info: &core::panic::PanicInfo) -> ! {
94 loop {}
95} \ No newline at end of file
diff --git a/examples/blink.rs b/examples/blink.rs
index 6289ac14e..a9b6e7093 100644
--- a/examples/blink.rs
+++ b/examples/blink.rs
@@ -85,9 +85,3 @@ async fn main(_spawner: Spawner) {
85 Timer::after(Duration::from_millis(1000)).await; 85 Timer::after(Duration::from_millis(1000)).await;
86 } 86 }
87} 87}
88
89#[cfg(not(feature = "defmt"))]
90#[panic_handler]
91fn panic(_info: &core::panic::PanicInfo) -> ! {
92 loop {}
93}
diff --git a/examples/hello.rs b/examples/hello.rs
index 591bf2460..e39adaced 100644
--- a/examples/hello.rs
+++ b/examples/hello.rs
@@ -7,12 +7,7 @@ use hal::uart;
7 7
8mod common; 8mod common;
9 9
10#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] 10use {defmt_rtt as _, panic_probe as _};
11use defmt_rtt as _;
12#[cfg(feature = "defmt")]
13use panic_probe as _;
14#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
15use rtt_target as _;
16 11
17/// Simple helper to write a byte as hex to UART 12/// Simple helper to write a byte as hex to UART
18fn write_hex_byte(uart: &hal::uart::Uart<hal::uart::Lpuart2>, byte: u8) { 13fn write_hex_byte(uart: &hal::uart::Uart<hal::uart::Lpuart2>, byte: u8) {
@@ -25,7 +20,6 @@ fn write_hex_byte(uart: &hal::uart::Uart<hal::uart::Lpuart2>, byte: u8) {
25async fn main(_spawner: Spawner) { 20async fn main(_spawner: Spawner) {
26 let p = hal::init(hal::config::Config::default()); 21 let p = hal::init(hal::config::Config::default());
27 22
28 #[cfg(feature = "defmt")]
29 defmt::info!("boot"); 23 defmt::info!("boot");
30 24
31 // Board-level init for UART2 clocks and pins. 25 // Board-level init for UART2 clocks and pins.
@@ -118,9 +112,3 @@ fn parse_u8(bytes: &[u8]) -> Result<u8, ()> {
118 } 112 }
119 Ok(result) 113 Ok(result)
120} 114}
121
122#[cfg(not(feature = "defmt"))]
123#[panic_handler]
124fn panic(_info: &core::panic::PanicInfo) -> ! {
125 loop {}
126}
diff --git a/examples/lpuart_buffered.rs b/examples/lpuart_buffered.rs
index 88f256096..d0d4d2ee0 100644
--- a/examples/lpuart_buffered.rs
+++ b/examples/lpuart_buffered.rs
@@ -80,9 +80,3 @@ async fn main(_spawner: Spawner) {
80 tx.write_all(&buf[..]).await.unwrap(); 80 tx.write_all(&buf[..]).await.unwrap();
81 } 81 }
82} 82}
83
84#[cfg(not(feature = "defmt"))]
85#[panic_handler]
86fn panic(_info: &core::panic::PanicInfo) -> ! {
87 loop {}
88}
diff --git a/examples/lpuart_polling.rs b/examples/lpuart_polling.rs
index c83c959e8..f9172de40 100644
--- a/examples/lpuart_polling.rs
+++ b/examples/lpuart_polling.rs
@@ -1,16 +1,11 @@
1#![no_std] 1#![no_std]
2#![no_main] 2#![no_main]
3 3
4use crate::hal::lpuart::{lib, Config, Lpuart}; 4use crate::hal::lpuart::{Config, Lpuart, lib};
5use embassy_executor::Spawner; 5use embassy_executor::Spawner;
6use embassy_mcxa276 as hal; 6use embassy_mcxa276 as hal;
7 7
8#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] 8use {defmt_rtt as _, panic_probe as _};
9use defmt_rtt as _;
10#[cfg(feature = "defmt")]
11use panic_probe as _;
12#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
13use rtt_target as _;
14 9
15mod common; 10mod common;
16 11
@@ -19,7 +14,6 @@ async fn main(_spawner: Spawner) {
19 let _p = hal::init(hal::config::Config::default()); 14 let _p = hal::init(hal::config::Config::default());
20 let p2 = lib::init(); 15 let p2 = lib::init();
21 16
22 #[cfg(feature = "defmt")]
23 defmt::info!("boot"); 17 defmt::info!("boot");
24 18
25 // Board-level init for UART2 clocks and pins. 19 // Board-level init for UART2 clocks and pins.
@@ -59,9 +53,3 @@ async fn main(_spawner: Spawner) {
59 tx.blocking_write(&buf).unwrap(); 53 tx.blocking_write(&buf).unwrap();
60 } 54 }
61} 55}
62
63#[cfg(not(feature = "defmt"))]
64#[panic_handler]
65fn panic(_info: &core::panic::PanicInfo) -> ! {
66 loop {}
67}
diff --git a/examples/ostimer_alarm.rs b/examples/ostimer_alarm.rs
index 823e37c15..eca669509 100644
--- a/examples/ostimer_alarm.rs
+++ b/examples/ostimer_alarm.rs
@@ -9,12 +9,7 @@ use hal::uart;
9 9
10mod common; 10mod common;
11 11
12#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] 12use {defmt_rtt as _, panic_probe as _};
13use defmt_rtt as _;
14#[cfg(feature = "defmt")]
15use panic_probe as _;
16#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
17use rtt_target as _;
18 13
19use embassy_mcxa276::bind_interrupts; 14use embassy_mcxa276::bind_interrupts;
20 15
@@ -61,7 +56,8 @@ async fn main(_spawner: Spawner) {
61 init_match_max: true, 56 init_match_max: true,
62 clock_frequency_hz: 1_000_000, // 1MHz 57 clock_frequency_hz: 1_000_000, // 1MHz
63 }; 58 };
64 let ostimer = hal::ostimer::Ostimer::<hal::ostimer::Ostimer0>::new(p.OSTIMER0, config, hal::pac()); 59 let ostimer =
60 hal::ostimer::Ostimer::<hal::ostimer::Ostimer0>::new(p.OSTIMER0, config, hal::pac());
65 61
66 // Create alarm with callback 62 // Create alarm with callback
67 let alarm = hal::ostimer::Alarm::new() 63 let alarm = hal::ostimer::Alarm::new()
@@ -118,9 +114,3 @@ async fn main(_spawner: Spawner) {
118 114
119 uart.write_str_blocking("Example complete\n"); 115 uart.write_str_blocking("Example complete\n");
120} 116}
121
122#[cfg(not(feature = "defmt"))]
123#[panic_handler]
124fn panic(_info: &core::panic::PanicInfo) -> ! {
125 loop {}
126}
diff --git a/examples/ostimer_async.rs b/examples/ostimer_async.rs
index 181ce58ef..37fb3b3d1 100644
--- a/examples/ostimer_async.rs
+++ b/examples/ostimer_async.rs
@@ -7,16 +7,9 @@ use hal::uart;
7 7
8mod common; 8mod common;
9 9
10#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
11use defmt_rtt as _;
12#[cfg(feature = "defmt")]
13use panic_probe as _;
14#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
15use rtt_target as _;
16
17use embassy_time::{Duration, Timer};
18
19use embassy_mcxa276::bind_interrupts; 10use embassy_mcxa276::bind_interrupts;
11use embassy_time::{Duration, Timer};
12use {defmt_rtt as _, panic_probe as _};
20 13
21// Bind only OS_EVENT, and retain the symbol explicitly so it can’t be GC’ed. 14// Bind only OS_EVENT, and retain the symbol explicitly so it can’t be GC’ed.
22bind_interrupts!(struct Irqs { 15bind_interrupts!(struct Irqs {
@@ -57,20 +50,11 @@ async fn main(_spawner: Spawner) {
57 // Removed force-pend; rely on real hardware match to trigger OS_EVENT. 50 // Removed force-pend; rely on real hardware match to trigger OS_EVENT.
58 51
59 // Log using defmt if enabled 52 // Log using defmt if enabled
60 #[cfg(feature = "defmt")]
61 defmt::info!("OSTIMER async example starting..."); 53 defmt::info!("OSTIMER async example starting...");
62 54
63 loop { 55 loop {
64 #[cfg(feature = "defmt")]
65 defmt::info!("tick"); 56 defmt::info!("tick");
66 #[cfg(not(feature = "defmt"))]
67 uart.write_str_blocking("tick\n"); 57 uart.write_str_blocking("tick\n");
68 Timer::after(Duration::from_millis(1000)).await; 58 Timer::after(Duration::from_millis(1000)).await;
69 } 59 }
70} 60}
71
72#[cfg(not(feature = "defmt"))]
73#[panic_handler]
74fn panic(_info: &core::panic::PanicInfo) -> ! {
75 loop {}
76}
diff --git a/examples/ostimer_counter.rs b/examples/ostimer_counter.rs
index 3af0f03f2..1f5bdf434 100644
--- a/examples/ostimer_counter.rs
+++ b/examples/ostimer_counter.rs
@@ -9,12 +9,7 @@
9use embassy_executor::Spawner; 9use embassy_executor::Spawner;
10use embassy_time::{Duration, Timer}; 10use embassy_time::{Duration, Timer};
11 11
12#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] 12use {defmt_rtt as _, panic_probe as _};
13use defmt_rtt as _;
14#[cfg(feature = "defmt")]
15use panic_probe as _;
16#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
17use rtt_target as _;
18 13
19use embassy_mcxa276 as hal; 14use embassy_mcxa276 as hal;
20use hal::bind_interrupts; 15use hal::bind_interrupts;
@@ -37,7 +32,8 @@ async fn main(_spawner: Spawner) {
37 common::init_uart2(hal::pac()); 32 common::init_uart2(hal::pac());
38 } 33 }
39 let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; 34 let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) };
40 let mut uart = hal::uart::Uart::<hal::uart::Lpuart2>::new(p.LPUART2, hal::uart::Config::new(src)); 35 let mut uart =
36 hal::uart::Uart::<hal::uart::Lpuart2>::new(p.LPUART2, hal::uart::Config::new(src));
41 37
42 uart.write_str_blocking("OSTIMER Counter Reading and Reset Example\n"); 38 uart.write_str_blocking("OSTIMER Counter Reading and Reset Example\n");
43 39
@@ -134,9 +130,3 @@ fn write_u64(uart: &mut hal::uart::Uart<hal::uart::Lpuart2>, value: u64) {
134 } 130 }
135 } 131 }
136} 132}
137
138#[cfg(not(feature = "defmt"))]
139#[panic_handler]
140fn panic(_info: &core::panic::PanicInfo) -> ! {
141 loop {}
142}
diff --git a/examples/ostimer_race_test.rs b/examples/ostimer_race_test.rs
index 4470b65fd..072310309 100644
--- a/examples/ostimer_race_test.rs
+++ b/examples/ostimer_race_test.rs
@@ -12,16 +12,10 @@
12use embassy_executor::Spawner; 12use embassy_executor::Spawner;
13use embassy_time::{Duration, Timer}; 13use embassy_time::{Duration, Timer};
14 14
15#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
16use defmt_rtt as _;
17#[cfg(feature = "defmt")]
18use panic_probe as _;
19#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
20use rtt_target as _;
21
22use core::sync::atomic::{AtomicU32, Ordering}; 15use core::sync::atomic::{AtomicU32, Ordering};
23use embassy_mcxa276 as hal; 16use embassy_mcxa276 as hal;
24use hal::bind_interrupts; 17use hal::bind_interrupts;
18use {defmt_rtt as _, panic_probe as _};
25 19
26mod common; 20mod common;
27 21
@@ -86,7 +80,8 @@ async fn main(_spawner: Spawner) {
86 common::init_uart2(hal::pac()); 80 common::init_uart2(hal::pac());
87 } 81 }
88 let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) }; 82 let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) };
89 let mut uart = hal::uart::Uart::<hal::uart::Lpuart2>::new(p.LPUART2, hal::uart::Config::new(src)); 83 let mut uart =
84 hal::uart::Uart::<hal::uart::Lpuart2>::new(p.LPUART2, hal::uart::Config::new(src));
90 85
91 uart.write_str_blocking("OSTIMER Race Condition Test Starting...\n"); 86 uart.write_str_blocking("OSTIMER Race Condition Test Starting...\n");
92 87
@@ -403,9 +398,3 @@ fn write_u64(uart: &mut hal::uart::Uart<hal::uart::Lpuart2>, value: u64) {
403 } 398 }
404 } 399 }
405} 400}
406
407#[cfg(not(feature = "defmt"))]
408#[panic_handler]
409fn panic(_info: &core::panic::PanicInfo) -> ! {
410 loop {}
411}
diff --git a/examples/rtc_alarm.rs b/examples/rtc_alarm.rs
index 8f4ff1623..a190b8ba5 100644
--- a/examples/rtc_alarm.rs
+++ b/examples/rtc_alarm.rs
@@ -1,26 +1,21 @@
1#![no_std] 1#![no_std]
2#![no_main] 2#![no_main]
3 3
4
5use embassy_mcxa276 as hal;
6use cortex_m; 4use cortex_m;
7use embassy_executor::Spawner; 5use embassy_executor::Spawner;
6use embassy_mcxa276 as hal;
7use hal::InterruptExt;
8use hal::rtc::{RtcDateTime, RtcInterruptEnable}; 8use hal::rtc::{RtcDateTime, RtcInterruptEnable};
9use hal::uart; 9use hal::uart;
10use hal::InterruptExt;
11 10
12mod common; 11mod common;
13 12
14type MyRtc = hal::rtc::Rtc<hal::rtc::Rtc0>; 13type MyRtc = hal::rtc::Rtc<hal::rtc::Rtc0>;
15 14
16#[cfg(all(feature = "defmt", feature = "defmt-rtt"))] 15use {defmt_rtt as _, panic_probe as _};
17use defmt_rtt as _;
18#[cfg(feature = "defmt")]
19use panic_probe as _;
20#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
21use rtt_target as _;
22 16
23use embassy_mcxa276::bind_interrupts; 17use embassy_mcxa276::bind_interrupts;
18
24bind_interrupts!(struct Irqs { 19bind_interrupts!(struct Irqs {
25 RTC => hal::rtc::RtcHandler; 20 RTC => hal::rtc::RtcHandler;
26}); 21});
@@ -31,7 +26,6 @@ static KEEP_RTC: unsafe extern "C" fn() = RTC;
31 26
32#[embassy_executor::main] 27#[embassy_executor::main]
33async fn main(_spawner: Spawner) { 28async fn main(_spawner: Spawner) {
34
35 let p = hal::init(hal::config::Config::default()); 29 let p = hal::init(hal::config::Config::default());
36 30
37 unsafe { 31 unsafe {
@@ -58,12 +52,11 @@ async fn main(_spawner: Spawner) {
58 second: 0, 52 second: 0,
59 }; 53 };
60 54
61
62 rtc.stop(); 55 rtc.stop();
63 56
64 uart.write_str_blocking("Time set to: 2025-10-15 14:30:00\r\n"); 57 uart.write_str_blocking("Time set to: 2025-10-15 14:30:00\r\n");
65 rtc.set_datetime(now); 58 rtc.set_datetime(now);
66 59
67 let mut alarm = now; 60 let mut alarm = now;
68 alarm.second += 10; 61 alarm.second += 10;
69 62
@@ -92,14 +85,6 @@ async fn main(_spawner: Spawner) {
92 } 85 }
93 86
94 uart.write_str_blocking("Example complete - Test PASSED!\r\n"); 87 uart.write_str_blocking("Example complete - Test PASSED!\r\n");
95
96 loop {
97
98 }
99}
100 88
101#[cfg(not(feature = "defmt"))]
102#[panic_handler]
103fn panic(_info: &core::panic::PanicInfo) -> ! {
104 loop {} 89 loop {}
105} 90}
diff --git a/examples/uart_interrupt.rs b/examples/uart_interrupt.rs
index 85743bb64..bd734f859 100644
--- a/examples/uart_interrupt.rs
+++ b/examples/uart_interrupt.rs
@@ -8,14 +8,8 @@ use hal::uart;
8 8
9mod common; 9mod common;
10 10
11#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
12use defmt_rtt as _;
13#[cfg(feature = "defmt")]
14use panic_probe as _;
15#[cfg(all(feature = "defmt", feature = "defmt-rtt"))]
16use rtt_target as _;
17
18use embassy_mcxa276::bind_interrupts; 11use embassy_mcxa276::bind_interrupts;
12use {defmt_rtt as _, panic_probe as _};
19 13
20// Bind LPUART2 interrupt to our handler 14// Bind LPUART2 interrupt to our handler
21bind_interrupts!(struct Irqs { 15bind_interrupts!(struct Irqs {
@@ -57,7 +51,6 @@ async fn main(_spawner: Spawner) {
57 uart.write_str_blocking("Type characters to echo them back.\r\n"); 51 uart.write_str_blocking("Type characters to echo them back.\r\n");
58 52
59 // Log using defmt if enabled 53 // Log using defmt if enabled
60 #[cfg(feature = "defmt")]
61 defmt::info!("UART interrupt echo demo starting..."); 54 defmt::info!("UART interrupt echo demo starting...");
62 55
63 loop { 56 loop {
@@ -74,15 +67,3 @@ async fn main(_spawner: Spawner) {
74 } 67 }
75 } 68 }
76} 69}
77
78#[cfg(feature = "defmt")]
79#[export_name = "_defmt_timestamp"]
80fn defmt_timestamp(_fmt: defmt::Formatter<'_>) {
81 // Return empty timestamp for now
82}
83
84#[cfg(not(feature = "defmt"))]
85#[panic_handler]
86fn panic(_info: &core::panic::PanicInfo) -> ! {
87 loop {}
88}
diff --git a/src/adc.rs b/src/adc.rs
index f56d744c6..5625330e9 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -1,12 +1,12 @@
1//! ADC driver 1//! ADC driver
2use crate::pac; 2use crate::pac;
3use core::sync::atomic::{AtomicBool, Ordering}; 3use core::sync::atomic::{AtomicBool, Ordering};
4 4
5use crate::pac::adc1::ctrl::{CalAvgs}; 5use crate::pac::adc1::cfg::{HptExdi, Pwrsel, Refsel, Tcmdres, Tprictrl, Tres};
6use crate::pac::adc1::cfg::{Refsel, Pwrsel, Tprictrl, Tres, Tcmdres, HptExdi}; 6use crate::pac::adc1::cmdh1::{Avgs, Cmpen, Next, Sts};
7use crate::pac::adc1::tctrl::{Tcmd, Tpri};
8use crate::pac::adc1::cmdl1::{Adch, Ctype, Mode}; 7use crate::pac::adc1::cmdl1::{Adch, Ctype, Mode};
9use crate::pac::adc1::cmdh1::{Next, Avgs, Sts, Cmpen}; 8use crate::pac::adc1::ctrl::CalAvgs;
9use crate::pac::adc1::tctrl::{Tcmd, Tpri};
10 10
11type Regs = pac::adc1::RegisterBlock; 11type Regs = pac::adc1::RegisterBlock;
12 12
@@ -17,9 +17,7 @@ pub trait Instance {
17} 17}
18 18
19/// Token for ADC1 19/// Token for ADC1
20#[cfg(feature = "adc1")]
21pub type Adc1 = crate::peripherals::ADC1; 20pub type Adc1 = crate::peripherals::ADC1;
22#[cfg(feature = "adc1")]
23impl Instance for crate::peripherals::ADC1 { 21impl Instance for crate::peripherals::ADC1 {
24 #[inline(always)] 22 #[inline(always)]
25 fn ptr() -> *const Regs { 23 fn ptr() -> *const Regs {
@@ -28,7 +26,6 @@ impl Instance for crate::peripherals::ADC1 {
28} 26}
29 27
30// Also implement Instance for the Peri wrapper type 28// Also implement Instance for the Peri wrapper type
31#[cfg(feature = "adc1")]
32impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::ADC1> { 29impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::ADC1> {
33 #[inline(always)] 30 #[inline(always)]
34 fn ptr() -> *const Regs { 31 fn ptr() -> *const Regs {
@@ -97,16 +94,15 @@ pub struct ConvResult {
97 pub conv_value: u16, 94 pub conv_value: u16,
98} 95}
99 96
100
101pub struct Adc<I: Instance> { 97pub struct Adc<I: Instance> {
102 _inst: core::marker::PhantomData<I>, 98 _inst: core::marker::PhantomData<I>,
103} 99}
104 100
105impl<I: Instance> Adc<I> { 101impl<I: Instance> Adc<I> {
106 /// initialize ADC 102 /// initialize ADC
107 pub fn new(_inst: impl Instance, config : LpadcConfig) -> Self { 103 pub fn new(_inst: impl Instance, config: LpadcConfig) -> Self {
108 let adc = unsafe { &*I::ptr() }; 104 let adc = unsafe { &*I::ptr() };
109 105
110 /* Reset the module. */ 106 /* Reset the module. */
111 adc.ctrl().modify(|_, w| w.rst().held_in_reset()); 107 adc.ctrl().modify(|_, w| w.rst().held_in_reset());
112 adc.ctrl().modify(|_, w| w.rst().released_from_reset()); 108 adc.ctrl().modify(|_, w| w.rst().released_from_reset());
@@ -124,64 +120,81 @@ impl<I: Instance> Adc<I> {
124 } 120 }
125 121
126 /* Set calibration average mode. */ 122 /* Set calibration average mode. */
127 adc.ctrl().modify(|_, w| w.cal_avgs().variant(config.conversion_average_mode)); 123 adc.ctrl()
128 124 .modify(|_, w| w.cal_avgs().variant(config.conversion_average_mode));
129 adc.cfg().write(|w| unsafe { 125
126 adc.cfg().write(|w| unsafe {
130 let w = if config.enable_analog_preliminary { 127 let w = if config.enable_analog_preliminary {
131 w.pwren().pre_enabled() 128 w.pwren().pre_enabled()
132 } else { 129 } else {
133 w 130 w
134 }; 131 };
135 132
136 w.pudly().bits(config.power_up_delay) 133 w.pudly()
137 .refsel().variant(config.reference_voltage_source) 134 .bits(config.power_up_delay)
138 .pwrsel().variant(config.power_level_mode) 135 .refsel()
139 .tprictrl().variant(match config.trigger_priority_policy { 136 .variant(config.reference_voltage_source)
140 TriggerPriorityPolicy::ConvPreemptSoftlyNotAutoResumed | 137 .pwrsel()
141 TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted | 138 .variant(config.power_level_mode)
142 TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => Tprictrl::FinishCurrentOnPriority, 139 .tprictrl()
143 TriggerPriorityPolicy::ConvPreemptSubsequentlyNotAutoResumed | 140 .variant(match config.trigger_priority_policy {
144 TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted | 141 TriggerPriorityPolicy::ConvPreemptSoftlyNotAutoResumed
145 TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tprictrl::FinishSequenceOnPriority, 142 | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted
146 _ => Tprictrl::AbortCurrentOnPriority, 143 | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => {
147 }) 144 Tprictrl::FinishCurrentOnPriority
148 .tres().variant(match config.trigger_priority_policy { 145 }
149 TriggerPriorityPolicy::ConvPreemptImmediatelyAutoRestarted | 146 TriggerPriorityPolicy::ConvPreemptSubsequentlyNotAutoResumed
150 TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted | 147 | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted
151 TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed | 148 | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => {
152 TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed | 149 Tprictrl::FinishSequenceOnPriority
153 TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted | 150 }
154 TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tres::Enabled, 151 _ => Tprictrl::AbortCurrentOnPriority,
155 _ => Tres::Disabled, 152 })
156 }) 153 .tres()
157 .tcmdres().variant(match config.trigger_priority_policy { 154 .variant(match config.trigger_priority_policy {
158 TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed | 155 TriggerPriorityPolicy::ConvPreemptImmediatelyAutoRestarted
159 TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed | 156 | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted
160 TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed | 157 | TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed
161 TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => Tcmdres::Enabled, 158 | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed
162 _ => Tcmdres::Disabled, 159 | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted
163 }) 160 | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tres::Enabled,
164 .hpt_exdi().variant(match config.trigger_priority_policy { 161 _ => Tres::Disabled,
165 TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => HptExdi::Disabled, 162 })
166 _ => HptExdi::Enabled, 163 .tcmdres()
167 }) 164 .variant(match config.trigger_priority_policy {
168 }); 165 TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed
166 | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed
167 | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed
168 | TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => Tcmdres::Enabled,
169 _ => Tcmdres::Disabled,
170 })
171 .hpt_exdi()
172 .variant(match config.trigger_priority_policy {
173 TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => HptExdi::Disabled,
174 _ => HptExdi::Enabled,
175 })
176 });
169 177
170 if config.enable_conv_pause { 178 if config.enable_conv_pause {
171 adc.pause().modify(|_, w| unsafe { 179 adc.pause().modify(|_, w| unsafe {
172 w.pauseen().enabled() 180 w.pauseen()
173 .pausedly().bits(config.conv_pause_delay) 181 .enabled()
182 .pausedly()
183 .bits(config.conv_pause_delay)
174 }); 184 });
175 } else { 185 } else {
176 adc.pause().write(|w| unsafe { w.bits(0) }); 186 adc.pause().write(|w| unsafe { w.bits(0) });
177 } 187 }
178 188
179 adc.fctrl0().write(|w| unsafe { w.fwmark().bits(config.fifo_watermark) }); 189 adc.fctrl0()
190 .write(|w| unsafe { w.fwmark().bits(config.fifo_watermark) });
180 191
181 // Enable ADC 192 // Enable ADC
182 adc.ctrl().modify(|_, w| w.adcen().enabled()); 193 adc.ctrl().modify(|_, w| w.adcen().enabled());
183 194
184 Self { _inst: core::marker::PhantomData } 195 Self {
196 _inst: core::marker::PhantomData,
197 }
185 } 198 }
186 199
187 pub fn deinit(&self) { 200 pub fn deinit(&self) {
@@ -189,7 +202,6 @@ impl<I: Instance> Adc<I> {
189 adc.ctrl().modify(|_, w| w.adcen().disabled()); 202 adc.ctrl().modify(|_, w| w.adcen().disabled());
190 } 203 }
191 204
192
193 pub fn get_default_config() -> LpadcConfig { 205 pub fn get_default_config() -> LpadcConfig {
194 LpadcConfig { 206 LpadcConfig {
195 enable_in_doze_mode: true, 207 enable_in_doze_mode: true,
@@ -208,13 +220,14 @@ impl<I: Instance> Adc<I> {
208 pub fn do_offset_calibration(&self) { 220 pub fn do_offset_calibration(&self) {
209 let adc = unsafe { &*I::ptr() }; 221 let adc = unsafe { &*I::ptr() };
210 // Enable calibration mode 222 // Enable calibration mode
211 adc.ctrl().modify(|_, w| w.calofs().offset_calibration_request_pending()); 223 adc.ctrl()
224 .modify(|_, w| w.calofs().offset_calibration_request_pending());
212 225
213 // Wait for calibration to complete (polling status register) 226 // Wait for calibration to complete (polling status register)
214 while adc.stat().read().cal_rdy().is_not_set() {} 227 while adc.stat().read().cal_rdy().is_not_set() {}
215 } 228 }
216 229
217 pub fn get_gain_conv_result(&self, mut gain_adjustment: f32) -> u32{ 230 pub fn get_gain_conv_result(&self, mut gain_adjustment: f32) -> u32 {
218 let mut gcra_array = [0u32; 17]; 231 let mut gcra_array = [0u32; 17];
219 let mut gcalr: u32 = 0; 232 let mut gcalr: u32 = 0;
220 233
@@ -234,20 +247,21 @@ impl<I: Instance> Adc<I> {
234 247
235 pub fn do_auto_calibration(&self) { 248 pub fn do_auto_calibration(&self) {
236 let adc = unsafe { &*I::ptr() }; 249 let adc = unsafe { &*I::ptr() };
237 adc.ctrl().modify(|_, w| w.cal_req().calibration_request_pending()); 250 adc.ctrl()
251 .modify(|_, w| w.cal_req().calibration_request_pending());
238 252
239 while adc.gcc0().read().rdy().is_gain_cal_not_valid() {} 253 while adc.gcc0().read().rdy().is_gain_cal_not_valid() {}
240 254
241
242 let mut gcca = adc.gcc0().read().gain_cal().bits() as u32; 255 let mut gcca = adc.gcc0().read().gain_cal().bits() as u32;
243 if gcca & (((0xFFFF >> 0) + 1) >> 1) != 0 { 256 if gcca & (((0xFFFF >> 0) + 1) >> 1) != 0 {
244 gcca |= !0xFFFF; 257 gcca |= !0xFFFF;
245 } 258 }
246 259
247 let gcra = 131072.0 / (131072.0 - gcca as f32); 260 let gcra = 131072.0 / (131072.0 - gcca as f32);
248 261
249 // Write to GCR0 262 // Write to GCR0
250 adc.gcr0().write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) }); 263 adc.gcr0()
264 .write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) });
251 265
252 adc.gcr0().modify(|_, w| w.rdy().set_bit()); 266 adc.gcr0().modify(|_, w| w.rdy().set_bit());
253 267
@@ -284,15 +298,22 @@ impl<I: Instance> Adc<I> {
284 match index { 298 match index {
285 1 => { 299 1 => {
286 adc.cmdl1().write(|w| { 300 adc.cmdl1().write(|w| {
287 w.adch().variant(config.channel_number) 301 w.adch()
288 .mode().variant(config.conversion_resolution_mode) 302 .variant(config.channel_number)
303 .mode()
304 .variant(config.conversion_resolution_mode)
289 }); 305 });
290 adc.cmdh1().write(|w| unsafe { 306 adc.cmdh1().write(|w| unsafe {
291 w.next().variant(config.chained_next_command_number) 307 w.next()
292 .loop_().bits(config.loop_count) 308 .variant(config.chained_next_command_number)
293 .avgs().variant(config.hardware_average_mode) 309 .loop_()
294 .sts().variant(config.sample_time_mode) 310 .bits(config.loop_count)
295 .cmpen().variant(config.hardware_compare_mode); 311 .avgs()
312 .variant(config.hardware_average_mode)
313 .sts()
314 .variant(config.sample_time_mode)
315 .cmpen()
316 .variant(config.hardware_compare_mode);
296 if config.enable_wait_trigger { 317 if config.enable_wait_trigger {
297 w.wait_trig().enabled(); 318 w.wait_trig().enabled();
298 } 319 }
@@ -371,5 +392,7 @@ pub fn on_interrupt() {
371 392
372pub struct AdcHandler; 393pub struct AdcHandler;
373impl crate::interrupt::typelevel::Handler<crate::interrupt::typelevel::ADC1> for AdcHandler { 394impl crate::interrupt::typelevel::Handler<crate::interrupt::typelevel::ADC1> for AdcHandler {
374 unsafe fn on_interrupt() { on_interrupt(); } 395 unsafe fn on_interrupt() {
396 on_interrupt();
397 }
375} 398}
diff --git a/src/clocks.rs b/src/clocks.rs
index 5336c3efe..95d7ad567 100644
--- a/src/clocks.rs
+++ b/src/clocks.rs
@@ -112,10 +112,10 @@ pub unsafe fn init_fro16k(peripherals: &pac::Peripherals) {
112 let vbat = &peripherals.vbat0; 112 let vbat = &peripherals.vbat0;
113 // Enable FRO16K oscillator 113 // Enable FRO16K oscillator
114 vbat.froctla().modify(|_, w| w.fro_en().set_bit()); 114 vbat.froctla().modify(|_, w| w.fro_en().set_bit());
115 115
116 // Lock the control register 116 // Lock the control register
117 vbat.frolcka().modify(|_, w| w.lock().set_bit()); 117 vbat.frolcka().modify(|_, w| w.lock().set_bit());
118 118
119 // Enable clock outputs to both VSYS and VDD_CORE domains 119 // Enable clock outputs to both VSYS and VDD_CORE domains
120 // Bit 0: clk_16k0 to VSYS domain 120 // Bit 0: clk_16k0 to VSYS domain
121 // Bit 1: clk_16k1 to VDD_CORE domain 121 // Bit 1: clk_16k1 to VDD_CORE domain
@@ -130,7 +130,6 @@ pub unsafe fn enable_adc(peripherals: &pac::Peripherals) {
130pub unsafe fn select_adc_clock(peripherals: &pac::Peripherals) { 130pub unsafe fn select_adc_clock(peripherals: &pac::Peripherals) {
131 // Use FRO_LF_DIV (already running) MUX=0 DIV=0 131 // Use FRO_LF_DIV (already running) MUX=0 DIV=0
132 let mrcc = &peripherals.mrcc0; 132 let mrcc = &peripherals.mrcc0;
133 mrcc.mrcc_adc_clksel() 133 mrcc.mrcc_adc_clksel().write(|w| w.mux().clkroot_func_0());
134 .write(|w| w.mux().clkroot_func_0());
135 mrcc.mrcc_adc_clkdiv().write(|w| unsafe { w.bits(0) }); 134 mrcc.mrcc_adc_clkdiv().write(|w| unsafe { w.bits(0) });
136} \ No newline at end of file 135}
diff --git a/src/gpio.rs b/src/gpio.rs
index 08f375cba..faeefd333 100644
--- a/src/gpio.rs
+++ b/src/gpio.rs
@@ -66,7 +66,7 @@ pub trait PinId {
66} 66}
67 67
68pub mod pins { 68pub mod pins {
69 use super::{pac, AnyPin, PinId}; 69 use super::{AnyPin, PinId, pac};
70 70
71 macro_rules! define_pin { 71 macro_rules! define_pin {
72 ($Name:ident, $port:literal, $pin:literal, $GpioBlk:ident) => { 72 ($Name:ident, $port:literal, $pin:literal, $GpioBlk:ident) => {
diff --git a/src/interrupt.rs b/src/interrupt.rs
index 8226f01ab..d91e6479a 100644
--- a/src/interrupt.rs
+++ b/src/interrupt.rs
@@ -6,8 +6,8 @@ mod generated {
6 embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART2, RTC, ADC1); 6 embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART2, RTC, ADC1);
7} 7}
8 8
9pub use generated::interrupt::typelevel;
10pub use generated::interrupt::Priority; 9pub use generated::interrupt::Priority;
10pub use generated::interrupt::typelevel;
11 11
12use crate::pac::Interrupt; 12use crate::pac::Interrupt;
13use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; 13use core::sync::atomic::{AtomicU16, AtomicU32, Ordering};
diff --git a/src/lib.rs b/src/lib.rs
index eb4727106..518fe01d2 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,31 +1,19 @@
1#![no_std] 1#![no_std]
2 2
3pub mod clocks; // still provide clock helpers 3pub mod clocks; // still provide clock helpers
4#[cfg(feature = "gpio")]
5pub mod gpio; 4pub mod gpio;
6pub mod pins; // pin mux helpers 5pub mod pins; // pin mux helpers
7pub mod reset; // reset control helpers 6pub mod reset; // reset control helpers
8 7
8pub mod adc;
9pub mod config; 9pub mod config;
10pub mod interrupt; 10pub mod interrupt;
11pub mod ostimer;
12pub mod uart;
13pub mod lpuart; 11pub mod lpuart;
12pub mod ostimer;
14pub mod rtc; 13pub mod rtc;
15pub mod adc; 14pub mod uart;
16 15
17embassy_hal_internal::peripherals!( 16embassy_hal_internal::peripherals!(LPUART2, OSTIMER0, GPIO, RTC0, ADC1,);
18 #[cfg(feature = "lpuart2")]
19 LPUART2,
20 #[cfg(feature = "ostimer0")]
21 OSTIMER0,
22 #[cfg(feature = "gpio")]
23 GPIO,
24 #[cfg(feature = "rtc0")]
25 RTC0,
26 #[cfg(feature = "adc1")]
27 ADC1,
28);
29 17
30/// Get access to the PAC Peripherals for low-level register access. 18/// Get access to the PAC Peripherals for low-level register access.
31/// This is a lazy-initialized singleton that can be called after init(). 19/// This is a lazy-initialized singleton that can be called after init().
@@ -42,43 +30,32 @@ pub fn pac() -> &'static pac::Peripherals {
42 } 30 }
43} 31}
44 32
45pub use cortex_m_rt; 33#[cfg(feature = "unstable-pac")]
46pub use mcxa276_pac as pac; 34pub use mcxa_pac as pac;
35#[cfg(not(feature = "unstable-pac"))]
36pub(crate) use mcxa_pac as pac;
37
47// Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it. 38// Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it.
48 39
49// Re-export interrupt traits and types 40// Re-export interrupt traits and types
41pub use adc::Adc1 as Adc1Token;
42pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output, pins::*};
50pub use interrupt::InterruptExt; 43pub use interrupt::InterruptExt;
51#[cfg(feature = "ostimer0")]
52pub use ostimer::Ostimer0 as Ostimer0Token; 44pub use ostimer::Ostimer0 as Ostimer0Token;
53#[cfg(feature = "lpuart2")]
54pub use uart::Lpuart2 as Uart2Token;
55#[cfg(feature = "rtc0")]
56pub use rtc::Rtc0 as Rtc0Token; 45pub use rtc::Rtc0 as Rtc0Token;
57#[cfg(feature = "adc1")] 46pub use uart::Lpuart2 as Uart2Token;
58pub use adc::Adc1 as Adc1Token;
59#[cfg(feature = "gpio")]
60pub use gpio::{pins::*, AnyPin, Flex, Gpio as GpioToken, Input, Level, Output};
61 47
62/// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals. 48/// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals.
63/// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling). 49/// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling).
64#[allow(unused_variables)] 50#[allow(unused_variables)]
65pub fn init(cfg: crate::config::Config) -> Peripherals { 51pub fn init(cfg: crate::config::Config) -> Peripherals {
66 let peripherals = Peripherals::take(); 52 let peripherals = Peripherals::take();
67 #[cfg(feature = "ostimer0")] 53 // Apply user-configured priority early; enabling is left to examples/apps
68 { 54 crate::interrupt::OS_EVENT.set_priority(cfg.time_interrupt_priority);
69 // Apply user-configured priority early; enabling is left to examples/apps 55 // Apply user-configured priority early; enabling is left to examples/apps
70 crate::interrupt::OS_EVENT.set_priority(cfg.time_interrupt_priority); 56 crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority);
71 } 57 // Apply user-configured priority early; enabling is left to examples/apps
72 #[cfg(feature = "rtc0")] 58 crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority);
73 {
74 // Apply user-configured priority early; enabling is left to examples/apps
75 crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority);
76 }
77 #[cfg(feature = "adc1")]
78 {
79 // Apply user-configured priority early; enabling is left to examples/apps
80 crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority);
81 }
82 peripherals 59 peripherals
83} 60}
84 61
diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs
index 03673d975..e2382e86d 100644
--- a/src/lpuart/buffered.rs
+++ b/src/lpuart/buffered.rs
@@ -3,8 +3,8 @@ use core::marker::PhantomData;
3use core::sync::atomic::{AtomicBool, Ordering}; 3use core::sync::atomic::{AtomicBool, Ordering};
4use core::task::Poll; 4use core::task::Poll;
5 5
6use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
7use embassy_hal_internal::Peri; 6use embassy_hal_internal::Peri;
7use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
8use embassy_sync::waitqueue::AtomicWaker; 8use embassy_sync::waitqueue::AtomicWaker;
9 9
10use super::*; 10use super::*;
diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs
index 431547f86..99f4a4a66 100644
--- a/src/lpuart/mod.rs
+++ b/src/lpuart/mod.rs
@@ -6,7 +6,7 @@ use paste::paste;
6use crate::pac; 6use crate::pac;
7use crate::pac::lpuart0::baud::Sbns as StopBits; 7use crate::pac::lpuart0::baud::Sbns as StopBits;
8use crate::pac::lpuart0::ctrl::{ 8use crate::pac::lpuart0::ctrl::{
9 Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits, 9 Idlecfg as IdleConfig, Ilt as IdleType, M as DataBits, Pt as Parity,
10}; 10};
11use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; 11use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource};
12use crate::pac::lpuart0::stat::Msbf as MsbFirst; 12use crate::pac::lpuart0::stat::Msbf as MsbFirst;
diff --git a/src/ostimer.rs b/src/ostimer.rs
index b9688313a..6a4188db0 100644
--- a/src/ostimer.rs
+++ b/src/ostimer.rs
@@ -493,10 +493,8 @@ pub trait Instance {
493} 493}
494 494
495// Token for OSTIMER0 provided by embassy-hal-internal peripherals macro. 495// Token for OSTIMER0 provided by embassy-hal-internal peripherals macro.
496#[cfg(feature = "ostimer0")]
497pub type Ostimer0 = crate::peripherals::OSTIMER0; 496pub type Ostimer0 = crate::peripherals::OSTIMER0;
498 497
499#[cfg(feature = "ostimer0")]
500impl Instance for crate::peripherals::OSTIMER0 { 498impl Instance for crate::peripherals::OSTIMER0 {
501 #[inline(always)] 499 #[inline(always)]
502 fn ptr() -> *const Regs { 500 fn ptr() -> *const Regs {
@@ -505,7 +503,6 @@ impl Instance for crate::peripherals::OSTIMER0 {
505} 503}
506 504
507// Also implement Instance for the Peri wrapper type 505// Also implement Instance for the Peri wrapper type
508#[cfg(feature = "ostimer0")]
509impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::OSTIMER0> { 506impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::OSTIMER0> {
510 #[inline(always)] 507 #[inline(always)]
511 fn ptr() -> *const Regs { 508 fn ptr() -> *const Regs {
@@ -528,11 +525,10 @@ fn gray_to_bin(gray: u64) -> u64 {
528 bin 525 bin
529} 526}
530 527
531#[cfg(feature = "ostimer0")]
532pub mod time_driver { 528pub mod time_driver {
533 use super::{ 529 use super::{
534 bin_to_gray, now_ticks_read, Regs, ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, 530 ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, EVTIMER_HI_MASK,
535 ALARM_TARGET_TIME, EVTIMER_HI_MASK, EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, 531 EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, Regs, bin_to_gray, now_ticks_read,
536 }; 532 };
537 use crate::pac; 533 use crate::pac;
538 use core::sync::atomic::Ordering; 534 use core::sync::atomic::Ordering;
diff --git a/src/pins.rs b/src/pins.rs
index d46a3e6b3..1d92f9fef 100644
--- a/src/pins.rs
+++ b/src/pins.rs
@@ -57,7 +57,6 @@ pub unsafe fn configure_adc_pins() {
57 .inv0() 57 .inv0()
58 .lk() 58 .lk()
59 .lk0() 59 .lk0()
60
61 }); 60 });
62 core::arch::asm!("dsb sy; isb sy"); 61 core::arch::asm!("dsb sy; isb sy");
63} 62}
diff --git a/src/rtc.rs b/src/rtc.rs
index f83baab5e..5e3dfe6c1 100644
--- a/src/rtc.rs
+++ b/src/rtc.rs
@@ -1,6 +1,6 @@
1//! RTC DateTime driver. 1//! RTC DateTime driver.
2use crate::pac; 2use crate::pac;
3use crate::pac::rtc0::cr::{Um}; 3use crate::pac::rtc0::cr::Um;
4use core::sync::atomic::{AtomicBool, Ordering}; 4use core::sync::atomic::{AtomicBool, Ordering};
5 5
6type Regs = pac::rtc0::RegisterBlock; 6type Regs = pac::rtc0::RegisterBlock;
@@ -13,9 +13,7 @@ pub trait Instance {
13} 13}
14 14
15/// Token for RTC0 15/// Token for RTC0
16#[cfg(feature = "rtc0")]
17pub type Rtc0 = crate::peripherals::RTC0; 16pub type Rtc0 = crate::peripherals::RTC0;
18#[cfg(feature = "rtc0")]
19impl Instance for crate::peripherals::RTC0 { 17impl Instance for crate::peripherals::RTC0 {
20 #[inline(always)] 18 #[inline(always)]
21 fn ptr() -> *const Regs { 19 fn ptr() -> *const Regs {
@@ -24,7 +22,6 @@ impl Instance for crate::peripherals::RTC0 {
24} 22}
25 23
26// Also implement Instance for the Peri wrapper type 24// Also implement Instance for the Peri wrapper type
27#[cfg(feature = "rtc0")]
28impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::RTC0> { 25impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::RTC0> {
29 #[inline(always)] 26 #[inline(always)]
30 fn ptr() -> *const Regs { 27 fn ptr() -> *const Regs {
@@ -87,7 +84,6 @@ pub fn convert_datetime_to_seconds(datetime: &RtcDateTime) -> u32 {
87 seconds 84 seconds
88} 85}
89 86
90
91pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime { 87pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime {
92 let mut seconds_remaining = seconds; 88 let mut seconds_remaining = seconds;
93 let mut days = seconds_remaining / SECONDS_IN_A_DAY + 1; 89 let mut days = seconds_remaining / SECONDS_IN_A_DAY + 1;
@@ -166,11 +162,15 @@ impl<I: Instance> Rtc<I> {
166 rtc.cr().modify(|_, w| w.um().variant(config.update_mode)); 162 rtc.cr().modify(|_, w| w.um().variant(config.update_mode));
167 163
168 rtc.tcr().modify(|_, w| unsafe { 164 rtc.tcr().modify(|_, w| unsafe {
169 w.cir().bits(config.compensation_interval) 165 w.cir()
170 .tcr().bits(config.compensation_time) 166 .bits(config.compensation_interval)
167 .tcr()
168 .bits(config.compensation_time)
171 }); 169 });
172 170
173 Self { _inst: core::marker::PhantomData } 171 Self {
172 _inst: core::marker::PhantomData,
173 }
174 } 174 }
175 175
176 pub fn set_datetime(&self, datetime: RtcDateTime) { 176 pub fn set_datetime(&self, datetime: RtcDateTime) {
@@ -178,7 +178,7 @@ impl<I: Instance> Rtc<I> {
178 let seconds = convert_datetime_to_seconds(&datetime); 178 let seconds = convert_datetime_to_seconds(&datetime);
179 rtc.tsr().write(|w| unsafe { w.bits(seconds) }); 179 rtc.tsr().write(|w| unsafe { w.bits(seconds) });
180 } 180 }
181 181
182 pub fn get_datetime(&self) -> RtcDateTime { 182 pub fn get_datetime(&self) -> RtcDateTime {
183 let rtc = unsafe { &*I::ptr() }; 183 let rtc = unsafe { &*I::ptr() };
184 let seconds = rtc.tsr().read().bits(); 184 let seconds = rtc.tsr().read().bits();
@@ -203,7 +203,7 @@ impl<I: Instance> Rtc<I> {
203 } 203 }
204 } 204 }
205 205
206 pub fn get_alarm(&self) -> RtcDateTime{ 206 pub fn get_alarm(&self) -> RtcDateTime {
207 let rtc = unsafe { &*I::ptr() }; 207 let rtc = unsafe { &*I::ptr() };
208 let alarm_seconds = rtc.tar().read().bits(); 208 let alarm_seconds = rtc.tar().read().bits();
209 convert_seconds_to_datetime(alarm_seconds) 209 convert_seconds_to_datetime(alarm_seconds)
@@ -264,7 +264,7 @@ impl<I: Instance> Rtc<I> {
264 ALARM_TRIGGERED.load(Ordering::Relaxed) 264 ALARM_TRIGGERED.load(Ordering::Relaxed)
265 } 265 }
266} 266}
267 267
268pub fn on_interrupt() { 268pub fn on_interrupt() {
269 let rtc = unsafe { &*pac::Rtc0::ptr() }; 269 let rtc = unsafe { &*pac::Rtc0::ptr() };
270 // Check if this is actually a time alarm interrupt 270 // Check if this is actually a time alarm interrupt
@@ -277,5 +277,7 @@ pub fn on_interrupt() {
277 277
278pub struct RtcHandler; 278pub struct RtcHandler;
279impl crate::interrupt::typelevel::Handler<crate::interrupt::typelevel::RTC> for RtcHandler { 279impl crate::interrupt::typelevel::Handler<crate::interrupt::typelevel::RTC> for RtcHandler {
280 unsafe fn on_interrupt() { on_interrupt(); } 280 unsafe fn on_interrupt() {
281} \ No newline at end of file 281 on_interrupt();
282 }
283}
diff --git a/src/uart.rs b/src/uart.rs
index 45b6b2be3..65dd91492 100644
--- a/src/uart.rs
+++ b/src/uart.rs
@@ -15,9 +15,7 @@ pub trait Instance {
15} 15}
16 16
17/// Token for LPUART2 provided by embassy-hal-internal peripherals macro. 17/// Token for LPUART2 provided by embassy-hal-internal peripherals macro.
18#[cfg(feature = "lpuart2")]
19pub type Lpuart2 = crate::peripherals::LPUART2; 18pub type Lpuart2 = crate::peripherals::LPUART2;
20#[cfg(feature = "lpuart2")]
21impl Instance for crate::peripherals::LPUART2 { 19impl Instance for crate::peripherals::LPUART2 {
22 #[inline(always)] 20 #[inline(always)]
23 fn ptr() -> *const Regs { 21 fn ptr() -> *const Regs {
@@ -26,7 +24,6 @@ impl Instance for crate::peripherals::LPUART2 {
26} 24}
27 25
28// Also implement Instance for the Peri wrapper type 26// Also implement Instance for the Peri wrapper type
29#[cfg(feature = "lpuart2")]
30impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::LPUART2> { 27impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::LPUART2> {
31 #[inline(always)] 28 #[inline(always)]
32 fn ptr() -> *const Regs { 29 fn ptr() -> *const Regs {
@@ -111,7 +108,7 @@ impl<I: Instance> Uart<I> {
111 cortex_m::asm::delay(3); // Short delay for reset to take effect 108 cortex_m::asm::delay(3); // Short delay for reset to take effect
112 l.global().write(|w| w.rst().no_effect()); 109 l.global().write(|w| w.rst().no_effect());
113 cortex_m::asm::delay(10); // Allow peripheral to stabilize after reset 110 cortex_m::asm::delay(10); // Allow peripheral to stabilize after reset
114 // 2) BAUD 111 // 2) BAUD
115 let (osr, sbr) = compute_osr_sbr(cfg.src_hz, cfg.baud); 112 let (osr, sbr) = compute_osr_sbr(cfg.src_hz, cfg.baud);
116 l.baud().modify(|_, w| { 113 l.baud().modify(|_, w| {
117 let w = match cfg.stop_bits { 114 let w = match cfg.stop_bits {
@@ -145,7 +142,9 @@ impl<I: Instance> Uart<I> {
145 }); 142 });
146 l.water() 143 l.water()
147 .modify(|_, w| unsafe { w.txwater().bits(0).rxwater().bits(0) }); 144 .modify(|_, w| unsafe { w.txwater().bits(0).rxwater().bits(0) });
148 Self { _inst: core::marker::PhantomData } 145 Self {
146 _inst: core::marker::PhantomData,
147 }
149 } 148 }
150 149
151 /// Enable RX interrupts. The caller must ensure an appropriate IRQ handler is installed. 150 /// Enable RX interrupts. The caller must ensure an appropriate IRQ handler is installed.