Merge #589

589: stm32/i2c: allow empty writes r=Dirbaio a=darkwater

The Senseair Sunrise CO2 sensor expects a wake-up packet in the form of (START, address, STOP), which looks like a `write(addr, &[])`, but this assertion prevents sending that.

I'm not sure why the assertion is there. Sending empty packets works fine in my limited testing, at least.

Co-authored-by: Sam Lakerveld <[email protected]>

2 files changed, 26 insertions, 8 deletions

diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index b7067a9c4..3b22faca7 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -130,7 +130,7 @@ mod transfers {
         reg_addr: *mut W,
         buf: &'a mut [W],
     ) -> impl Future<Output = ()> + 'a {
-        assert!(buf.len() <= 0xFFFF);
+        assert!(buf.len() > 0 && buf.len() <= 0xFFFF);
         unborrow!(channel);
 
         unsafe { channel.start_read::<W>(request, reg_addr, buf) };
@@ -145,7 +145,7 @@ mod transfers {
         buf: &'a [W],
         reg_addr: *mut W,
     ) -> impl Future<Output = ()> + 'a {
-        assert!(buf.len() <= 0xFFFF);
+        assert!(buf.len() > 0 && buf.len() <= 0xFFFF);
         unborrow!(channel);
 
         unsafe { channel.start_write::<W>(request, buf, reg_addr) };
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index af04dc061..5b0e5fce2 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -139,7 +139,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
     }
 
     unsafe fn master_read(address: u8, length: usize, stop: Stop, reload: bool, restart: bool) {
-        assert!(length < 256 && length > 0);
+        assert!(length < 256);
 
         if !restart {
             // Wait for any previous address sequence to end
@@ -170,7 +170,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
     }
 
     unsafe fn master_write(address: u8, length: usize, stop: Stop, reload: bool) {
-        assert!(length < 256 && length > 0);
+        assert!(length < 256);
 
         // Wait for any previous address sequence to end
         // automatically. This could be up to 50% of a bus
@@ -577,7 +577,11 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
     where
         TXDMA: crate::i2c::TxDma<T>,
     {
-        self.write_dma_internal(address, bytes, true, true).await
+        if bytes.is_empty() {
+            self.write_internal(address, bytes, true)
+        } else {
+            self.write_dma_internal(address, bytes, true, true).await
+        }
     }
 
     pub async fn write_vectored(&mut self, address: u8, bytes: &[&[u8]]) -> Result<(), Error>
@@ -606,7 +610,11 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
     where
         RXDMA: crate::i2c::RxDma<T>,
     {
-        self.read_dma_internal(address, buffer, false).await
+        if buffer.is_empty() {
+            self.read_internal(address, buffer, false)
+        } else {
+            self.read_dma_internal(address, buffer, false).await
+        }
     }
 
     pub async fn write_read(
@@ -619,8 +627,18 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
         TXDMA: super::TxDma<T>,
         RXDMA: super::RxDma<T>,
     {
-        self.write_dma_internal(address, bytes, true, true).await?;
-        self.read_dma_internal(address, buffer, true).await?;
+        if bytes.is_empty() {
+            self.write_internal(address, bytes, false)?;
+        } else {
+            self.write_dma_internal(address, bytes, true, true).await?;
+        }
+
+        if buffer.is_empty() {
+            self.read_internal(address, buffer, true)?;
+        } else {
+            self.read_dma_internal(address, buffer, true).await?;
+        }
+
         Ok(())
     }