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authorUlf Lilleengen <[email protected]>2021-11-24 14:59:18 +0100
committerUlf Lilleengen <[email protected]>2021-11-24 14:59:18 +0100
commitcd9a1d547c3e377bd7c0f6743a27218b38b2f491 (patch)
treef2949b29a4defb6d7064f13889620b2bc1b9e935
parent8fea6c94f6d0978042554eb6b154706d8f7a9fd5 (diff)
Ensure SPI DMA write is completed
Fix a bug where DMA writes were not fully completed and only a single byte out of two were written.
-rw-r--r--embassy-stm32/src/spi/v2.rs13
1 files changed, 11 insertions, 2 deletions
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs
index 9b8a74d7b..488e80ef8 100644
--- a/embassy-stm32/src/spi/v2.rs
+++ b/embassy-stm32/src/spi/v2.rs
@@ -17,7 +17,7 @@ use embassy::util::Unborrow;
17use embassy_hal_common::unborrow; 17use embassy_hal_common::unborrow;
18use embassy_traits::spi as traits; 18use embassy_traits::spi as traits;
19pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; 19pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
20use futures::future::join3; 20use futures::future::{join, join3};
21 21
22impl WordSize { 22impl WordSize {
23 fn ds(&self) -> spi::vals::Ds { 23 fn ds(&self) -> spi::vals::Ds {
@@ -186,7 +186,16 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
186 }); 186 });
187 } 187 }
188 188
189 f.await; 189 join(f, Self::wait_for_idle()).await;
190
191 unsafe {
192 T::regs().cr2().modify(|reg| {
193 reg.set_txdmaen(false);
194 });
195 T::regs().cr1().modify(|w| {
196 w.set_spe(false);
197 });
198 }
190 Ok(()) 199 Ok(())
191 } 200 }
192 201