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authorPeter Gibson <[email protected]>2023-06-15 18:35:58 +1000
committerPeter Gibson <[email protected]>2023-06-15 18:35:58 +1000
commitd236f3dbf9b53c5e646020946d8da1458eb591a1 (patch)
tree6e74eb416189f4d05fe7890b93952d7511afeb2d
parentd23717904b283fa46a02525acfb42eb9f42e61e3 (diff)
actually fix formatting
-rw-r--r--embassy-stm32/src/usart/buffered.rs6
1 files changed, 2 insertions, 4 deletions
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index e04b3ea0f..530760bd1 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -24,8 +24,7 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
24 // Reading DR clears the rxne, error and idle interrupt flags on v1. 24 // Reading DR clears the rxne, error and idle interrupt flags on v1.
25 let dr = if sr.ore() || sr.idle() || sr.rxne() { 25 let dr = if sr.ore() || sr.idle() || sr.rxne() {
26 Some(rdr(r).read_volatile()) 26 Some(rdr(r).read_volatile())
27 } 27 } else {
28 else {
29 None 28 None
30 }; 29 };
31 clear_interrupt_flags(r, sr); 30 clear_interrupt_flags(r, sr);
@@ -48,8 +47,7 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
48 if !buf.is_empty() { 47 if !buf.is_empty() {
49 buf[0] = dr.unwrap(); 48 buf[0] = dr.unwrap();
50 rx_writer.push_done(1); 49 rx_writer.push_done(1);
51 } 50 } else {
52 else {
53 // FIXME: Should we disable any further RX interrupts when the buffer becomes full. 51 // FIXME: Should we disable any further RX interrupts when the buffer becomes full.
54 } 52 }
55 53