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| author | Dario Nieuwenhuis <[email protected]> | 2025-09-10 12:46:29 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2025-09-10 12:46:29 +0000 |
| commit | d860530009c1bf96a20edeff22f10f738bab1503 (patch) | |
| tree | 88be1895b3f2ece9836463a96e04afa58cef3c88 | |
| parent | c9baf4ec09a628c281dda79a9631b211a8cb99d8 (diff) | |
| parent | 88c4274547db9fe6e6e720c69e61c4912fe03abd (diff) | |
Merge pull request #4648 from birktj/stm32-blocking-uart-flush
stm32/usart: fix blocking flush
| -rw-r--r-- | embassy-stm32/CHANGELOG.md | 1 | ||||
| -rw-r--r-- | embassy-stm32/src/usart/buffered.rs | 4 |
2 files changed, 4 insertions, 1 deletions
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md index ba565f663..4ea11b664 100644 --- a/embassy-stm32/CHANGELOG.md +++ b/embassy-stm32/CHANGELOG.md | |||
| @@ -15,6 +15,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 | |||
| 15 | - Add I2S support for STM32F1, STM32C0, STM32F0, STM32F3, STM32F7, STM32G0, STM32WL, STM32H5, STM32H7RS | 15 | - Add I2S support for STM32F1, STM32C0, STM32F0, STM32F3, STM32F7, STM32G0, STM32WL, STM32H5, STM32H7RS |
| 16 | - fix: STM32: Prevent dropped DacChannel from disabling Dac peripheral if another DacChannel is still in scope ([#4577](https://github.com/embassy-rs/embassy/pull/4577)) | 16 | - fix: STM32: Prevent dropped DacChannel from disabling Dac peripheral if another DacChannel is still in scope ([#4577](https://github.com/embassy-rs/embassy/pull/4577)) |
| 17 | - feat: Added support for more OctoSPI configurations (e.g. APS6408 RAM) ([#4581](https://github.com/embassy-rs/embassy/pull/4581)) | 17 | - feat: Added support for more OctoSPI configurations (e.g. APS6408 RAM) ([#4581](https://github.com/embassy-rs/embassy/pull/4581)) |
| 18 | - fix: stm32/usart: fix bug with blocking flush in buffered uart ([#4648](https://github.com/embassy-rs/embassy/pull/4648)) | ||
| 18 | 19 | ||
| 19 | ## 0.4.0 - 2025-08-26 | 20 | ## 0.4.0 - 2025-08-26 |
| 20 | 21 | ||
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs index 890c8a80e..c734eed49 100644 --- a/embassy-stm32/src/usart/buffered.rs +++ b/embassy-stm32/src/usart/buffered.rs | |||
| @@ -692,6 +692,8 @@ impl<'d> BufferedUartTx<'d> { | |||
| 692 | fn blocking_write(&self, buf: &[u8]) -> Result<usize, Error> { | 692 | fn blocking_write(&self, buf: &[u8]) -> Result<usize, Error> { |
| 693 | loop { | 693 | loop { |
| 694 | let state = self.state; | 694 | let state = self.state; |
| 695 | state.tx_done.store(false, Ordering::Release); | ||
| 696 | |||
| 695 | let empty = state.tx_buf.is_empty(); | 697 | let empty = state.tx_buf.is_empty(); |
| 696 | 698 | ||
| 697 | let mut tx_writer = unsafe { state.tx_buf.writer() }; | 699 | let mut tx_writer = unsafe { state.tx_buf.writer() }; |
| @@ -713,7 +715,7 @@ impl<'d> BufferedUartTx<'d> { | |||
| 713 | fn blocking_flush(&self) -> Result<(), Error> { | 715 | fn blocking_flush(&self) -> Result<(), Error> { |
| 714 | loop { | 716 | loop { |
| 715 | let state = self.state; | 717 | let state = self.state; |
| 716 | if state.tx_buf.is_empty() { | 718 | if state.tx_done.load(Ordering::Acquire) { |
| 717 | return Ok(()); | 719 | return Ok(()); |
| 718 | } | 720 | } |
| 719 | } | 721 | } |
