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authorxoviat <[email protected]>2023-11-01 22:31:43 +0000
committerGitHub <[email protected]>2023-11-01 22:31:43 +0000
commitd98c064bfe303038a8b0a465aa18d1c305c8a3bb (patch)
tree0110be2b2612107b10ec02e3470bce8fbcd94b5a
parent4ef3dc5b904de8e7bf8fc63816637610bb0d3c8b (diff)
parenta9045385550d3b72d61e9387acd6336c1bab6984 (diff)
Merge pull request #2134 from xoviat/revert-rcc
stm32/rcc: revert part of #2106
-rw-r--r--embassy-stm32/src/rcc/f4f7.rs23
1 files changed, 6 insertions, 17 deletions
diff --git a/embassy-stm32/src/rcc/f4f7.rs b/embassy-stm32/src/rcc/f4f7.rs
index 3102600a1..2e4f95722 100644
--- a/embassy-stm32/src/rcc/f4f7.rs
+++ b/embassy-stm32/src/rcc/f4f7.rs
@@ -152,9 +152,9 @@ pub(crate) unsafe fn init(config: Config) {
152 source: config.pll_src, 152 source: config.pll_src,
153 }; 153 };
154 let pll = init_pll(PllInstance::Pll, config.pll, &pll_input); 154 let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
155 #[cfg(any(all(stm32f4, not(any(stm32f410, stm32f429))), stm32f7))] 155 #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
156 let _plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input); 156 let _plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input);
157 #[cfg(all(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7), not(stm32f429)))] 157 #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
158 let _pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input); 158 let _pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input);
159 159
160 // Configure sysclk 160 // Configure sysclk
@@ -197,25 +197,15 @@ pub(crate) unsafe fn init(config: Config) {
197 pclk2_tim, 197 pclk2_tim,
198 rtc, 198 rtc,
199 pll1_q: pll.q, 199 pll1_q: pll.q,
200 #[cfg(all(rcc_f4, not(any(stm32f410, stm32f429))))] 200 #[cfg(all(rcc_f4, not(stm32f410)))]
201 plli2s1_q: _plli2s.q, 201 plli2s1_q: _plli2s.q,
202 #[cfg(all(rcc_f4, not(any(stm32f410, stm32f429))))] 202 #[cfg(all(rcc_f4, not(stm32f410)))]
203 plli2s1_r: _plli2s.r, 203 plli2s1_r: _plli2s.r,
204 204
205 #[cfg(stm32f429)] 205 #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
206 plli2s1_q: None,
207 #[cfg(stm32f429)]
208 plli2s1_r: None,
209
210 #[cfg(any(stm32f427, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
211 pllsai1_q: _pllsai.q, 206 pllsai1_q: _pllsai.q,
212 #[cfg(any(stm32f427, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))] 207 #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
213 pllsai1_r: _pllsai.r, 208 pllsai1_r: _pllsai.r,
214
215 #[cfg(stm32f429)]
216 pllsai1_q: None,
217 #[cfg(stm32f429)]
218 pllsai1_r: None,
219 }); 209 });
220} 210}
221 211
@@ -233,7 +223,6 @@ struct PllOutput {
233 r: Option<Hertz>, 223 r: Option<Hertz>,
234} 224}
235 225
236#[allow(dead_code)]
237#[derive(PartialEq, Eq, Clone, Copy)] 226#[derive(PartialEq, Eq, Clone, Copy)]
238enum PllInstance { 227enum PllInstance {
239 Pll, 228 Pll,