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authori509VCB <[email protected]>2025-10-18 20:58:09 -0500
committeri509VCB <[email protected]>2025-10-18 20:58:09 -0500
commitda5a563489757b9803074d6bddf0bf1b2d7f13d0 (patch)
treea3354ba2add985350d65409018f227871317cf94
parent2a79c55d4d38e95f90a8efcf93a3e28f4d6ad35f (diff)
nxp/lpc55: move usart ALT pin definitions to impl_xx_pin macros
-rw-r--r--embassy-nxp/CHANGELOG.md1
-rw-r--r--embassy-nxp/src/usart/lpc55.rs139
2 files changed, 88 insertions, 52 deletions
diff --git a/embassy-nxp/CHANGELOG.md b/embassy-nxp/CHANGELOG.md
index 295d45c2d..ad8670854 100644
--- a/embassy-nxp/CHANGELOG.md
+++ b/embassy-nxp/CHANGELOG.md
@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
7 7
8<!-- next-header --> 8<!-- next-header -->
9## Unreleased - ReleaseDate 9## Unreleased - ReleaseDate
10- LPC55: Move ALT definitions for USART to TX/RX pin impls.
10- LPC55: Remove internal match_iocon macro 11- LPC55: Remove internal match_iocon macro
11- LPC55: DMA Controller and asynchronous version of USART 12- LPC55: DMA Controller and asynchronous version of USART
12- Moved NXP LPC55S69 from `lpc55-pac` to `nxp-pac` 13- Moved NXP LPC55S69 from `lpc55-pac` to `nxp-pac`
diff --git a/embassy-nxp/src/usart/lpc55.rs b/embassy-nxp/src/usart/lpc55.rs
index 6cbde82a3..d54927b25 100644
--- a/embassy-nxp/src/usart/lpc55.rs
+++ b/embassy-nxp/src/usart/lpc55.rs
@@ -146,7 +146,8 @@ impl<'d, M: Mode> UsartTx<'d, M> {
146 tx_dma: Peri<'d, impl Channel>, 146 tx_dma: Peri<'d, impl Channel>,
147 config: Config, 147 config: Config,
148 ) -> Self { 148 ) -> Self {
149 Usart::<M>::init::<T>(Some(tx.into()), None, config); 149 let tx_func = tx.pin_func();
150 Usart::<M>::init::<T>(Some((tx.into(), tx_func)), None, config);
150 Self::new_inner(T::info(), Some(tx_dma.into())) 151 Self::new_inner(T::info(), Some(tx_dma.into()))
151 } 152 }
152 153
@@ -179,7 +180,8 @@ impl<'d, M: Mode> UsartTx<'d, M> {
179 180
180impl<'d> UsartTx<'d, Blocking> { 181impl<'d> UsartTx<'d, Blocking> {
181 pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self { 182 pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self {
182 Usart::<Blocking>::init::<T>(Some(tx.into()), None, config); 183 let tx_func = tx.pin_func();
184 Usart::<Blocking>::init::<T>(Some((tx.into(), tx_func)), None, config);
183 Self::new_inner(T::info(), None) 185 Self::new_inner(T::info(), None)
184 } 186 }
185} 187}
@@ -208,7 +210,8 @@ impl<'d, M: Mode> UsartRx<'d, M> {
208 rx_dma: Peri<'d, impl Channel>, 210 rx_dma: Peri<'d, impl Channel>,
209 config: Config, 211 config: Config,
210 ) -> Self { 212 ) -> Self {
211 Usart::<M>::init::<T>(None, Some(rx.into()), config); 213 let rx_func = rx.pin_func();
214 Usart::<M>::init::<T>(None, Some((rx.into(), rx_func)), config);
212 Self::new_inner(T::info(), T::dma_state(), has_irq, Some(rx_dma.into())) 215 Self::new_inner(T::info(), T::dma_state(), has_irq, Some(rx_dma.into()))
213 } 216 }
214 217
@@ -280,7 +283,8 @@ impl<'d, M: Mode> UsartRx<'d, M> {
280 283
281impl<'d> UsartRx<'d, Blocking> { 284impl<'d> UsartRx<'d, Blocking> {
282 pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self { 285 pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self {
283 Usart::<Blocking>::init::<T>(None, Some(rx.into()), config); 286 let rx_func = rx.pin_func();
287 Usart::<Blocking>::init::<T>(None, Some((rx.into(), rx_func)), config);
284 Self::new_inner(T::info(), T::dma_state(), false, None) 288 Self::new_inner(T::info(), T::dma_state(), false, None)
285 } 289 }
286} 290}
@@ -405,7 +409,10 @@ impl<'d> Usart<'d, Blocking> {
405 rx: Peri<'d, impl RxPin<T>>, 409 rx: Peri<'d, impl RxPin<T>>,
406 config: Config, 410 config: Config,
407 ) -> Self { 411 ) -> Self {
408 Self::new_inner(usart, tx.into(), rx.into(), false, None, None, config) 412 let tx_func = tx.pin_func();
413 let rx_func = rx.pin_func();
414
415 Self::new_inner(usart, tx.into(), tx_func, rx.into(), rx_func, false, None, None, config)
409 } 416 }
410} 417}
411 418
@@ -419,10 +426,15 @@ impl<'d> Usart<'d, Async> {
419 rx_dma: Peri<'d, impl RxChannel<T>>, 426 rx_dma: Peri<'d, impl RxChannel<T>>,
420 config: Config, 427 config: Config,
421 ) -> Self { 428 ) -> Self {
429 let tx_func = tx.pin_func();
430 let rx_func = rx.pin_func();
431
422 Self::new_inner( 432 Self::new_inner(
423 uart, 433 uart,
424 tx.into(), 434 tx.into(),
435 tx_func,
425 rx.into(), 436 rx.into(),
437 rx_func,
426 true, 438 true,
427 Some(tx_dma.into()), 439 Some(tx_dma.into()),
428 Some(rx_dma.into()), 440 Some(rx_dma.into()),
@@ -435,20 +447,26 @@ impl<'d, M: Mode> Usart<'d, M> {
435 fn new_inner<T: Instance>( 447 fn new_inner<T: Instance>(
436 _usart: Peri<'d, T>, 448 _usart: Peri<'d, T>,
437 mut tx: Peri<'d, AnyPin>, 449 mut tx: Peri<'d, AnyPin>,
450 tx_func: PioFunc,
438 mut rx: Peri<'d, AnyPin>, 451 mut rx: Peri<'d, AnyPin>,
452 rx_func: PioFunc,
439 has_irq: bool, 453 has_irq: bool,
440 tx_dma: Option<Peri<'d, AnyChannel>>, 454 tx_dma: Option<Peri<'d, AnyChannel>>,
441 rx_dma: Option<Peri<'d, AnyChannel>>, 455 rx_dma: Option<Peri<'d, AnyChannel>>,
442 config: Config, 456 config: Config,
443 ) -> Self { 457 ) -> Self {
444 Self::init::<T>(Some(tx.reborrow()), Some(rx.reborrow()), config); 458 Self::init::<T>(Some((tx.reborrow(), tx_func)), Some((rx.reborrow(), rx_func)), config);
445 Self { 459 Self {
446 tx: UsartTx::new_inner(T::info(), tx_dma), 460 tx: UsartTx::new_inner(T::info(), tx_dma),
447 rx: UsartRx::new_inner(T::info(), T::dma_state(), has_irq, rx_dma), 461 rx: UsartRx::new_inner(T::info(), T::dma_state(), has_irq, rx_dma),
448 } 462 }
449 } 463 }
450 464
451 fn init<T: Instance>(tx: Option<Peri<'_, AnyPin>>, rx: Option<Peri<'_, AnyPin>>, config: Config) { 465 fn init<T: Instance>(
466 tx: Option<(Peri<'_, AnyPin>, PioFunc)>,
467 rx: Option<(Peri<'_, AnyPin>, PioFunc)>,
468 config: Config,
469 ) {
452 Self::configure_flexcomm(T::info().fc_reg, T::instance_number()); 470 Self::configure_flexcomm(T::info().fc_reg, T::instance_number());
453 Self::configure_clock::<T>(&config); 471 Self::configure_clock::<T>(&config);
454 Self::pin_config::<T>(tx, rx); 472 Self::pin_config::<T>(tx, rx);
@@ -553,10 +571,10 @@ impl<'d, M: Mode> Usart<'d, M> {
553 .modify(|w| w.set_brgval((brg_value - 1) as u16)); 571 .modify(|w| w.set_brgval((brg_value - 1) as u16));
554 } 572 }
555 573
556 fn pin_config<T: Instance>(tx: Option<Peri<'_, AnyPin>>, rx: Option<Peri<'_, AnyPin>>) { 574 fn pin_config<T: Instance>(tx: Option<(Peri<'_, AnyPin>, PioFunc)>, rx: Option<(Peri<'_, AnyPin>, PioFunc)>) {
557 if let Some(tx_pin) = tx { 575 if let Some((tx_pin, func)) = tx {
558 tx_pin.pio().modify(|w| { 576 tx_pin.pio().modify(|w| {
559 w.set_func(T::tx_pin_func()); 577 w.set_func(func);
560 w.set_mode(iocon::vals::PioMode::INACTIVE); 578 w.set_mode(iocon::vals::PioMode::INACTIVE);
561 w.set_slew(iocon::vals::PioSlew::STANDARD); 579 w.set_slew(iocon::vals::PioSlew::STANDARD);
562 w.set_invert(false); 580 w.set_invert(false);
@@ -565,9 +583,9 @@ impl<'d, M: Mode> Usart<'d, M> {
565 }); 583 });
566 } 584 }
567 585
568 if let Some(rx_pin) = rx { 586 if let Some((rx_pin, func)) = rx {
569 rx_pin.pio().modify(|w| { 587 rx_pin.pio().modify(|w| {
570 w.set_func(T::rx_pin_func()); 588 w.set_func(func);
571 w.set_mode(iocon::vals::PioMode::INACTIVE); 589 w.set_mode(iocon::vals::PioMode::INACTIVE);
572 w.set_slew(iocon::vals::PioSlew::STANDARD); 590 w.set_slew(iocon::vals::PioSlew::STANDARD);
573 w.set_invert(false); 591 w.set_invert(false);
@@ -810,8 +828,6 @@ trait SealedInstance {
810 fn info() -> &'static Info; 828 fn info() -> &'static Info;
811 fn dma_state() -> &'static DmaState; 829 fn dma_state() -> &'static DmaState;
812 fn instance_number() -> usize; 830 fn instance_number() -> usize;
813 fn tx_pin_func() -> PioFunc;
814 fn rx_pin_func() -> PioFunc;
815} 831}
816 832
817/// UART instance. 833/// UART instance.
@@ -822,7 +838,7 @@ pub trait Instance: SealedInstance + PeripheralType {
822} 838}
823 839
824macro_rules! impl_instance { 840macro_rules! impl_instance {
825 ($inst:ident, $fc:ident, $tx_pin:ident, $rx_pin:ident, $fc_num:expr) => { 841 ($inst:ident, $fc:ident, $fc_num:expr) => {
826 impl $crate::usart::inner::SealedInstance for $crate::peripherals::$inst { 842 impl $crate::usart::inner::SealedInstance for $crate::peripherals::$inst {
827 fn info() -> &'static Info { 843 fn info() -> &'static Info {
828 static INFO: Info = Info { 844 static INFO: Info = Info {
@@ -844,14 +860,6 @@ macro_rules! impl_instance {
844 fn instance_number() -> usize { 860 fn instance_number() -> usize {
845 $fc_num 861 $fc_num
846 } 862 }
847 #[inline]
848 fn tx_pin_func() -> PioFunc {
849 PioFunc::$tx_pin
850 }
851 #[inline]
852 fn rx_pin_func() -> PioFunc {
853 PioFunc::$rx_pin
854 }
855 } 863 }
856 impl $crate::usart::Instance for $crate::peripherals::$inst { 864 impl $crate::usart::Instance for $crate::peripherals::$inst {
857 type Interrupt = crate::interrupt::typelevel::$fc; 865 type Interrupt = crate::interrupt::typelevel::$fc;
@@ -859,45 +867,72 @@ macro_rules! impl_instance {
859 }; 867 };
860} 868}
861 869
862impl_instance!(USART0, FLEXCOMM0, ALT1, ALT1, 0); 870impl_instance!(USART0, FLEXCOMM0, 0);
863impl_instance!(USART1, FLEXCOMM1, ALT2, ALT2, 1); 871impl_instance!(USART1, FLEXCOMM1, 1);
864impl_instance!(USART2, FLEXCOMM2, ALT1, ALT1, 2); 872impl_instance!(USART2, FLEXCOMM2, 2);
865impl_instance!(USART3, FLEXCOMM3, ALT1, ALT1, 3); 873impl_instance!(USART3, FLEXCOMM3, 3);
866impl_instance!(USART4, FLEXCOMM4, ALT1, ALT2, 4); 874impl_instance!(USART4, FLEXCOMM4, 4);
867impl_instance!(USART5, FLEXCOMM5, ALT3, ALT3, 5); 875impl_instance!(USART5, FLEXCOMM5, 5);
868impl_instance!(USART6, FLEXCOMM6, ALT2, ALT2, 6); 876impl_instance!(USART6, FLEXCOMM6, 6);
869impl_instance!(USART7, FLEXCOMM7, ALT7, ALT7, 7); 877impl_instance!(USART7, FLEXCOMM7, 7);
878
879pub(crate) trait SealedTxPin<T: Instance>: crate::gpio::Pin {
880 fn pin_func(&self) -> PioFunc;
881}
882
883pub(crate) trait SealedRxPin<T: Instance>: crate::gpio::Pin {
884 fn pin_func(&self) -> PioFunc;
885}
870 886
871/// Trait for TX pins. 887/// Trait for TX pins.
872pub trait TxPin<T: Instance>: crate::gpio::Pin {} 888#[allow(private_bounds)]
889pub trait TxPin<T: Instance>: SealedTxPin<T> + crate::gpio::Pin {}
890
873/// Trait for RX pins. 891/// Trait for RX pins.
874pub trait RxPin<T: Instance>: crate::gpio::Pin {} 892#[allow(private_bounds)]
893pub trait RxPin<T: Instance>: SealedRxPin<T> + crate::gpio::Pin {}
894
895macro_rules! impl_tx_pin {
896 ($pin:ident, $instance:ident, $func: ident) => {
897 impl SealedTxPin<crate::peripherals::$instance> for crate::peripherals::$pin {
898 fn pin_func(&self) -> PioFunc {
899 PioFunc::$func
900 }
901 }
875 902
876macro_rules! impl_pin {
877 ($pin:ident, $instance:ident, Tx) => {
878 impl TxPin<crate::peripherals::$instance> for crate::peripherals::$pin {} 903 impl TxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
879 }; 904 };
880 ($pin:ident, $instance:ident, Rx) => { 905}
906
907macro_rules! impl_rx_pin {
908 ($pin:ident, $instance:ident, $func: ident) => {
909 impl SealedRxPin<crate::peripherals::$instance> for crate::peripherals::$pin {
910 fn pin_func(&self) -> PioFunc {
911 PioFunc::$func
912 }
913 }
914
881 impl RxPin<crate::peripherals::$instance> for crate::peripherals::$pin {} 915 impl RxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
882 }; 916 };
883} 917}
884 918
885impl_pin!(PIO1_6, USART0, Tx); 919impl_tx_pin!(PIO1_6, USART0, ALT1);
886impl_pin!(PIO1_5, USART0, Rx); 920impl_tx_pin!(PIO1_11, USART1, ALT2);
887impl_pin!(PIO1_11, USART1, Tx); 921impl_tx_pin!(PIO0_27, USART2, ALT1);
888impl_pin!(PIO1_10, USART1, Rx); 922impl_tx_pin!(PIO0_2, USART3, ALT1);
889impl_pin!(PIO0_27, USART2, Tx); 923impl_tx_pin!(PIO0_16, USART4, ALT1);
890impl_pin!(PIO1_24, USART2, Rx); 924impl_tx_pin!(PIO0_9, USART5, ALT3);
891impl_pin!(PIO0_2, USART3, Tx); 925impl_tx_pin!(PIO1_16, USART6, ALT2);
892impl_pin!(PIO0_3, USART3, Rx); 926impl_tx_pin!(PIO0_19, USART7, ALT7);
893impl_pin!(PIO0_16, USART4, Tx); 927
894impl_pin!(PIO0_5, USART4, Rx); 928impl_rx_pin!(PIO1_5, USART0, ALT1);
895impl_pin!(PIO0_9, USART5, Tx); 929impl_rx_pin!(PIO1_10, USART1, ALT2);
896impl_pin!(PIO0_8, USART5, Rx); 930impl_rx_pin!(PIO1_24, USART2, ALT1);
897impl_pin!(PIO1_16, USART6, Tx); 931impl_rx_pin!(PIO0_3, USART3, ALT1);
898impl_pin!(PIO1_13, USART6, Rx); 932impl_rx_pin!(PIO0_5, USART4, ALT2);
899impl_pin!(PIO0_19, USART7, Tx); 933impl_rx_pin!(PIO0_8, USART5, ALT3);
900impl_pin!(PIO0_20, USART7, Rx); 934impl_rx_pin!(PIO1_13, USART6, ALT2);
935impl_rx_pin!(PIO0_20, USART7, ALT7);
901 936
902/// Trait for TX DMA channels. 937/// Trait for TX DMA channels.
903pub trait TxChannel<T: Instance>: crate::dma::Channel {} 938pub trait TxChannel<T: Instance>: crate::dma::Channel {}