Merge branch 'embassy-rs:main' into stm32_adc_v3_hw_oversampling_support

321 files changed, 10994 insertions, 2220 deletions

diff --git a/.github/ci/book.sh b/.github/ci/book.sh
index 285cdc8fa..2466f53f5 100755
--- a/.github/ci/book.sh
+++ b/.github/ci/book.sh
@@ -1,5 +1,7 @@
 #!/bin/bash
 ## on push branch=main
+## priority -9
+## dedup dequeue
 
 set -euxo pipefail
 
diff --git a/.github/ci/doc.sh b/.github/ci/doc.sh
index 58ffe5f2e..9162b37ae 100755
--- a/.github/ci/doc.sh
+++ b/.github/ci/doc.sh
@@ -1,5 +1,7 @@
 #!/bin/bash
 ## on push branch=main
+## priority -10
+## dedup dequeue
 
 set -euxo pipefail
 
@@ -26,6 +28,7 @@ docserver-builder -i ./embassy-futures -o webroot/crates/embassy-futures/git.zup
 docserver-builder -i ./embassy-nrf -o webroot/crates/embassy-nrf/git.zup
 docserver-builder -i ./embassy-rp -o webroot/crates/embassy-rp/git.zup
 docserver-builder -i ./embassy-mspm0 -o webroot/crates/embassy-mspm0/git.zup
+docserver-builder -i ./embassy-nxp -o webroot/crates/embassy-nxp/git.zup
 docserver-builder -i ./embassy-sync -o webroot/crates/embassy-sync/git.zup
 docserver-builder -i ./cyw43 -o webroot/crates/cyw43/git.zup
 docserver-builder -i ./cyw43-pio -o webroot/crates/cyw43-pio/git.zup
@@ -42,6 +45,7 @@ docserver-builder -i ./embassy-usb-logger -o webroot/crates/embassy-usb-logger/g
 docserver-builder -i ./embassy-usb-synopsys-otg -o webroot/crates/embassy-usb-synopsys-otg/git.zup
 
 docserver-builder -i ./embassy-net -o webroot/crates/embassy-net/git.zup
+docserver-builder -i ./embassy-net-nrf91 -o webroot/crates/embassy-net-nrf91/git.zup
 docserver-builder -i ./embassy-net-driver -o webroot/crates/embassy-net-driver/git.zup
 docserver-builder -i ./embassy-net-driver-channel -o webroot/crates/embassy-net-driver-channel/git.zup
 docserver-builder -i ./embassy-net-wiznet -o webroot/crates/embassy-net-wiznet/git.zup
diff --git a/.vscode/settings.json b/.vscode/settings.json
index e4814ff27..6edd9312a 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -36,6 +36,8 @@
     // "examples/nrf52840-rtic/Cargo.toml",
     // "examples/nrf5340/Cargo.toml",
     // "examples/nrf-rtos-trace/Cargo.toml",
+    // "examples/mimxrt1011/Cargo.toml",
+    // "examples/mimxrt1062-evk/Cargo.toml",
     // "examples/rp/Cargo.toml",
     // "examples/std/Cargo.toml",
     // "examples/stm32c0/Cargo.toml",
diff --git a/RELEASE.md b/RELEASE.md
new file mode 100644
index 000000000..0ebcfd9fa
--- /dev/null
+++ b/RELEASE.md
@@ -0,0 +1,58 @@
+# RELEASE.md
+
+This document outlines the process for releasing Embassy crates using `cargo-release` and the `release/bump-dependency.sh` script.
+
+When releasing a crate, keep in mind that you may need to recursively release dependencies as well. 
+
+## Prerequisites
+
+- Install [`cargo-release`](https://github.com/crate-ci/cargo-release):
+
+  ```sh
+  cargo binstall cargo-release
+
+## Crate release
+
+Check if there are changes to the public API since the last release. If there is a breaking change, follow
+the process for creating a minor release. Otherewise, follow the process for creating a new patch release.
+
+Keep in mind that some crates may need the --features and --target flags passed to cargo release. For more information on that,
+look at the `Cargo.toml` files.
+
+### Patch release (no breaking public API changes)
+
+```
+cd embassy-nrf/
+cargo release patch --features time,defmt,unstable-pac,gpiote,time-driver-rtc1,nrf52840 --target thumbv7em-none-eabi
+
+# If dry-run is OK (no missing dependencies on crates.io) 
+cargo release patch --execute --features time,defmt,unstable-pac,gpiote,time-driver-rtc1,nrf52840 --target thumbv7em-none-eabi
+```
+
+### Minor release
+
+```
+# Bump versions in crate files
+./release/bump-dependency.sh embassy-nrf 0.4.0
+
+# Commit version bump
+git commit -am 'chore: update to `embassy-nrf` v0.4.0'
+
+# Release crate
+cd embassy-nrf/
+cargo release minor --features time,defmt,unstable-pac,gpiote,time-driver-rtc1,nrf52840 --target thumbv7em-none-eabi
+
+# If dry-run is OK (no missing dependencies on crates.io) 
+cargo release minor --execute --features time,defmt,unstable-pac,gpiote,time-driver-rtc1,nrf52840 --target thumbv7em-none-eabi
+```
+
+## Push tags
+
+Push the git tags that `cargo release` created earlier:
+
+```
+git push --tags
+```
+## Reference
+
+* [PR introducing release automation](https://github.com/embassy-rs/embassy/pull/4289)
diff --git a/ci.sh b/ci.sh
index e1fdf998a..f4db1da03 100755
--- a/ci.sh
+++ b/ci.sh
@@ -40,6 +40,8 @@ cargo batch \
     --- build --release --manifest-path embassy-executor/Cargo.toml --target armv7r-none-eabihf --features arch-cortex-ar,executor-thread \
     --- build --release --manifest-path embassy-executor/Cargo.toml --target riscv32imac-unknown-none-elf --features arch-riscv32 \
     --- build --release --manifest-path embassy-executor/Cargo.toml --target riscv32imac-unknown-none-elf --features arch-riscv32,executor-thread \
+    --- build --release --manifest-path embassy-embedded-hal/Cargo.toml --target thumbv7em-none-eabi \
+    --- build --release --manifest-path embassy-embedded-hal/Cargo.toml --target thumbv7em-none-eabi --features time \
     --- build --release --manifest-path embassy-sync/Cargo.toml --target thumbv6m-none-eabi --features defmt \
     --- build --release --manifest-path embassy-time/Cargo.toml --target thumbv6m-none-eabi --features defmt,defmt-timestamp-uptime,mock-driver \
     --- build --release --manifest-path embassy-time-queue-utils/Cargo.toml --target thumbv6m-none-eabi \
@@ -102,6 +104,8 @@ cargo batch \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,exti \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,single-bank,defmt \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c071rb,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c051f6,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f038f6,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f030c6,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f058t8,defmt,exti,time-driver-any,time \
@@ -155,11 +159,13 @@ cargo batch \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f303c8,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f398ve,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f378cc,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g0b0ce,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g0c1ve,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f217zg,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,dual-bank,defmt,exti,time-driver-any,low-power,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32wl54jc-cm0p,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wle5jb,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g431kb,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g474pe,dual-bank,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f107vc,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f103re,defmt,exti,time-driver-any,time \
@@ -169,6 +175,8 @@ cargo batch \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h562ag,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32wba50ke,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32wba55ug,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32wba62cg,defmt,exti,time-driver-any,time \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32wba65ri,defmt,exti,time-driver-any,low-power,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32u5f9zj,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32u5g9nj,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb35ce,defmt,exti,time-driver-any,time \
@@ -176,7 +184,9 @@ cargo batch \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32u031r8,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32u073mb,defmt,exti,time-driver-any,time \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32u083rc,defmt,exti,time-driver-any,time \
-    --- build --release --manifest-path embassy-nxp/Cargo.toml --target thumbv8m.main-none-eabihf \
+    --- build --release --manifest-path embassy-nxp/Cargo.toml --target thumbv8m.main-none-eabihf --features lpc55,defmt \
+    --- build --release --manifest-path embassy-nxp/Cargo.toml --target thumbv7em-none-eabihf --features mimxrt1011,rt,defmt,time-driver-pit \
+    --- build --release --manifest-path embassy-nxp/Cargo.toml --target thumbv7em-none-eabihf --features mimxrt1062,rt,defmt,time-driver-pit \
     --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0c1104dgs20,defmt,time-driver-any \
     --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0g3507pm,defmt,time-driver-any \
     --- build --release --manifest-path embassy-mspm0/Cargo.toml --target thumbv6m-none-eabi --features mspm0g3519pz,defmt,time-driver-any \
@@ -244,6 +254,7 @@ cargo batch \
     --- build --release --manifest-path examples/stm32h5/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/stm32h5 \
     --- build --release --manifest-path examples/stm32h7/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h7 \
     --- build --release --manifest-path examples/stm32h7b0/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h7b0 \
+    --- build --release --manifest-path examples/stm32h723/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h723 \
     --- build --release --manifest-path examples/stm32h735/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h735 \
     --- build --release --manifest-path examples/stm32h755cm4/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h755cm4 \
     --- build --release --manifest-path examples/stm32h755cm7/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32h755cm7 \
@@ -259,6 +270,8 @@ cargo batch \
     --- build --release --manifest-path examples/stm32wba/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/stm32wba \
     --- build --release --manifest-path examples/stm32wl/Cargo.toml --target thumbv7em-none-eabi --artifact-dir out/examples/stm32wl \
     --- build --release --manifest-path examples/lpc55s69/Cargo.toml --target thumbv8m.main-none-eabihf --artifact-dir out/examples/lpc55s69 \
+    --- build --release --manifest-path examples/mimxrt1011/Cargo.toml --target thumbv7em-none-eabihf --artifact-dir out/examples/mimxrt1011 \
+    --- build --release --manifest-path examples/mimxrt1062-evk/Cargo.toml --target thumbv7em-none-eabihf --artifact-dir out/examples/mimxrt1062-evk \
     --- build --release --manifest-path examples/mspm0g3507/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/mspm0g3507 \
     --- build --release --manifest-path examples/mspm0g3519/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/mspm0g3519 \
     --- build --release --manifest-path examples/mspm0l1306/Cargo.toml --target thumbv6m-none-eabi --artifact-dir out/examples/mspm0l1306 \
@@ -294,6 +307,7 @@ cargo batch \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g491re --artifact-dir out/tests/stm32g491re \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g071rb --artifact-dir out/tests/stm32g071rb \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c031c6 --artifact-dir out/tests/stm32c031c6 \
+    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c071rb --artifact-dir out/tests/stm32c071rb \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi --artifact-dir out/tests/stm32h755zi \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h753zi --artifact-dir out/tests/stm32h753zi \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7a3zi --artifact-dir out/tests/stm32h7a3zi \
@@ -369,8 +383,12 @@ rm out/tests/pimoroni-pico-plus-2/adc
 # temporarily disabled
 rm out/tests/pimoroni-pico-plus-2/pwm
 
-# temporarily disabled, bad hardware connection.
-rm -f out/tests/rpi-pico/*
+# flaky
+rm out/tests/rpi-pico/pwm
+rm out/tests/rpi-pico/cyw43-perf
+
+# tests are implemented but the HIL test farm doesn't actually have this board yet
+rm -rf out/tests/stm32c071rb
 
 if [[ -z "${TELEPROBE_TOKEN-}" ]]; then
     echo No teleprobe token found, skipping running HIL tests
diff --git a/cyw43-pio/CHANGELOG.md b/cyw43-pio/CHANGELOG.md
index 4d56973df..218271e15 100644
--- a/cyw43-pio/CHANGELOG.md
+++ b/cyw43-pio/CHANGELOG.md
@@ -5,9 +5,14 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## Unreleased
+<!-- next-header -->
+## Unreleased - ReleaseDate
 
-- Update embassy-rp to 0.4.0
+## 0.5.1 - 2025-07-16
+
+## 0.5.0 - 2025-07-15
+
+- Update embassy-rp to 0.5.0
 
 ## 0.3.0 - 2025-01-05
 
diff --git a/cyw43-pio/Cargo.toml b/cyw43-pio/Cargo.toml
index 93a2e7089..d60793bdc 100644
--- a/cyw43-pio/Cargo.toml
+++ b/cyw43-pio/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "cyw43-pio"
-version = "0.4.0"
+version = "0.5.1"
 edition = "2021"
 description = "RP2040 PIO SPI implementation for cyw43"
 keywords = ["embedded", "cyw43", "embassy-net", "embedded-hal-async", "wifi"]
@@ -10,8 +10,8 @@ repository = "https://github.com/embassy-rs/embassy"
 documentation = "https://docs.embassy.dev/cyw43-pio"
 
 [dependencies]
-cyw43 = { version = "0.3.0", path = "../cyw43" }
-embassy-rp = { version = "0.4.0", path = "../embassy-rp" }
+cyw43 = { version = "0.4.0", path = "../cyw43" }
+embassy-rp = { version = "0.6.0", path = "../embassy-rp" }
 fixed = "1.23.1"
 defmt = { version = "1.0.1", optional = true }
 
diff --git a/cyw43-pio/release.toml b/cyw43-pio/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/cyw43-pio/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/cyw43/CHANGELOG.md b/cyw43/CHANGELOG.md
index 40a638388..c800e785b 100644
--- a/cyw43/CHANGELOG.md
+++ b/cyw43/CHANGELOG.md
@@ -5,7 +5,14 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## Unreleased
+<!-- next-header -->
+## Unreleased - ReleaseDate
+
+## 0.4.0 - 2025-07-15
+
+- bump embassy-sync to 0.7.0
+- bump bt-hci to 0.3.0
+- make State::new const fn
 
 ## 0.3.0 - 2025-01-05
 
diff --git a/cyw43/Cargo.toml b/cyw43/Cargo.toml
index c52a653bd..8aef8963c 100644
--- a/cyw43/Cargo.toml
+++ b/cyw43/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "cyw43"
-version = "0.3.0"
+version = "0.4.0"
 edition = "2021"
 description = "Rust driver for the CYW43439 WiFi chip, used in the Raspberry Pi Pico W."
 keywords = ["embedded", "cyw43", "embassy-net", "embedded-hal-async", "wifi"]
@@ -21,7 +21,7 @@ firmware-logs = []
 embassy-time = { version = "0.4.0", path = "../embassy-time"}
 embassy-sync = { version = "0.7.0", path = "../embassy-sync"}
 embassy-futures = { version = "0.1.0", path = "../embassy-futures"}
-embassy-net-driver-channel = { version = "0.3.0", path = "../embassy-net-driver-channel"}
+embassy-net-driver-channel = { version = "0.3.1", path = "../embassy-net-driver-channel"}
 
 defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.17", optional = true }
diff --git a/cyw43/release.toml b/cyw43/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/cyw43/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/docs/examples/basic/Cargo.toml b/docs/examples/basic/Cargo.toml
index f5cf2b231..c4b72d81a 100644
--- a/docs/examples/basic/Cargo.toml
+++ b/docs/examples/basic/Cargo.toml
@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 [dependencies]
 embassy-executor = { version = "0.7.0", path = "../../../embassy-executor", features = ["defmt", "arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.4.0", path = "../../../embassy-time", features = ["defmt"] }
-embassy-nrf = { version = "0.3.1", path = "../../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote"] }
+embassy-nrf = { version = "0.5.0", path = "../../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/docs/index.adoc b/docs/index.adoc
index 9c6150196..80754d5a4 100644
--- a/docs/index.adoc
+++ b/docs/index.adoc
@@ -5,6 +5,7 @@
 :toc-placement: left
 :toclevels: 2
 :imagesdir: images
+:source-highlighter: rouge
 
 # Embassy Book
 
diff --git a/docs/pages/layer_by_layer.adoc b/docs/pages/layer_by_layer.adoc
index 7dba11b5e..0692ee4fa 100644
--- a/docs/pages/layer_by_layer.adoc
+++ b/docs/pages/layer_by_layer.adoc
@@ -8,7 +8,7 @@ The application we'll write is a simple 'push button, blink led' application, wh
 
 == PAC version
 
-The PAC is the lowest API for accessing peripherals and registers, if you don't count reading/writing directly to memory addresses. It provides distinct types to make accessing peripheral registers easier, but it does not prevent you from writing unsafe code.
+The PAC is the lowest API for accessing peripherals and registers, if you don't count reading/writing directly to memory addresses. It provides distinct types to make accessing peripheral registers easier, but it does little to prevent you from configuring or coordinating those registers incorrectly.
 
 Writing an application using the PAC directly is therefore not recommended, but if the functionality you want to use is not exposed in the upper layers, that's what you need to use.
 
diff --git a/docs/pages/new_project.adoc b/docs/pages/new_project.adoc
index cd943b4f6..906d89f36 100644
--- a/docs/pages/new_project.adoc
+++ b/docs/pages/new_project.adoc
@@ -11,6 +11,8 @@ Once you’ve successfully xref:#_getting_started[run some example projects], th
 - link:https://github.com/lulf/embassy-template[embassy-template] (STM32, NRF, and RP)
 - link:https://github.com/bentwire/embassy-rp2040-template[embassy-rp2040-template] (RP)
 
+=== esp-generate
+- link:https://github.com/esp-rs/esp-generate[esp-generate] (ESP32 using esp-hal)
 
 == Starting a project from scratch
 
diff --git a/docs/pages/overview.adoc b/docs/pages/overview.adoc
index acd757795..18eaaeb75 100644
--- a/docs/pages/overview.adoc
+++ b/docs/pages/overview.adoc
@@ -30,7 +30,7 @@ The Embassy project maintains HALs for select hardware, but you can still use HA
 * link:https://docs.embassy.dev/embassy-nrf/[embassy-nrf], for the Nordic Semiconductor nRF52, nRF53, nRF91 series.
 * link:https://docs.embassy.dev/embassy-rp/[embassy-rp], for the Raspberry Pi RP2040 as well as RP235x microcontroller.
 * link:https://docs.embassy.dev/embassy-mspm0/[embassy-mspm0], for the Texas Instruments MSPM0 microcontrollers.
-* link:https://github.com/esp-rs[esp-rs], for the Espressif Systems ESP32 series of chips.
+* link:https://github.com/esp-rs/esp-hal[esp-hal], for the Espressif Systems ESP32 series of chips.
 * link:https://github.com/ch32-rs/ch32-hal[ch32-hal], for the WCH 32-bit RISC-V(CH32V) series of chips.
 * link:https://github.com/AlexCharlton/mpfs-hal[mpfs-hal], for the Microchip PolarFire SoC.
 * link:https://github.com/py32-rs/py32-hal[py32-hal], for the Puya Semiconductor PY32 series of chips.
diff --git a/embassy-boot-nrf/Cargo.toml b/embassy-boot-nrf/Cargo.toml
index 3cfaa5a80..81479759c 100644
--- a/embassy-boot-nrf/Cargo.toml
+++ b/embassy-boot-nrf/Cargo.toml
@@ -1,7 +1,7 @@
 [package]
 edition = "2021"
 name = "embassy-boot-nrf"
-version = "0.4.0"
+version = "0.6.0"
 description = "Bootloader lib for nRF chips"
 license = "MIT OR Apache-2.0"
 repository = "https://github.com/embassy-rs/embassy"
@@ -25,8 +25,8 @@ defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.17", optional = true }
 
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
-embassy-nrf = { version = "0.3.1", path = "../embassy-nrf", default-features = false }
-embassy-boot = { version = "0.4.0", path = "../embassy-boot" }
+embassy-nrf = { version = "0.5.0", path = "../embassy-nrf", default-features = false }
+embassy-boot = { version = "0.5.0", path = "../embassy-boot" }
 cortex-m = { version = "0.7.6" }
 cortex-m-rt = { version = "0.7" }
 embedded-storage = "0.3.1"
diff --git a/embassy-boot-rp/Cargo.toml b/embassy-boot-rp/Cargo.toml
index afe5d6691..8ca999f67 100644
--- a/embassy-boot-rp/Cargo.toml
+++ b/embassy-boot-rp/Cargo.toml
@@ -1,7 +1,7 @@
 [package]
 edition = "2021"
 name = "embassy-boot-rp"
-version = "0.5.0"
+version = "0.6.0"
 description = "Bootloader lib for RP2040 chips"
 license = "MIT OR Apache-2.0"
 repository = "https://github.com/embassy-rs/embassy"
@@ -25,8 +25,8 @@ defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4", optional = true }
 
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
-embassy-rp = { version = "0.4.0", path = "../embassy-rp", default-features = false }
-embassy-boot = { version = "0.4.0", path = "../embassy-boot" }
+embassy-rp = { version = "0.6.0", path = "../embassy-rp", default-features = false }
+embassy-boot = { version = "0.5.0", path = "../embassy-boot" }
 embassy-time = { version = "0.4.0", path = "../embassy-time" }
 
 cortex-m = { version = "0.7.6" }
diff --git a/embassy-boot-stm32/Cargo.toml b/embassy-boot-stm32/Cargo.toml
index 11ad453b8..b92d06c54 100644
--- a/embassy-boot-stm32/Cargo.toml
+++ b/embassy-boot-stm32/Cargo.toml
@@ -1,7 +1,7 @@
 [package]
 edition = "2021"
 name = "embassy-boot-stm32"
-version = "0.3.0"
+version = "0.4.0"
 description = "Bootloader lib for STM32 chips"
 license = "MIT OR Apache-2.0"
 repository = "https://github.com/embassy-rs/embassy"
@@ -26,7 +26,7 @@ log = { version = "0.4", optional = true }
 
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
 embassy-stm32 = { version = "0.2.0", path = "../embassy-stm32", default-features = false }
-embassy-boot = { version = "0.4.0", path = "../embassy-boot" }
+embassy-boot = { version = "0.5.0", path = "../embassy-boot" }
 cortex-m = { version = "0.7.6" }
 cortex-m-rt = { version = "0.7" }
 embedded-storage = "0.3.1"
diff --git a/embassy-boot/Cargo.toml b/embassy-boot/Cargo.toml
index f12e8e304..172330ef2 100644
--- a/embassy-boot/Cargo.toml
+++ b/embassy-boot/Cargo.toml
@@ -1,7 +1,7 @@
 [package]
 edition = "2021"
 name = "embassy-boot"
-version = "0.4.0"
+version = "0.5.0"
 description = "A lightweight bootloader supporting firmware updates in a power-fail-safe way, with trial boots and rollbacks."
 license = "MIT OR Apache-2.0"
 repository = "https://github.com/embassy-rs/embassy"
@@ -28,7 +28,7 @@ defmt = { version = "1.0.1", optional = true }
 digest = "0.10"
 log = { version = "0.4", optional = true }
 ed25519-dalek = { version = "2", default-features = false, features = ["digest"], optional = true }
-embassy-embedded-hal = { version = "0.3.0", path = "../embassy-embedded-hal" }
+embassy-embedded-hal = { version = "0.3.1", path = "../embassy-embedded-hal" }
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
 embedded-storage = "0.3.1"
 embedded-storage-async = { version = "0.4.1" }
diff --git a/embassy-embedded-hal/CHANGELOG.md b/embassy-embedded-hal/CHANGELOG.md
index 224036af4..04d95415c 100644
--- a/embassy-embedded-hal/CHANGELOG.md
+++ b/embassy-embedded-hal/CHANGELOG.md
@@ -5,7 +5,13 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## Unreleased
+<!-- next-header -->
+## Unreleased - ReleaseDate
+
+## 0.3.1 - 2025-07-16
+
+- `SpiDevice` cancel safety: always set CS pin to high on drop
+- Update `embassy-sync` to v0.7.0
 
 ## 0.3.0 - 2025-01-05
 
diff --git a/embassy-embedded-hal/Cargo.toml b/embassy-embedded-hal/Cargo.toml
index efc3173d4..8277aa291 100644
--- a/embassy-embedded-hal/Cargo.toml
+++ b/embassy-embedded-hal/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-embedded-hal"
-version = "0.3.0"
+version = "0.3.1"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "Collection of utilities to use `embedded-hal` and `embedded-storage` traits with Embassy."
@@ -19,10 +19,9 @@ target = "x86_64-unknown-linux-gnu"
 
 [features]
 time = ["dep:embassy-time"]
-default = ["time"]
 
 [dependencies]
-embassy-hal-internal = { version = "0.2.0", path = "../embassy-hal-internal" }
+embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal" }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
 embassy-time = { version = "0.4.0", path = "../embassy-time", optional = true }
diff --git a/embassy-embedded-hal/release.toml b/embassy-embedded-hal/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/embassy-embedded-hal/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/embassy-embedded-hal/src/adapter/blocking_async.rs b/embassy-embedded-hal/src/adapter/blocking_async.rs
index bafc31583..3b6e0ec00 100644
--- a/embassy-embedded-hal/src/adapter/blocking_async.rs
+++ b/embassy-embedded-hal/src/adapter/blocking_async.rs
@@ -1,5 +1,3 @@
-use embedded_hal_02::blocking;
-
 /// Wrapper that implements async traits using blocking implementations.
 ///
 /// This allows driver writers to depend on the async traits while still supporting embedded-hal peripheral implementations.
@@ -24,7 +22,7 @@ impl<T> BlockingAsync<T> {
 impl<T, E> embedded_hal_1::i2c::ErrorType for BlockingAsync<T>
 where
     E: embedded_hal_1::i2c::Error + 'static,
-    T: blocking::i2c::WriteRead<Error = E> + blocking::i2c::Read<Error = E> + blocking::i2c::Write<Error = E>,
+    T: embedded_hal_1::i2c::I2c<Error = E>,
 {
     type Error = E;
 }
@@ -32,7 +30,7 @@ where
 impl<T, E> embedded_hal_async::i2c::I2c for BlockingAsync<T>
 where
     E: embedded_hal_1::i2c::Error + 'static,
-    T: blocking::i2c::WriteRead<Error = E> + blocking::i2c::Read<Error = E> + blocking::i2c::Write<Error = E>,
+    T: embedded_hal_1::i2c::I2c<Error = E>,
 {
     async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
         self.wrapped.read(address, read)
@@ -51,9 +49,7 @@ where
         address: u8,
         operations: &mut [embedded_hal_1::i2c::Operation<'_>],
     ) -> Result<(), Self::Error> {
-        let _ = address;
-        let _ = operations;
-        todo!()
+        self.wrapped.transaction(address, operations)
     }
 }
 
@@ -63,16 +59,16 @@ where
 
 impl<T, E> embedded_hal_async::spi::ErrorType for BlockingAsync<T>
 where
-    E: embedded_hal_1::spi::Error,
-    T: blocking::spi::Transfer<u8, Error = E> + blocking::spi::Write<u8, Error = E>,
+    E: embedded_hal_async::spi::Error,
+    T: embedded_hal_1::spi::SpiBus<Error = E>,
 {
     type Error = E;
 }
 
 impl<T, E> embedded_hal_async::spi::SpiBus<u8> for BlockingAsync<T>
 where
-    E: embedded_hal_1::spi::Error + 'static,
-    T: blocking::spi::Transfer<u8, Error = E> + blocking::spi::Write<u8, Error = E>,
+    E: embedded_hal_async::spi::Error,
+    T: embedded_hal_1::spi::SpiBus<Error = E>,
 {
     async fn flush(&mut self) -> Result<(), Self::Error> {
         Ok(())
@@ -84,21 +80,17 @@ where
     }
 
     async fn read(&mut self, data: &mut [u8]) -> Result<(), Self::Error> {
-        self.wrapped.transfer(data)?;
+        self.wrapped.read(data)?;
         Ok(())
     }
 
     async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
-        // Ensure we write the expected bytes
-        for i in 0..core::cmp::min(read.len(), write.len()) {
-            read[i] = write[i].clone();
-        }
-        self.wrapped.transfer(read)?;
+        self.wrapped.transfer(read, write)?;
         Ok(())
     }
 
     async fn transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Self::Error> {
-        self.wrapped.transfer(data)?;
+        self.wrapped.transfer_in_place(data)?;
         Ok(())
     }
 }
diff --git a/embassy-executor-macros/src/macros/task.rs b/embassy-executor-macros/src/macros/task.rs
index 91d6beee8..1c5e3571d 100644
--- a/embassy-executor-macros/src/macros/task.rs
+++ b/embassy-executor-macros/src/macros/task.rs
@@ -51,7 +51,11 @@ pub fn run(args: TokenStream, item: TokenStream) -> TokenStream {
         .embassy_executor
         .unwrap_or(Expr::Verbatim(TokenStream::from_str("::embassy_executor").unwrap()));
 
-    if f.sig.asyncness.is_none() {
+    let returns_impl_trait = match &f.sig.output {
+        ReturnType::Type(_, ty) => matches!(**ty, Type::ImplTrait(_)),
+        _ => false,
+    };
+    if f.sig.asyncness.is_none() && !returns_impl_trait {
         error(&mut errors, &f.sig, "task functions must be async");
     }
     if !f.sig.generics.params.is_empty() {
@@ -66,17 +70,19 @@ pub fn run(args: TokenStream, item: TokenStream) -> TokenStream {
     if !f.sig.variadic.is_none() {
         error(&mut errors, &f.sig, "task functions must not be variadic");
     }
-    match &f.sig.output {
-        ReturnType::Default => {}
-        ReturnType::Type(_, ty) => match &**ty {
-            Type::Tuple(tuple) if tuple.elems.is_empty() => {}
-            Type::Never(_) => {}
-            _ => error(
-                &mut errors,
-                &f.sig,
-                "task functions must either not return a value, return `()` or return `!`",
-            ),
-        },
+    if f.sig.asyncness.is_some() {
+        match &f.sig.output {
+            ReturnType::Default => {}
+            ReturnType::Type(_, ty) => match &**ty {
+                Type::Tuple(tuple) if tuple.elems.is_empty() => {}
+                Type::Never(_) => {}
+                _ => error(
+                    &mut errors,
+                    &f.sig,
+                    "task functions must either not return a value, return `()` or return `!`",
+                ),
+            },
+        }
     }
 
     let mut args = Vec::new();
@@ -125,15 +131,21 @@ pub fn run(args: TokenStream, item: TokenStream) -> TokenStream {
         ));
     }
 
+    let spawn = if returns_impl_trait {
+        quote!(spawn)
+    } else {
+        quote!(_spawn_async_fn)
+    };
+
     #[cfg(feature = "nightly")]
     let mut task_outer_body = quote! {
         trait _EmbassyInternalTaskTrait {
-            type Fut: ::core::future::Future + 'static;
+            type Fut: ::core::future::Future<Output: #embassy_executor::_export::TaskReturnValue> + 'static;
             fn construct(#fargs) -> Self::Fut;
         }
 
         impl _EmbassyInternalTaskTrait for () {
-            type Fut = impl core::future::Future + 'static;
+            type Fut = impl core::future::Future<Output: #embassy_executor::_export::TaskReturnValue> + 'static;
             fn construct(#fargs) -> Self::Fut {
                 #task_inner_ident(#(#full_args,)*)
             }
@@ -141,7 +153,7 @@ pub fn run(args: TokenStream, item: TokenStream) -> TokenStream {
 
         const POOL_SIZE: usize = #pool_size;
         static POOL: #embassy_executor::raw::TaskPool<<() as _EmbassyInternalTaskTrait>::Fut, POOL_SIZE> = #embassy_executor::raw::TaskPool::new();
-        unsafe { POOL._spawn_async_fn(move || <() as _EmbassyInternalTaskTrait>::construct(#(#full_args,)*)) }
+        unsafe { POOL.#spawn(move || <() as _EmbassyInternalTaskTrait>::construct(#(#full_args,)*)) }
     };
     #[cfg(not(feature = "nightly"))]
     let mut task_outer_body = quote! {
@@ -158,7 +170,7 @@ pub fn run(args: TokenStream, item: TokenStream) -> TokenStream {
             {#embassy_executor::_export::task_pool_size::<_, _, _, POOL_SIZE>(#task_inner_ident)},
             {#embassy_executor::_export::task_pool_align::<_, _, _, POOL_SIZE>(#task_inner_ident)},
         > = unsafe { ::core::mem::transmute(#embassy_executor::_export::task_pool_new::<_, _, _, POOL_SIZE>(#task_inner_ident)) };
-        unsafe { __task_pool_get(#task_inner_ident)._spawn_async_fn(move || #task_inner_ident(#(#full_args,)*)) }
+        unsafe { __task_pool_get(#task_inner_ident).#spawn(move || #task_inner_ident(#(#full_args,)*)) }
     };
 
     let task_outer_attrs = task_inner.attrs.clone();
diff --git a/embassy-executor/CHANGELOG.md b/embassy-executor/CHANGELOG.md
index 608c67724..914863a83 100644
--- a/embassy-executor/CHANGELOG.md
+++ b/embassy-executor/CHANGELOG.md
@@ -5,9 +5,22 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## unreleased
-
+<!-- next-header -->
+## Unreleased - ReleaseDate
+
+- Added `SpawnToken::id`
+- Task pools are now statically allocated on stable rust. All `task-arena-size-*` features have been removed and are no longer necessary.
+- New trace hooks: `_embassy_trace_poll_start` & `_embassy_trace_task_end`
+- Added task naming capability to tracing infrastructure
+- Added `Executor::id` & `Spawner::executor_id`
+- Disable `critical-section/std` for arch-std
+- Added possibility to select an executor in `#[embassy_executor::main]`
+- Fix AVR executor
+- executor: Make state implementations and their conditions match
 - Added support for Cortex-A and Cortex-R
+- Added support for `-> impl Future<Output = ()>` in `#[task]`
+- Fixed `Send` unsoundness with `-> impl Future` tasks
+- Marked `Spawner::for_current_executor` as `unsafe`
 
 ## 0.7.0 - 2025-01-02
 
diff --git a/embassy-executor/Cargo.toml b/embassy-executor/Cargo.toml
index f014ccf30..2dbf2c29a 100644
--- a/embassy-executor/Cargo.toml
+++ b/embassy-executor/Cargo.toml
@@ -59,6 +59,7 @@ avr-device = { version = "0.7.0", optional = true }
 critical-section = { version = "1.1", features = ["std"] }
 trybuild = "1.0"
 embassy-sync = { path = "../embassy-sync" }
+rustversion = "1.0.21"
 
 [features]
 
diff --git a/embassy-executor/build_common.rs b/embassy-executor/build_common.rs
index b15a8369f..4f24e6d37 100644
--- a/embassy-executor/build_common.rs
+++ b/embassy-executor/build_common.rs
@@ -92,35 +92,3 @@ pub fn set_target_cfgs(cfgs: &mut CfgSet) {
 
     cfgs.set("has_fpu", target.ends_with("-eabihf"));
 }
-
-#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
-pub struct CompilerDate {
-    year: u16,
-    month: u8,
-    day: u8,
-}
-
-impl CompilerDate {
-    fn parse(date: &str) -> Option<Self> {
-        let mut parts = date.split('-');
-        let year = parts.next()?.parse().ok()?;
-        let month = parts.next()?.parse().ok()?;
-        let day = parts.next()?.parse().ok()?;
-        Some(Self { year, month, day })
-    }
-}
-
-impl PartialEq<&str> for CompilerDate {
-    fn eq(&self, other: &&str) -> bool {
-        let Some(other) = Self::parse(other) else {
-            return false;
-        };
-        self.eq(&other)
-    }
-}
-
-impl PartialOrd<&str> for CompilerDate {
-    fn partial_cmp(&self, other: &&str) -> Option<std::cmp::Ordering> {
-        Self::parse(other).map(|other| self.cmp(&other))
-    }
-}
diff --git a/embassy-executor/release.toml b/embassy-executor/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/embassy-executor/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/embassy-executor/src/lib.rs b/embassy-executor/src/lib.rs
index dfe420bab..e174a0594 100644
--- a/embassy-executor/src/lib.rs
+++ b/embassy-executor/src/lib.rs
@@ -65,8 +65,17 @@ pub mod _export {
 
     use crate::raw::TaskPool;
 
+    trait TaskReturnValue {}
+    impl TaskReturnValue for () {}
+    impl TaskReturnValue for Never {}
+
+    #[diagnostic::on_unimplemented(
+        message = "task futures must resolve to `()` or `!`",
+        note = "use `async fn` or change the return type to `impl Future<Output = ()>`"
+    )]
+    #[allow(private_bounds)]
     pub trait TaskFn<Args>: Copy {
-        type Fut: Future + 'static;
+        type Fut: Future<Output: TaskReturnValue> + 'static;
     }
 
     macro_rules! task_fn_impl {
@@ -74,7 +83,7 @@ pub mod _export {
             impl<F, Fut, $($Tn,)*> TaskFn<($($Tn,)*)> for F
             where
                 F: Copy + FnOnce($($Tn,)*) -> Fut,
-                Fut: Future + 'static,
+                Fut: Future<Output: TaskReturnValue> + 'static,
             {
                 type Fut = Fut;
             }
@@ -205,4 +214,42 @@ pub mod _export {
         Align268435456: 268435456,
         Align536870912: 536870912,
     );
+
+    #[allow(dead_code)]
+    trait HasOutput {
+        type Output;
+    }
+
+    impl<O> HasOutput for fn() -> O {
+        type Output = O;
+    }
+
+    #[allow(dead_code)]
+    type Never = <fn() -> ! as HasOutput>::Output;
+}
+
+/// Implementation details for embassy macros.
+/// Do not use. Used for macros and HALs only. Not covered by semver guarantees.
+#[doc(hidden)]
+#[cfg(feature = "nightly")]
+pub mod _export {
+    #[diagnostic::on_unimplemented(
+        message = "task futures must resolve to `()` or `!`",
+        note = "use `async fn` or change the return type to `impl Future<Output = ()>`"
+    )]
+    pub trait TaskReturnValue {}
+    impl TaskReturnValue for () {}
+    impl TaskReturnValue for Never {}
+
+    #[allow(dead_code)]
+    trait HasOutput {
+        type Output;
+    }
+
+    impl<O> HasOutput for fn() -> O {
+        type Output = O;
+    }
+
+    #[allow(dead_code)]
+    type Never = <fn() -> ! as HasOutput>::Output;
 }
diff --git a/embassy-executor/src/raw/trace.rs b/embassy-executor/src/raw/trace.rs
index 6c9cfda25..aa27ab37e 100644
--- a/embassy-executor/src/raw/trace.rs
+++ b/embassy-executor/src/raw/trace.rs
@@ -283,7 +283,17 @@ pub(crate) fn task_new(executor: &SyncExecutor, task: &TaskRef) {
     }
 
     #[cfg(feature = "rtos-trace")]
-    rtos_trace::trace::task_new(task.as_ptr() as u32);
+    {
+        rtos_trace::trace::task_new(task.as_ptr() as u32);
+        let name = task.name().unwrap_or("unnamed task\0");
+        let info = rtos_trace::TaskInfo {
+            name,
+            priority: 0,
+            stack_base: 0,
+            stack_size: 0,
+        };
+        rtos_trace::trace::task_send_info(task.id(), info);
+    }
 
     #[cfg(feature = "rtos-trace")]
     TASK_TRACKER.add(*task);
diff --git a/embassy-executor/src/spawner.rs b/embassy-executor/src/spawner.rs
index 522d97db3..2909d19a0 100644
--- a/embassy-executor/src/spawner.rs
+++ b/embassy-executor/src/spawner.rs
@@ -122,10 +122,26 @@ impl Spawner {
     /// This function is `async` just to get access to the current async
     /// context. It returns instantly, it does not block/yield.
     ///
+    /// Using this method is discouraged due to it being unsafe. Consider the following
+    /// alternatives instead:
+    ///
+    /// - Pass the initial `Spawner` as an argument to tasks. Note that it's `Copy`, so you can
+    ///   make as many copies of it as you want.
+    /// - Use `SendSpawner::for_current_executor()` instead, which is safe but can only be used
+    ///   if task arguments are `Send`.
+    ///
+    /// The only case where using this method is absolutely required is obtaining the `Spawner`
+    /// for an `InterruptExecutor`.
+    ///
+    /// # Safety
+    ///
+    /// You must only execute this with an async `Context` created by the Embassy executor.
+    /// You must not execute it with manually-created `Context`s.
+    ///
     /// # Panics
     ///
     /// Panics if the current executor is not an Embassy executor.
-    pub fn for_current_executor() -> impl Future<Output = Self> {
+    pub unsafe fn for_current_executor() -> impl Future<Output = Self> {
         poll_fn(|cx| {
             let task = raw::task_from_waker(cx.waker());
             let executor = unsafe {
diff --git a/embassy-executor/tests/test.rs b/embassy-executor/tests/test.rs
index 78c49c071..c1e7ec5d7 100644
--- a/embassy-executor/tests/test.rs
+++ b/embassy-executor/tests/test.rs
@@ -1,7 +1,8 @@
 #![cfg_attr(feature = "nightly", feature(impl_trait_in_assoc_type))]
+#![cfg_attr(feature = "nightly", feature(never_type))]
 
 use std::boxed::Box;
-use std::future::poll_fn;
+use std::future::{poll_fn, Future};
 use std::sync::{Arc, Mutex};
 use std::task::Poll;
 
@@ -58,6 +59,39 @@ fn executor_task() {
         trace.push("poll task1")
     }
 
+    #[task]
+    async fn task2() -> ! {
+        panic!()
+    }
+
+    let (executor, trace) = setup();
+    executor.spawner().spawn(task1(trace.clone())).unwrap();
+
+    unsafe { executor.poll() };
+    unsafe { executor.poll() };
+
+    assert_eq!(
+        trace.get(),
+        &[
+            "pend",       // spawning a task pends the executor
+            "poll task1", // poll only once.
+        ]
+    )
+}
+
+#[test]
+fn executor_task_rpit() {
+    #[task]
+    fn task1(trace: Trace) -> impl Future<Output = ()> {
+        async move { trace.push("poll task1") }
+    }
+
+    #[cfg(feature = "nightly")]
+    #[task]
+    fn task2() -> impl Future<Output = !> {
+        async { panic!() }
+    }
+
     let (executor, trace) = setup();
     executor.spawner().spawn(task1(trace.clone())).unwrap();
 
diff --git a/embassy-executor/tests/ui.rs b/embassy-executor/tests/ui.rs
index 278a4b903..7757775ee 100644
--- a/embassy-executor/tests/ui.rs
+++ b/embassy-executor/tests/ui.rs
@@ -17,6 +17,17 @@ fn ui() {
     t.compile_fail("tests/ui/nonstatic_struct_elided.rs");
     t.compile_fail("tests/ui/nonstatic_struct_generic.rs");
     t.compile_fail("tests/ui/not_async.rs");
+    t.compile_fail("tests/ui/spawn_nonsend.rs");
+    t.compile_fail("tests/ui/return_impl_future_nonsend.rs");
+    if rustversion::cfg!(stable) {
+        // output is slightly different on nightly
+        t.compile_fail("tests/ui/bad_return_impl_future.rs");
+        t.compile_fail("tests/ui/return_impl_send.rs");
+    }
+    if cfg!(feature = "nightly") {
+        t.compile_fail("tests/ui/bad_return_impl_future_nightly.rs");
+        t.compile_fail("tests/ui/return_impl_send_nightly.rs");
+    }
     t.compile_fail("tests/ui/self_ref.rs");
     t.compile_fail("tests/ui/self.rs");
     t.compile_fail("tests/ui/type_error.rs");
diff --git a/embassy-executor/tests/ui/bad_return_impl_future.rs b/embassy-executor/tests/ui/bad_return_impl_future.rs
new file mode 100644
index 000000000..baaa7dc5a
--- /dev/null
+++ b/embassy-executor/tests/ui/bad_return_impl_future.rs
@@ -0,0 +1,9 @@
+#![cfg_attr(feature = "nightly", feature(impl_trait_in_assoc_type))]
+use core::future::Future;
+
+#[embassy_executor::task]
+fn task() -> impl Future<Output = u32> {
+    async { 5 }
+}
+
+fn main() {}
diff --git a/embassy-executor/tests/ui/bad_return_impl_future.stderr b/embassy-executor/tests/ui/bad_return_impl_future.stderr
new file mode 100644
index 000000000..57f147714
--- /dev/null
+++ b/embassy-executor/tests/ui/bad_return_impl_future.stderr
@@ -0,0 +1,120 @@
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/bad_return_impl_future.rs:5:4
+  |
+4 | #[embassy_executor::task]
+  | ------------------------- required by a bound introduced by this call
+5 | fn task() -> impl Future<Output = u32> {
+  |    ^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Future<Output = u32> {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_size`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_size<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> usize
+  |                  -------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |                         ^^^^^^^^^ required by this bound in `task_pool_size`
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/bad_return_impl_future.rs:4:1
+  |
+4 | #[embassy_executor::task]
+  | ^^^^^^^^^^^^^^^^^^^^^^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Future<Output = u32> {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_size`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_size<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> usize
+  |                  -------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |            ^^^^^^^^^^^^^^^^^^^^^^^ required by this bound in `task_pool_size`
+  = note: this error originates in the attribute macro `embassy_executor::task` (in Nightly builds, run with -Z macro-backtrace for more info)
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/bad_return_impl_future.rs:5:4
+  |
+4 | #[embassy_executor::task]
+  | ------------------------- required by a bound introduced by this call
+5 | fn task() -> impl Future<Output = u32> {
+  |    ^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Future<Output = u32> {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_align`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_align<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> usize
+  |                  --------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |                         ^^^^^^^^^ required by this bound in `task_pool_align`
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/bad_return_impl_future.rs:4:1
+  |
+4 | #[embassy_executor::task]
+  | ^^^^^^^^^^^^^^^^^^^^^^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Future<Output = u32> {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_align`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_align<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> usize
+  |                  --------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |            ^^^^^^^^^^^^^^^^^^^^^^^ required by this bound in `task_pool_align`
+  = note: this error originates in the attribute macro `embassy_executor::task` (in Nightly builds, run with -Z macro-backtrace for more info)
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/bad_return_impl_future.rs:5:4
+  |
+4 | #[embassy_executor::task]
+  | ------------------------- required by a bound introduced by this call
+5 | fn task() -> impl Future<Output = u32> {
+  |    ^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Future<Output = u32> {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `__task_pool_get`
+ --> tests/ui/bad_return_impl_future.rs:4:1
+  |
+4 | #[embassy_executor::task]
+  | ^^^^^^^^^^^^^^^^^^^^^^^^^ required by this bound in `__task_pool_get`
+  = note: this error originates in the attribute macro `embassy_executor::task` (in Nightly builds, run with -Z macro-backtrace for more info)
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/bad_return_impl_future.rs:5:4
+  |
+4 | #[embassy_executor::task]
+  | ------------------------- required by a bound introduced by this call
+5 | fn task() -> impl Future<Output = u32> {
+  |    ^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Future<Output = u32> {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_new`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_new<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> TaskPool<Fut, POOL_SIZE>
+  |                  ------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |                         ^^^^^^^^^ required by this bound in `task_pool_new`
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/bad_return_impl_future.rs:4:1
+  |
+4 | #[embassy_executor::task]
+  | ^^^^^^^^^^^^^^^^^^^^^^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Future<Output = u32> {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_new`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_new<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> TaskPool<Fut, POOL_SIZE>
+  |                  ------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |            ^^^^^^^^^^^^^^^^^^^^^^^ required by this bound in `task_pool_new`
+  = note: this error originates in the attribute macro `embassy_executor::task` (in Nightly builds, run with -Z macro-backtrace for more info)
diff --git a/embassy-executor/tests/ui/bad_return_impl_future_nightly.rs b/embassy-executor/tests/ui/bad_return_impl_future_nightly.rs
new file mode 100644
index 000000000..baaa7dc5a
--- /dev/null
+++ b/embassy-executor/tests/ui/bad_return_impl_future_nightly.rs
@@ -0,0 +1,9 @@
+#![cfg_attr(feature = "nightly", feature(impl_trait_in_assoc_type))]
+use core::future::Future;
+
+#[embassy_executor::task]
+fn task() -> impl Future<Output = u32> {
+    async { 5 }
+}
+
+fn main() {}
diff --git a/embassy-executor/tests/ui/bad_return_impl_future_nightly.stderr b/embassy-executor/tests/ui/bad_return_impl_future_nightly.stderr
new file mode 100644
index 000000000..73ceb989d
--- /dev/null
+++ b/embassy-executor/tests/ui/bad_return_impl_future_nightly.stderr
@@ -0,0 +1,10 @@
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/bad_return_impl_future_nightly.rs:4:1
+  |
+4 | #[embassy_executor::task]
+  | ^^^^^^^^^^^^^^^^^^^^^^^^^ the trait `TaskReturnValue` is not implemented for `u32`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+  = help: the following other types implement trait `TaskReturnValue`:
+            ()
+            <fn() -> ! as _export::HasOutput>::Output
diff --git a/embassy-executor/tests/ui/return_impl_future_nonsend.rs b/embassy-executor/tests/ui/return_impl_future_nonsend.rs
new file mode 100644
index 000000000..b8c184b21
--- /dev/null
+++ b/embassy-executor/tests/ui/return_impl_future_nonsend.rs
@@ -0,0 +1,21 @@
+#![cfg_attr(feature = "nightly", feature(impl_trait_in_assoc_type))]
+
+use core::future::Future;
+
+use embassy_executor::SendSpawner;
+
+#[embassy_executor::task]
+fn task() -> impl Future<Output = ()> {
+    // runs in spawning thread
+    let non_send: *mut () = core::ptr::null_mut();
+    async move {
+        // runs in executor thread
+        println!("{}", non_send as usize);
+    }
+}
+
+fn send_spawn(s: SendSpawner) {
+    s.spawn(task()).unwrap();
+}
+
+fn main() {}
diff --git a/embassy-executor/tests/ui/return_impl_future_nonsend.stderr b/embassy-executor/tests/ui/return_impl_future_nonsend.stderr
new file mode 100644
index 000000000..8aeb9738a
--- /dev/null
+++ b/embassy-executor/tests/ui/return_impl_future_nonsend.stderr
@@ -0,0 +1,17 @@
+error: future cannot be sent between threads safely
+  --> tests/ui/return_impl_future_nonsend.rs:18:13
+   |
+18 |     s.spawn(task()).unwrap();
+   |             ^^^^^^ future created by async block is not `Send`
+   |
+   = help: within `impl Sized`, the trait `Send` is not implemented for `*mut ()`
+note: captured value is not `Send`
+  --> tests/ui/return_impl_future_nonsend.rs:13:24
+   |
+13 |         println!("{}", non_send as usize);
+   |                        ^^^^^^^^ has type `*mut ()` which is not `Send`
+note: required by a bound in `SendSpawner::spawn`
+  --> src/spawner.rs
+   |
+   |     pub fn spawn<S: Send>(&self, token: SpawnToken<S>) -> Result<(), SpawnError> {
+   |                     ^^^^ required by this bound in `SendSpawner::spawn`
diff --git a/embassy-executor/tests/ui/return_impl_send.rs b/embassy-executor/tests/ui/return_impl_send.rs
new file mode 100644
index 000000000..6ddb0e722
--- /dev/null
+++ b/embassy-executor/tests/ui/return_impl_send.rs
@@ -0,0 +1,6 @@
+#![cfg_attr(feature = "nightly", feature(impl_trait_in_assoc_type))]
+
+#[embassy_executor::task]
+fn task() -> impl Send {}
+
+fn main() {}
diff --git a/embassy-executor/tests/ui/return_impl_send.stderr b/embassy-executor/tests/ui/return_impl_send.stderr
new file mode 100644
index 000000000..759be1cde
--- /dev/null
+++ b/embassy-executor/tests/ui/return_impl_send.stderr
@@ -0,0 +1,137 @@
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/return_impl_send.rs:4:4
+  |
+3 | #[embassy_executor::task]
+  | ------------------------- required by a bound introduced by this call
+4 | fn task() -> impl Send {}
+  |    ^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Send {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_size`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_size<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> usize
+  |                  -------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |                         ^^^^^^^^^ required by this bound in `task_pool_size`
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/return_impl_send.rs:3:1
+  |
+3 | #[embassy_executor::task]
+  | ^^^^^^^^^^^^^^^^^^^^^^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Send {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_size`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_size<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> usize
+  |                  -------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |            ^^^^^^^^^^^^^^^^^^^^^^^ required by this bound in `task_pool_size`
+  = note: this error originates in the attribute macro `embassy_executor::task` (in Nightly builds, run with -Z macro-backtrace for more info)
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/return_impl_send.rs:4:4
+  |
+3 | #[embassy_executor::task]
+  | ------------------------- required by a bound introduced by this call
+4 | fn task() -> impl Send {}
+  |    ^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Send {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_align`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_align<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> usize
+  |                  --------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |                         ^^^^^^^^^ required by this bound in `task_pool_align`
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/return_impl_send.rs:3:1
+  |
+3 | #[embassy_executor::task]
+  | ^^^^^^^^^^^^^^^^^^^^^^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Send {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_align`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_align<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> usize
+  |                  --------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |            ^^^^^^^^^^^^^^^^^^^^^^^ required by this bound in `task_pool_align`
+  = note: this error originates in the attribute macro `embassy_executor::task` (in Nightly builds, run with -Z macro-backtrace for more info)
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/return_impl_send.rs:4:4
+  |
+3 | #[embassy_executor::task]
+  | ------------------------- required by a bound introduced by this call
+4 | fn task() -> impl Send {}
+  |    ^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Send {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `__task_pool_get`
+ --> tests/ui/return_impl_send.rs:3:1
+  |
+3 | #[embassy_executor::task]
+  | ^^^^^^^^^^^^^^^^^^^^^^^^^ required by this bound in `__task_pool_get`
+  = note: this error originates in the attribute macro `embassy_executor::task` (in Nightly builds, run with -Z macro-backtrace for more info)
+
+error[E0277]: `impl Send` is not a future
+ --> tests/ui/return_impl_send.rs:3:1
+  |
+3 | #[embassy_executor::task]
+  | ^^^^^^^^^^^^^^^^^^^^^^^^^ `impl Send` is not a future
+  |
+  = help: the trait `Future` is not implemented for `impl Send`
+note: required by a bound in `TaskPool::<F, N>::spawn`
+ --> src/raw/mod.rs
+  |
+  | impl<F: Future + 'static, const N: usize> TaskPool<F, N> {
+  |         ^^^^^^ required by this bound in `TaskPool::<F, N>::spawn`
+...
+  |     pub fn spawn(&'static self, future: impl FnOnce() -> F) -> SpawnToken<impl Sized> {
+  |            ----- required by a bound in this associated function
+  = note: this error originates in the attribute macro `embassy_executor::task` (in Nightly builds, run with -Z macro-backtrace for more info)
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/return_impl_send.rs:4:4
+  |
+3 | #[embassy_executor::task]
+  | ------------------------- required by a bound introduced by this call
+4 | fn task() -> impl Send {}
+  |    ^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Send {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_new`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_new<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> TaskPool<Fut, POOL_SIZE>
+  |                  ------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |                         ^^^^^^^^^ required by this bound in `task_pool_new`
+
+error[E0277]: task futures must resolve to `()` or `!`
+ --> tests/ui/return_impl_send.rs:3:1
+  |
+3 | #[embassy_executor::task]
+  | ^^^^^^^^^^^^^^^^^^^^^^^^^ the trait `TaskFn<_>` is not implemented for fn item `fn() -> impl Send {__task_task}`
+  |
+  = note: use `async fn` or change the return type to `impl Future<Output = ()>`
+note: required by a bound in `task_pool_new`
+ --> src/lib.rs
+  |
+  |     pub const fn task_pool_new<F, Args, Fut, const POOL_SIZE: usize>(_: F) -> TaskPool<Fut, POOL_SIZE>
+  |                  ------------- required by a bound in this function
+  |     where
+  |         F: TaskFn<Args, Fut = Fut>,
+  |            ^^^^^^^^^^^^^^^^^^^^^^^ required by this bound in `task_pool_new`
+  = note: this error originates in the attribute macro `embassy_executor::task` (in Nightly builds, run with -Z macro-backtrace for more info)
diff --git a/embassy-executor/tests/ui/return_impl_send_nightly.rs b/embassy-executor/tests/ui/return_impl_send_nightly.rs
new file mode 100644
index 000000000..6ddb0e722
--- /dev/null
+++ b/embassy-executor/tests/ui/return_impl_send_nightly.rs
@@ -0,0 +1,6 @@
+#![cfg_attr(feature = "nightly", feature(impl_trait_in_assoc_type))]
+
+#[embassy_executor::task]
+fn task() -> impl Send {}
+
+fn main() {}
diff --git a/embassy-executor/tests/ui/return_impl_send_nightly.stderr b/embassy-executor/tests/ui/return_impl_send_nightly.stderr
new file mode 100644
index 000000000..de9ba6243
--- /dev/null
+++ b/embassy-executor/tests/ui/return_impl_send_nightly.stderr
@@ -0,0 +1,10 @@
+error[E0277]: `impl Send` is not a future
+ --> tests/ui/return_impl_send_nightly.rs:3:1
+  |
+3 | #[embassy_executor::task]
+  | ^^^^^^^^^^^^^^^^^^^^^^^^^
+  | |
+  | `impl Send` is not a future
+  | return type was inferred to be `impl Send` here
+  |
+  = help: the trait `Future` is not implemented for `impl Send`
diff --git a/embassy-executor/tests/ui/spawn_nonsend.rs b/embassy-executor/tests/ui/spawn_nonsend.rs
new file mode 100644
index 000000000..4c4cc7697
--- /dev/null
+++ b/embassy-executor/tests/ui/spawn_nonsend.rs
@@ -0,0 +1,16 @@
+#![cfg_attr(feature = "nightly", feature(impl_trait_in_assoc_type))]
+
+use core::future::Future;
+
+use embassy_executor::SendSpawner;
+
+#[embassy_executor::task]
+async fn task(non_send: *mut ()) {
+    println!("{}", non_send as usize);
+}
+
+fn send_spawn(s: SendSpawner) {
+    s.spawn(task(core::ptr::null_mut())).unwrap();
+}
+
+fn main() {}
diff --git a/embassy-executor/tests/ui/spawn_nonsend.stderr b/embassy-executor/tests/ui/spawn_nonsend.stderr
new file mode 100644
index 000000000..2a06c8b94
--- /dev/null
+++ b/embassy-executor/tests/ui/spawn_nonsend.stderr
@@ -0,0 +1,41 @@
+warning: unused import: `core::future::Future`
+ --> tests/ui/spawn_nonsend.rs:3:5
+  |
+3 | use core::future::Future;
+  |     ^^^^^^^^^^^^^^^^^^^^
+  |
+  = note: `#[warn(unused_imports)]` on by default
+
+error[E0277]: `*mut ()` cannot be sent between threads safely
+  --> tests/ui/spawn_nonsend.rs:13:13
+   |
+7  | #[embassy_executor::task]
+   | ------------------------- within this `impl Sized`
+...
+13 |     s.spawn(task(core::ptr::null_mut())).unwrap();
+   |       ----- ^^^^^^^^^^^^^^^^^^^^^^^^^^^ `*mut ()` cannot be sent between threads safely
+   |       |
+   |       required by a bound introduced by this call
+   |
+   = help: within `impl Sized`, the trait `Send` is not implemented for `*mut ()`
+note: required because it's used within this closure
+  --> tests/ui/spawn_nonsend.rs:7:1
+   |
+7  | #[embassy_executor::task]
+   | ^^^^^^^^^^^^^^^^^^^^^^^^^
+note: required because it appears within the type `impl Sized`
+  --> src/raw/mod.rs
+   |
+   |     pub unsafe fn _spawn_async_fn<FutFn>(&'static self, future: FutFn) -> SpawnToken<impl Sized>
+   |                                                                                      ^^^^^^^^^^
+note: required because it appears within the type `impl Sized`
+  --> tests/ui/spawn_nonsend.rs:7:1
+   |
+7  | #[embassy_executor::task]
+   | ^^^^^^^^^^^^^^^^^^^^^^^^^
+note: required by a bound in `SendSpawner::spawn`
+  --> src/spawner.rs
+   |
+   |     pub fn spawn<S: Send>(&self, token: SpawnToken<S>) -> Result<(), SpawnError> {
+   |                     ^^^^ required by this bound in `SendSpawner::spawn`
+   = note: this error originates in the attribute macro `embassy_executor::task` (in Nightly builds, run with -Z macro-backtrace for more info)
diff --git a/embassy-futures/CHANGELOG.md b/embassy-futures/CHANGELOG.md
new file mode 100644
index 000000000..eb76cdc4a
--- /dev/null
+++ b/embassy-futures/CHANGELOG.md
@@ -0,0 +1,14 @@
+# Changelog for embassy-futures
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
+and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
+
+<!-- next-header -->
+## Unreleased - ReleaseDate
+
+- Preserve location information for `defmt` in `fmt` calls ([#3085](https://github.com/embassy-rs/embassy/pull/3085))
+- Fixed soundness issue in `select_slice` ([#3328](https://github.com/embassy-rs/embassy/pull/3328))
+- Added `select5` and `select6` ([#3430](https://github.com/embassy-rs/embassy/pull/3430))
+- Added `is_x` methods for all `EitherN` enum variants (#[3650](https://github.com/embassy-rs/embassy/pull/3650))
diff --git a/embassy-futures/release.toml b/embassy-futures/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/embassy-futures/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/embassy-hal-internal/Cargo.toml b/embassy-hal-internal/Cargo.toml
index cc360682e..b4c52ccfa 100644
--- a/embassy-hal-internal/Cargo.toml
+++ b/embassy-hal-internal/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-hal-internal"
-version = "0.2.0"
+version = "0.3.0"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "Internal implementation details for Embassy HALs. DO NOT USE DIRECTLY."
diff --git a/embassy-imxrt/Cargo.toml b/embassy-imxrt/Cargo.toml
index 49dc8089c..df4687043 100644
--- a/embassy-imxrt/Cargo.toml
+++ b/embassy-imxrt/Cargo.toml
@@ -67,8 +67,8 @@ embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
 embassy-time-driver = { version = "0.2", path = "../embassy-time-driver", optional = true }
 embassy-time-queue-utils = { version = "0.1", path = "../embassy-time-queue-utils", optional = true }
 embassy-time = { version = "0.4", path = "../embassy-time", optional = true }
-embassy-hal-internal = { version = "0.2.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-3"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../embassy-embedded-hal", default-features = false }
+embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-3"] }
+embassy-embedded-hal = { version = "0.3.1", path = "../embassy-embedded-hal", default-features = false }
 embassy-futures = { version = "0.1.1", path = "../embassy-futures" }
 
 defmt = { version = "1.0.1", optional = true }
diff --git a/embassy-imxrt/src/lib.rs b/embassy-imxrt/src/lib.rs
index 5846afe5c..a3437c655 100644
--- a/embassy-imxrt/src/lib.rs
+++ b/embassy-imxrt/src/lib.rs
@@ -76,9 +76,11 @@ macro_rules! bind_interrupts {
             #[allow(non_snake_case)]
             #[no_mangle]
             unsafe extern "C" fn $irq() {
-                $(
-                    <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
-                )*
+                unsafe {
+                    $(
+                        <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
+                    )*
+                }
             }
 
             $(
diff --git a/embassy-mspm0/Cargo.toml b/embassy-mspm0/Cargo.toml
index 456d302af..61afcd76d 100644
--- a/embassy-mspm0/Cargo.toml
+++ b/embassy-mspm0/Cargo.toml
@@ -31,12 +31,15 @@ embassy-time = { version = "0.4.0", path = "../embassy-time", optional = true }
 embassy-time-driver = { version = "0.2", path = "../embassy-time-driver", optional = true, features = ["tick-hz-32_768"] }
 embassy-time-queue-utils = { version = "0.1", path = "../embassy-time-queue-utils", optional = true }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
-embassy-hal-internal = { version = "0.2.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-2"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../embassy-embedded-hal", default-features = false }
+embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-2"] }
+embassy-embedded-hal = { version = "0.3.1", path = "../embassy-embedded-hal", default-features = false }
 embassy-executor = { version = "0.7.0", path = "../embassy-executor", optional = true }
 
 embedded-hal = { version = "1.0" }
+embedded-hal-nb = { version = "1.0" }
 embedded-hal-async = { version = "1.0" }
+embedded-io = "0.6.1"
+embedded-io-async = "0.6.1"
 
 defmt = { version = "1.0.1", optional = true }
 fixed = "1.29"
@@ -46,14 +49,15 @@ cortex-m = "0.7.6"
 critical-section = "1.2.0"
 
 # mspm0-metapac = { version = "" }
-mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-26a6f681eda4ef120e8cb614a1631727c848590f" }
+mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-235158ac2865d8aac3a1eceb2d62026eb12bf38f" }
 
 [build-dependencies]
 proc-macro2 = "1.0.94"
 quote = "1.0.40"
+cfg_aliases = "0.2.1"
 
 # mspm0-metapac = { version = "", default-features = false, features = ["metadata"] }
-mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-26a6f681eda4ef120e8cb614a1631727c848590f", default-features = false, features = ["metadata"] }
+mspm0-metapac = { git = "https://github.com/mspm0-rs/mspm0-data-generated/", tag = "mspm0-data-235158ac2865d8aac3a1eceb2d62026eb12bf38f", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]
diff --git a/embassy-mspm0/build.rs b/embassy-mspm0/build.rs
index 6cd62895b..b9ba3aecf 100644
--- a/embassy-mspm0/build.rs
+++ b/embassy-mspm0/build.rs
@@ -67,6 +67,7 @@ fn generate_code() {
     g.extend(generate_peripheral_instances());
     g.extend(generate_pin_trait_impls());
     g.extend(generate_groups());
+    g.extend(generate_dma_channel_count());
 
     let out_dir = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
     let out_file = out_dir.join("_generated.rs").to_string_lossy().to_string();
@@ -209,6 +210,12 @@ fn generate_groups() -> TokenStream {
     }
 }
 
+fn generate_dma_channel_count() -> TokenStream {
+    let count = METADATA.dma_channels.len();
+
+    quote! { pub const DMA_CHANNELS: usize = #count; }
+}
+
 #[derive(Debug, Clone)]
 struct Singleton {
     name: String,
@@ -543,8 +550,6 @@ fn generate_peripheral_instances() -> TokenStream {
     for peripheral in METADATA.peripherals {
         let peri = format_ident!("{}", peripheral.name);
 
-        // Will be filled in when uart implementation is finished
-        let _ = peri;
         let tokens = match peripheral.kind {
             "uart" => Some(quote! { impl_uart_instance!(#peri); }),
             _ => None,
@@ -555,6 +560,18 @@ fn generate_peripheral_instances() -> TokenStream {
         }
     }
 
+    // DMA channels
+    for dma_channel in METADATA.dma_channels.iter() {
+        let peri = format_ident!("DMA_CH{}", dma_channel.number);
+        let num = dma_channel.number;
+
+        if dma_channel.full {
+            impls.push(quote! { impl_full_dma_channel!(#peri, #num); });
+        } else {
+            impls.push(quote! { impl_dma_channel!(#peri, #num); });
+        }
+    }
+
     quote! {
         #(#impls)*
     }
diff --git a/embassy-mspm0/src/dma.rs b/embassy-mspm0/src/dma.rs
new file mode 100644
index 000000000..66b79709c
--- /dev/null
+++ b/embassy-mspm0/src/dma.rs
@@ -0,0 +1,626 @@
+//! Direct Memory Access (DMA)
+
+#![macro_use]
+
+use core::future::Future;
+use core::mem;
+use core::pin::Pin;
+use core::sync::atomic::{compiler_fence, Ordering};
+use core::task::{Context, Poll};
+
+use critical_section::CriticalSection;
+use embassy_hal_internal::interrupt::InterruptExt;
+use embassy_hal_internal::{impl_peripheral, PeripheralType};
+use embassy_sync::waitqueue::AtomicWaker;
+use mspm0_metapac::common::{Reg, RW};
+use mspm0_metapac::dma::regs;
+use mspm0_metapac::dma::vals::{self, Autoen, Em, Incr, Preirq, Wdth};
+
+use crate::{interrupt, pac, Peri};
+
+/// The burst size of a DMA transfer.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum BurstSize {
+    /// The whole block transfer is completed in one transfer without interruption.
+    Complete,
+
+    /// The burst size is 8, after 9 transfers the block transfer is interrupted and the priority
+    /// is reevaluated.
+    _8,
+
+    /// The burst size is 16, after 17 transfers the block transfer is interrupted and the priority
+    /// is reevaluated.
+    _16,
+
+    /// The burst size is 32, after 32 transfers the block transfer is interrupted and the priority
+    /// is reevaluated.
+    _32,
+}
+
+/// DMA channel.
+#[allow(private_bounds)]
+pub trait Channel: Into<AnyChannel> + PeripheralType {}
+
+/// Full DMA channel.
+#[allow(private_bounds)]
+pub trait FullChannel: Channel + Into<AnyFullChannel> {}
+
+/// Type-erased DMA channel.
+pub struct AnyChannel {
+    pub(crate) id: u8,
+}
+impl_peripheral!(AnyChannel);
+
+impl SealedChannel for AnyChannel {
+    fn id(&self) -> u8 {
+        self.id
+    }
+}
+impl Channel for AnyChannel {}
+
+/// Type-erased full DMA channel.
+pub struct AnyFullChannel {
+    pub(crate) id: u8,
+}
+impl_peripheral!(AnyFullChannel);
+
+impl SealedChannel for AnyFullChannel {
+    fn id(&self) -> u8 {
+        self.id
+    }
+}
+impl Channel for AnyFullChannel {}
+impl FullChannel for AnyFullChannel {}
+
+impl From<AnyFullChannel> for AnyChannel {
+    fn from(value: AnyFullChannel) -> Self {
+        Self { id: value.id }
+    }
+}
+
+#[allow(private_bounds)]
+pub trait Word: SealedWord {
+    /// Size in bytes for the width.
+    fn size() -> isize;
+}
+
+impl SealedWord for u8 {
+    fn width() -> vals::Wdth {
+        vals::Wdth::BYTE
+    }
+}
+impl Word for u8 {
+    fn size() -> isize {
+        1
+    }
+}
+
+impl SealedWord for u16 {
+    fn width() -> vals::Wdth {
+        vals::Wdth::HALF
+    }
+}
+impl Word for u16 {
+    fn size() -> isize {
+        2
+    }
+}
+
+impl SealedWord for u32 {
+    fn width() -> vals::Wdth {
+        vals::Wdth::WORD
+    }
+}
+impl Word for u32 {
+    fn size() -> isize {
+        4
+    }
+}
+
+impl SealedWord for u64 {
+    fn width() -> vals::Wdth {
+        vals::Wdth::LONG
+    }
+}
+impl Word for u64 {
+    fn size() -> isize {
+        8
+    }
+}
+
+// TODO: u128 (LONGLONG) support. G350x does support it, but other parts do not such as C110x. More metadata is
+// needed to properly enable this.
+// impl SealedWord for u128 {
+//     fn width() -> vals::Wdth {
+//         vals::Wdth::LONGLONG
+//     }
+// }
+// impl Word for u128 {
+//     fn size() -> isize {
+//         16
+//     }
+// }
+
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    /// The DMA transfer is too large.
+    ///
+    /// The hardware limits the DMA to 16384 transfers per channel at a time. This means that transferring
+    /// 16384 `u8` and 16384 `u64` are equivalent, since the DMA must copy 16384 values.
+    TooManyTransfers,
+}
+
+/// DMA transfer mode for basic channels.
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum TransferMode {
+    /// Each DMA trigger will transfer a single value.
+    Single,
+
+    /// Each DMA trigger will transfer the complete block with one trigger.
+    Block,
+}
+
+/// DMA transfer options.
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub struct TransferOptions {
+    /// DMA transfer mode.
+    pub mode: TransferMode,
+    // TODO: Read and write stride.
+}
+
+impl Default for TransferOptions {
+    fn default() -> Self {
+        Self {
+            mode: TransferMode::Single,
+        }
+    }
+}
+
+/// DMA transfer.
+#[must_use = "futures do nothing unless you `.await` or poll them"]
+pub struct Transfer<'a> {
+    channel: Peri<'a, AnyChannel>,
+}
+
+impl<'a> Transfer<'a> {
+    /// Software trigger source.
+    ///
+    /// Using this trigger source means that a transfer will start immediately rather than waiting for
+    /// a hardware event. This can be useful if you want to do a DMA accelerated memcpy.
+    pub const SOFTWARE_TRIGGER: u8 = 0;
+
+    /// Create a new read DMA transfer.
+    pub unsafe fn new_read<SW: Word, DW: Word>(
+        channel: Peri<'a, impl Channel>,
+        trigger_source: u8,
+        src: *mut SW,
+        dst: &'a mut [DW],
+        options: TransferOptions,
+    ) -> Result<Self, Error> {
+        Self::new_read_raw(channel, trigger_source, src, dst, options)
+    }
+
+    /// Create a new read DMA transfer, using raw pointers.
+    pub unsafe fn new_read_raw<SW: Word, DW: Word>(
+        channel: Peri<'a, impl Channel>,
+        trigger_source: u8,
+        src: *mut SW,
+        dst: *mut [DW],
+        options: TransferOptions,
+    ) -> Result<Self, Error> {
+        verify_transfer::<DW>(dst)?;
+
+        let channel = channel.into();
+        channel.configure(
+            trigger_source,
+            src.cast(),
+            SW::width(),
+            dst.cast(),
+            DW::width(),
+            dst.len() as u16,
+            false,
+            true,
+            options,
+        );
+        channel.start();
+
+        Ok(Self { channel })
+    }
+
+    /// Create a new write DMA transfer.
+    pub unsafe fn new_write<SW: Word, DW: Word>(
+        channel: Peri<'a, impl Channel>,
+        trigger_source: u8,
+        src: &'a [SW],
+        dst: *mut DW,
+        options: TransferOptions,
+    ) -> Result<Self, Error> {
+        Self::new_write_raw(channel, trigger_source, src, dst, options)
+    }
+
+    /// Create a new write DMA transfer, using raw pointers.
+    pub unsafe fn new_write_raw<SW: Word, DW: Word>(
+        channel: Peri<'a, impl Channel>,
+        trigger_source: u8,
+        src: *const [SW],
+        dst: *mut DW,
+        options: TransferOptions,
+    ) -> Result<Self, Error> {
+        verify_transfer::<SW>(src)?;
+
+        let channel = channel.into();
+        channel.configure(
+            trigger_source,
+            src.cast(),
+            SW::width(),
+            dst.cast(),
+            DW::width(),
+            src.len() as u16,
+            true,
+            false,
+            options,
+        );
+        channel.start();
+
+        Ok(Self { channel })
+    }
+
+    // TODO: Copy between slices.
+
+    /// Request the transfer to resume.
+    pub fn resume(&mut self) {
+        self.channel.resume();
+    }
+
+    /// Request the transfer to pause, keeping the existing configuration for this channel.
+    /// To restart the transfer, call [`start`](Self::start) again.
+    ///
+    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
+    pub fn request_pause(&mut self) {
+        self.channel.request_pause();
+    }
+
+    /// Return whether this transfer is still running.
+    ///
+    /// If this returns [`false`], it can be because either the transfer finished, or
+    /// it was requested to stop early with [`request_stop`].
+    pub fn is_running(&mut self) -> bool {
+        self.channel.is_running()
+    }
+
+    /// Blocking wait until the transfer finishes.
+    pub fn blocking_wait(mut self) {
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        compiler_fence(Ordering::SeqCst);
+
+        while self.is_running() {}
+
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        compiler_fence(Ordering::SeqCst);
+
+        // Prevent drop from being called since we ran to completion (drop will try to pause).
+        mem::forget(self);
+    }
+}
+
+impl<'a> Unpin for Transfer<'a> {}
+impl<'a> Future for Transfer<'a> {
+    type Output = ();
+
+    fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
+        let state: &ChannelState = &STATE[self.channel.id as usize];
+
+        state.waker.register(cx.waker());
+
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        compiler_fence(Ordering::SeqCst);
+
+        if self.channel.is_running() {
+            Poll::Pending
+        } else {
+            Poll::Ready(())
+        }
+    }
+}
+
+impl<'a> Drop for Transfer<'a> {
+    fn drop(&mut self) {
+        self.channel.request_pause();
+        while self.is_running() {}
+
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        compiler_fence(Ordering::SeqCst);
+    }
+}
+
+// impl details
+
+fn verify_transfer<W: Word>(ptr: *const [W]) -> Result<(), Error> {
+    if ptr.len() > (u16::MAX as usize) {
+        return Err(Error::TooManyTransfers);
+    }
+
+    // TODO: Stride checks
+
+    Ok(())
+}
+
+fn convert_burst_size(value: BurstSize) -> vals::Burstsz {
+    match value {
+        BurstSize::Complete => vals::Burstsz::INFINITI,
+        BurstSize::_8 => vals::Burstsz::BURST_8,
+        BurstSize::_16 => vals::Burstsz::BURST_16,
+        BurstSize::_32 => vals::Burstsz::BURST_32,
+    }
+}
+
+fn convert_mode(mode: TransferMode) -> vals::Tm {
+    match mode {
+        TransferMode::Single => vals::Tm::SINGLE,
+        TransferMode::Block => vals::Tm::BLOCK,
+    }
+}
+
+const CHANNEL_COUNT: usize = crate::_generated::DMA_CHANNELS;
+static STATE: [ChannelState; CHANNEL_COUNT] = [const { ChannelState::new() }; CHANNEL_COUNT];
+
+struct ChannelState {
+    waker: AtomicWaker,
+}
+
+impl ChannelState {
+    const fn new() -> Self {
+        Self {
+            waker: AtomicWaker::new(),
+        }
+    }
+}
+
+/// SAFETY: Must only be called once.
+///
+/// Changing the burst size mid transfer may have some odd behavior.
+pub(crate) unsafe fn init(_cs: CriticalSection, burst_size: BurstSize, round_robin: bool) {
+    pac::DMA.prio().modify(|prio| {
+        prio.set_burstsz(convert_burst_size(burst_size));
+        prio.set_roundrobin(round_robin);
+    });
+    pac::DMA.int_event(0).imask().modify(|w| {
+        w.set_dataerr(true);
+        w.set_addrerr(true);
+    });
+
+    interrupt::DMA.enable();
+}
+
+pub(crate) trait SealedWord {
+    fn width() -> vals::Wdth;
+}
+
+pub(crate) trait SealedChannel {
+    fn id(&self) -> u8;
+
+    #[inline]
+    fn tctl(&self) -> Reg<regs::Tctl, RW> {
+        pac::DMA.trig(self.id() as usize).tctl()
+    }
+
+    #[inline]
+    fn ctl(&self) -> Reg<regs::Ctl, RW> {
+        pac::DMA.chan(self.id() as usize).ctl()
+    }
+
+    #[inline]
+    fn sa(&self) -> Reg<u32, RW> {
+        pac::DMA.chan(self.id() as usize).sa()
+    }
+
+    #[inline]
+    fn da(&self) -> Reg<u32, RW> {
+        pac::DMA.chan(self.id() as usize).da()
+    }
+
+    #[inline]
+    fn sz(&self) -> Reg<regs::Sz, RW> {
+        pac::DMA.chan(self.id() as usize).sz()
+    }
+
+    #[inline]
+    fn mask_interrupt(&self, enable: bool) {
+        // Enabling interrupts is an RMW operation.
+        critical_section::with(|_cs| {
+            pac::DMA.int_event(0).imask().modify(|w| {
+                w.set_ch(self.id() as usize, enable);
+            });
+        })
+    }
+
+    /// # Safety
+    ///
+    /// - `src` must be valid for the lifetime of the transfer.
+    /// - `dst` must be valid for the lifetime of the transfer.
+    unsafe fn configure(
+        &self,
+        trigger_sel: u8,
+        src: *const u32,
+        src_wdth: Wdth,
+        dst: *const u32,
+        dst_wdth: Wdth,
+        transfer_count: u16,
+        increment_src: bool,
+        increment_dst: bool,
+        options: TransferOptions,
+    ) {
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        compiler_fence(Ordering::SeqCst);
+
+        self.ctl().modify(|w| {
+            // SLAU 5.2.5:
+            // "The DMATSEL bits should be modified only when the DMACTLx.DMAEN bit is
+            //  0; otherwise, unpredictable DMA triggers can occur."
+            //
+            // We also want to stop any transfers before setup.
+            w.set_en(false);
+            w.set_req(false);
+
+            // Not every part supports auto enable, so force its value to 0.
+            w.set_autoen(Autoen::NONE);
+            w.set_preirq(Preirq::PREIRQ_DISABLE);
+            w.set_srcwdth(src_wdth);
+            w.set_dstwdth(dst_wdth);
+            w.set_srcincr(if increment_src {
+                Incr::INCREMENT
+            } else {
+                Incr::UNCHANGED
+            });
+            w.set_dstincr(if increment_dst {
+                Incr::INCREMENT
+            } else {
+                Incr::UNCHANGED
+            });
+
+            w.set_em(Em::NORMAL);
+            // Single and block will clear the enable bit when the transfers finish.
+            w.set_tm(convert_mode(options.mode));
+        });
+
+        self.tctl().write(|w| {
+            w.set_tsel(trigger_sel);
+            // Basic channels do not implement cross triggering.
+            w.set_tint(vals::Tint::EXTERNAL);
+        });
+
+        self.sz().write(|w| {
+            w.set_size(transfer_count);
+        });
+
+        self.sa().write_value(src as u32);
+        self.da().write_value(dst as u32);
+
+        // Enable the channel.
+        self.ctl().modify(|w| {
+            // FIXME: Why did putting set_req later fix some transfers
+            w.set_en(true);
+            w.set_req(true);
+        });
+    }
+
+    fn start(&self) {
+        self.mask_interrupt(true);
+
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        compiler_fence(Ordering::SeqCst);
+
+        // Request the DMA transfer to start.
+        self.ctl().modify(|w| {
+            w.set_req(true);
+        });
+    }
+
+    fn resume(&self) {
+        self.mask_interrupt(true);
+
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        compiler_fence(Ordering::SeqCst);
+
+        self.ctl().modify(|w| {
+            // w.set_en(true);
+            w.set_req(true);
+        });
+    }
+
+    fn request_pause(&self) {
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        compiler_fence(Ordering::SeqCst);
+
+        // Stop the transfer.
+        //
+        // SLAU846 5.2.6:
+        // "A DMA block transfer in progress can be stopped by clearing the DMAEN bit"
+        self.ctl().modify(|w| {
+            // w.set_en(false);
+            w.set_req(false);
+        });
+    }
+
+    fn is_running(&self) -> bool {
+        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+        compiler_fence(Ordering::SeqCst);
+
+        let ctl = self.ctl().read();
+
+        // Is the transfer requested?
+        ctl.req()
+            // Is the channel enabled?
+            && ctl.en()
+    }
+}
+
+macro_rules! impl_dma_channel {
+    ($instance: ident, $num: expr) => {
+        impl crate::dma::SealedChannel for crate::peripherals::$instance {
+            fn id(&self) -> u8 {
+                $num
+            }
+        }
+
+        impl From<crate::peripherals::$instance> for crate::dma::AnyChannel {
+            fn from(value: crate::peripherals::$instance) -> Self {
+                use crate::dma::SealedChannel;
+
+                Self { id: value.id() }
+            }
+        }
+
+        impl crate::dma::Channel for crate::peripherals::$instance {}
+    };
+}
+
+// C1104 has no full DMA channels.
+#[allow(unused_macros)]
+macro_rules! impl_full_dma_channel {
+    ($instance: ident, $num: expr) => {
+        impl_dma_channel!($instance, $num);
+
+        impl From<crate::peripherals::$instance> for crate::dma::AnyFullChannel {
+            fn from(value: crate::peripherals::$instance) -> Self {
+                use crate::dma::SealedChannel;
+
+                Self { id: value.id() }
+            }
+        }
+
+        impl crate::dma::FullChannel for crate::peripherals::$instance {}
+    };
+}
+
+#[cfg(feature = "rt")]
+#[interrupt]
+fn DMA() {
+    use crate::BitIter;
+
+    let events = pac::DMA.int_event(0);
+    let mis = events.mis().read();
+
+    // TODO: Handle DATAERR and ADDRERR? However we do not know which channel causes an error.
+    if mis.dataerr() {
+        panic!("DMA data error");
+    } else if mis.addrerr() {
+        panic!("DMA address error")
+    }
+
+    // Ignore preirq interrupts (values greater than 16).
+    for i in BitIter(mis.0 & 0x0000_FFFF) {
+        if let Some(state) = STATE.get(i as usize) {
+            state.waker.wake();
+
+            // Notify the future that the counter size hit zero
+            events.imask().modify(|w| {
+                w.set_ch(i as usize, false);
+            });
+        }
+    }
+}
diff --git a/embassy-mspm0/src/gpio.rs b/embassy-mspm0/src/gpio.rs
index 738d51928..f77848888 100644
--- a/embassy-mspm0/src/gpio.rs
+++ b/embassy-mspm0/src/gpio.rs
@@ -223,13 +223,13 @@ impl<'d> Flex<'d> {
     /// Get whether the pin input level is high.
     #[inline]
     pub fn is_high(&self) -> bool {
-        !self.is_low()
+        self.pin.block().din31_0().read().dio(self.pin.bit_index())
     }
 
     /// Get whether the pin input level is low.
     #[inline]
     pub fn is_low(&self) -> bool {
-        self.pin.block().din31_0().read().dio(self.pin.bit_index())
+        !self.is_high()
     }
 
     /// Returns current pin level
@@ -271,22 +271,22 @@ impl<'d> Flex<'d> {
         }
     }
 
-    /// Get the current pin input level.
+    /// Get the current pin output level.
     #[inline]
     pub fn get_output_level(&self) -> Level {
-        self.is_high().into()
+        self.is_set_high().into()
     }
 
     /// Is the output level high?
     #[inline]
     pub fn is_set_high(&self) -> bool {
-        !self.is_set_low()
+        self.pin.block().dout31_0().read().dio(self.pin.bit_index())
     }
 
     /// Is the output level low?
     #[inline]
     pub fn is_set_low(&self) -> bool {
-        (self.pin.block().dout31_0().read().0 & self.pin.bit_index() as u32) == 0
+        !self.is_set_high()
     }
 
     /// Wait until the pin is high. If it is already high, return immediately.
@@ -1090,7 +1090,9 @@ pub(crate) fn init(gpio: gpio::Gpio) {
 
 #[cfg(feature = "rt")]
 fn irq_handler(gpio: gpio::Gpio, wakers: &[AtomicWaker; 32]) {
+    use crate::BitIter;
     // Only consider pins which have interrupts unmasked.
+
     let bits = gpio.cpu_int().mis().read().0;
 
     for i in BitIter(bits) {
@@ -1103,22 +1105,6 @@ fn irq_handler(gpio: gpio::Gpio, wakers: &[AtomicWaker; 32]) {
     }
 }
 
-struct BitIter(u32);
-
-impl Iterator for BitIter {
-    type Item = u32;
-
-    fn next(&mut self) -> Option<Self::Item> {
-        match self.0.trailing_zeros() {
-            32 => None,
-            b => {
-                self.0 &= !(1 << b);
-                Some(b)
-            }
-        }
-    }
-}
-
 // C110x and L110x have a dedicated interrupts just for GPIOA.
 //
 // These chips do not have a GROUP1 interrupt.
diff --git a/embassy-mspm0/src/lib.rs b/embassy-mspm0/src/lib.rs
index 7ff60e946..629ebfa1f 100644
--- a/embassy-mspm0/src/lib.rs
+++ b/embassy-mspm0/src/lib.rs
@@ -13,6 +13,7 @@ pub(crate) mod fmt;
 // This must be declared early as well for
 mod macros;
 
+pub mod dma;
 pub mod gpio;
 pub mod timer;
 pub mod uart;
@@ -59,22 +60,108 @@ pub(crate) use mspm0_metapac as pac;
 
 pub use crate::_generated::interrupt;
 
+/// Macro to bind interrupts to handlers.
+///
+/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
+/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
+/// prove at compile-time that the right interrupts have been bound.
+///
+/// Example of how to bind one interrupt:
+///
+/// ```rust,ignore
+/// use embassy_nrf::{bind_interrupts, spim, peripherals};
+///
+/// bind_interrupts!(
+///     /// Binds the SPIM3 interrupt.
+///     struct Irqs {
+///         SPIM3 => spim::InterruptHandler<peripherals::SPI3>;
+///     }
+/// );
+/// ```
+///
+/// Example of how to bind multiple interrupts in a single macro invocation:
+///
+/// ```rust,ignore
+/// use embassy_nrf::{bind_interrupts, spim, twim, peripherals};
+///
+/// bind_interrupts!(struct Irqs {
+///     SPIM3 => spim::InterruptHandler<peripherals::SPI3>;
+///     TWISPI0 => twim::InterruptHandler<peripherals::TWISPI0>;
+/// });
+/// ```
+
+// developer note: this macro can't be in `embassy-hal-internal` due to the use of `$crate`.
+#[macro_export]
+macro_rules! bind_interrupts {
+    ($(#[$attr:meta])* $vis:vis struct $name:ident {
+        $(
+            $(#[cfg($cond_irq:meta)])?
+            $irq:ident => $(
+                $(#[cfg($cond_handler:meta)])?
+                $handler:ty
+            ),*;
+        )*
+    }) => {
+        #[derive(Copy, Clone)]
+        $(#[$attr])*
+        $vis struct $name;
+
+        $(
+            #[allow(non_snake_case)]
+            #[no_mangle]
+            $(#[cfg($cond_irq)])?
+            unsafe extern "C" fn $irq() {
+                unsafe {
+                    $(
+                        $(#[cfg($cond_handler)])?
+                        <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
+
+                    )*
+                }
+            }
+
+            $(#[cfg($cond_irq)])?
+            $crate::bind_interrupts!(@inner
+                $(
+                    $(#[cfg($cond_handler)])?
+                    unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {}
+                )*
+            );
+        )*
+    };
+    (@inner $($t:tt)*) => {
+        $($t)*
+    }
+}
+
 /// `embassy-mspm0` global configuration.
 #[non_exhaustive]
 #[derive(Clone, Copy)]
 pub struct Config {
-    // TODO
+    // TODO: OSC configuration.
+    /// The size of DMA block transfer burst.
+    ///
+    /// If this is set to a value
+    pub dma_burst_size: dma::BurstSize,
+
+    /// Whether the DMA channels are used in a fixed priority or a round robin fashion.
+    ///
+    /// If [`false`], the DMA priorities are fixed.
+    ///
+    /// If [`true`], after a channel finishes a transfer it becomes the lowest priority.
+    pub dma_round_robin: bool,
 }
 
 impl Default for Config {
     fn default() -> Self {
         Self {
-            // TODO
+            dma_burst_size: dma::BurstSize::Complete,
+            dma_round_robin: false,
         }
     }
 }
 
-pub fn init(_config: Config) -> Peripherals {
+pub fn init(config: Config) -> Peripherals {
     critical_section::with(|cs| {
         let peripherals = Peripherals::take_with_cs(cs);
 
@@ -112,9 +199,33 @@ pub fn init(_config: Config) -> Peripherals {
             crate::interrupt::typelevel::GPIOA::enable();
         }
 
+        // SAFETY: Peripherals::take_with_cs will only be run once or panic.
+        unsafe { dma::init(cs, config.dma_burst_size, config.dma_round_robin) };
+
         #[cfg(feature = "_time-driver")]
         time_driver::init(cs);
 
         peripherals
     })
 }
+
+pub(crate) mod sealed {
+    #[allow(dead_code)]
+    pub trait Sealed {}
+}
+
+struct BitIter(u32);
+
+impl Iterator for BitIter {
+    type Item = u32;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        match self.0.trailing_zeros() {
+            32 => None,
+            b => {
+                self.0 &= !(1 << b);
+                Some(b)
+            }
+        }
+    }
+}
diff --git a/embassy-mspm0/src/uart/buffered.rs b/embassy-mspm0/src/uart/buffered.rs
new file mode 100644
index 000000000..cbc0b6c80
--- /dev/null
+++ b/embassy-mspm0/src/uart/buffered.rs
@@ -0,0 +1,1060 @@
+use core::future::{poll_fn, Future};
+use core::marker::PhantomData;
+use core::slice;
+use core::sync::atomic::{AtomicU8, Ordering};
+use core::task::Poll;
+
+use embassy_embedded_hal::SetConfig;
+use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
+use embassy_hal_internal::interrupt::InterruptExt;
+use embassy_sync::waitqueue::AtomicWaker;
+use embedded_hal_nb::nb;
+
+use crate::gpio::{AnyPin, SealedPin};
+use crate::interrupt::typelevel::Binding;
+use crate::pac::uart::Uart as Regs;
+use crate::uart::{Config, ConfigError, CtsPin, Error, Info, Instance, RtsPin, RxPin, State, TxPin};
+use crate::{interrupt, Peri};
+
+/// Interrupt handler.
+pub struct BufferedInterruptHandler<T: Instance> {
+    _uart: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for BufferedInterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        on_interrupt(T::info().regs, T::buffered_state())
+    }
+}
+
+/// Bidirectional buffered UART which acts as a combination of [`BufferedUartTx`] and [`BufferedUartRx`].
+pub struct BufferedUart<'d> {
+    rx: BufferedUartRx<'d>,
+    tx: BufferedUartTx<'d>,
+}
+
+impl SetConfig for BufferedUart<'_> {
+    type Config = Config;
+    type ConfigError = ConfigError;
+
+    fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
+        self.set_config(config)
+    }
+}
+
+impl<'d> BufferedUart<'d> {
+    /// Create a new bidirectional buffered UART.
+    pub fn new<T: Instance>(
+        uart: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
+        rx: Peri<'d, impl RxPin<T>>,
+        _irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
+        tx_buffer: &'d mut [u8],
+        rx_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Result<Self, ConfigError> {
+        Self::new_inner(
+            uart,
+            new_pin!(rx, config.rx_pf()),
+            new_pin!(tx, config.tx_pf()),
+            None,
+            None,
+            tx_buffer,
+            rx_buffer,
+            config,
+        )
+    }
+
+    /// Create a new bidirectional buffered UART with request-to-send and clear-to-send pins
+    pub fn new_with_rtscts<T: Instance>(
+        uart: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
+        rx: Peri<'d, impl RxPin<T>>,
+        rts: Peri<'d, impl RtsPin<T>>,
+        cts: Peri<'d, impl CtsPin<T>>,
+        _irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
+        tx_buffer: &'d mut [u8],
+        rx_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Result<Self, ConfigError> {
+        Self::new_inner(
+            uart,
+            new_pin!(rx, config.rx_pf()),
+            new_pin!(tx, config.tx_pf()),
+            new_pin!(rts, config.rts_pf()),
+            new_pin!(cts, config.cts_pf()),
+            tx_buffer,
+            rx_buffer,
+            config,
+        )
+    }
+
+    /// Reconfigure the driver
+    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
+        self.tx.set_config(config)?;
+        self.rx.set_config(config)
+    }
+
+    /// Set baudrate
+    pub fn set_baudrate(&mut self, baudrate: u32) -> Result<(), ConfigError> {
+        self.rx.set_baudrate(baudrate)
+    }
+
+    /// Write to UART TX buffer, blocking execution until done.
+    pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<usize, Error> {
+        self.tx.blocking_write(buffer)
+    }
+
+    /// Flush UART TX buffer, blocking execution until done.
+    pub fn blocking_flush(&mut self) -> Result<(), Error> {
+        self.tx.blocking_flush()
+    }
+
+    /// Check if UART is busy.
+    pub fn busy(&self) -> bool {
+        self.tx.busy()
+    }
+
+    /// Read from UART RX buffer, blocking execution until done.
+    pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
+        self.rx.blocking_read(buffer)
+    }
+
+    /// Send break character.
+    pub fn send_break(&mut self) {
+        self.tx.send_break()
+    }
+
+    /// Split into separate RX and TX handles.
+    pub fn split(self) -> (BufferedUartTx<'d>, BufferedUartRx<'d>) {
+        (self.tx, self.rx)
+    }
+
+    /// Split into separate RX and TX handles.
+    pub fn split_ref(&mut self) -> (BufferedUartTx<'_>, BufferedUartRx<'_>) {
+        (
+            BufferedUartTx {
+                info: self.tx.info,
+                state: self.tx.state,
+                tx: self.tx.tx.as_mut().map(Peri::reborrow),
+                cts: self.tx.cts.as_mut().map(Peri::reborrow),
+                reborrowed: true,
+            },
+            BufferedUartRx {
+                info: self.rx.info,
+                state: self.rx.state,
+                rx: self.rx.rx.as_mut().map(Peri::reborrow),
+                rts: self.rx.rts.as_mut().map(Peri::reborrow),
+                reborrowed: true,
+            },
+        )
+    }
+}
+
+/// Rx-only buffered UART.
+///
+/// Can be obtained from [`BufferedUart::split`], or can be constructed independently,
+/// if you do not need the transmitting half of the driver.
+pub struct BufferedUartRx<'d> {
+    info: &'static Info,
+    state: &'static BufferedState,
+    rx: Option<Peri<'d, AnyPin>>,
+    rts: Option<Peri<'d, AnyPin>>,
+    reborrowed: bool,
+}
+
+impl SetConfig for BufferedUartRx<'_> {
+    type Config = Config;
+    type ConfigError = ConfigError;
+
+    fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
+        self.set_config(config)
+    }
+}
+
+impl<'d> BufferedUartRx<'d> {
+    /// Create a new rx-only buffered UART with no hardware flow control.
+    ///
+    /// Useful if you only want Uart Rx. It saves 1 pin.
+    pub fn new<T: Instance>(
+        uart: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        _irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
+        rx_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Result<Self, ConfigError> {
+        Self::new_inner(uart, new_pin!(rx, config.rx_pf()), None, rx_buffer, config)
+    }
+
+    /// Create a new rx-only buffered UART with a request-to-send pin
+    pub fn new_with_rts<T: Instance>(
+        uart: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        rts: Peri<'d, impl RtsPin<T>>,
+        _irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
+        rx_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Result<Self, ConfigError> {
+        Self::new_inner(
+            uart,
+            new_pin!(rx, config.rx_pf()),
+            new_pin!(rts, config.rts_pf()),
+            rx_buffer,
+            config,
+        )
+    }
+
+    /// Reconfigure the driver
+    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
+        if let Some(ref rx) = self.rx {
+            rx.update_pf(config.rx_pf());
+        }
+
+        if let Some(ref rts) = self.rts {
+            rts.update_pf(config.rts_pf());
+        }
+
+        super::reconfigure(&self.info, &self.state.state, config)
+    }
+
+    /// Set baudrate
+    pub fn set_baudrate(&mut self, baudrate: u32) -> Result<(), ConfigError> {
+        super::set_baudrate(&self.info, self.state.state.clock.load(Ordering::Relaxed), baudrate)
+    }
+
+    /// Read from UART RX buffer, blocking execution until done.
+    pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
+        self.blocking_read_inner(buffer)
+    }
+}
+
+impl Drop for BufferedUartRx<'_> {
+    fn drop(&mut self) {
+        if !self.reborrowed {
+            let state = self.state;
+
+            // SAFETY: RX is being dropped (and is not reborrowed), so the ring buffer must be deinitialized
+            // in order to meet the requirements of init.
+            unsafe {
+                state.rx_buf.deinit();
+            }
+
+            // TX is inactive if the buffer is not available. If this is true, then disable the
+            // interrupt handler since we are running in RX only mode.
+            if state.tx_buf.len() == 0 {
+                self.info.interrupt.disable();
+            }
+
+            self.rx.as_ref().map(|x| x.set_as_disconnected());
+            self.rts.as_ref().map(|x| x.set_as_disconnected());
+        }
+    }
+}
+
+/// Tx-only buffered UART.
+///
+/// Can be obtained from [`BufferedUart::split`], or can be constructed independently,
+/// if you do not need the receiving half of the driver.
+pub struct BufferedUartTx<'d> {
+    info: &'static Info,
+    state: &'static BufferedState,
+    tx: Option<Peri<'d, AnyPin>>,
+    cts: Option<Peri<'d, AnyPin>>,
+    reborrowed: bool,
+}
+
+impl SetConfig for BufferedUartTx<'_> {
+    type Config = Config;
+    type ConfigError = ConfigError;
+
+    fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
+        self.set_config(config)
+    }
+}
+
+impl<'d> BufferedUartTx<'d> {
+    /// Create a new tx-only buffered UART with no hardware flow control.
+    ///
+    /// Useful if you only want Uart Tx. It saves 1 pin.
+    pub fn new<T: Instance>(
+        uart: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
+        _irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
+        tx_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Result<Self, ConfigError> {
+        Self::new_inner(uart, new_pin!(tx, config.tx_pf()), None, tx_buffer, config)
+    }
+
+    /// Create a new tx-only buffered UART with a clear-to-send pin
+    pub fn new_with_rts<T: Instance>(
+        uart: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
+        cts: Peri<'d, impl CtsPin<T>>,
+        _irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
+        tx_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Result<Self, ConfigError> {
+        Self::new_inner(
+            uart,
+            new_pin!(tx, config.tx_pf()),
+            new_pin!(cts, config.cts_pf()),
+            tx_buffer,
+            config,
+        )
+    }
+
+    /// Reconfigure the driver
+    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
+        if let Some(ref tx) = self.tx {
+            tx.update_pf(config.tx_pf());
+        }
+
+        if let Some(ref cts) = self.cts {
+            cts.update_pf(config.cts_pf());
+        }
+
+        super::reconfigure(self.info, &self.state.state, config)
+    }
+
+    /// Set baudrate
+    pub fn set_baudrate(&self, baudrate: u32) -> Result<(), ConfigError> {
+        super::set_baudrate(&self.info, self.state.state.clock.load(Ordering::Relaxed), baudrate)
+    }
+
+    /// Write to UART TX buffer, blocking execution until done.
+    pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<usize, Error> {
+        self.blocking_write_inner(buffer)
+    }
+
+    /// Flush UART TX buffer, blocking execution until done.
+    pub fn blocking_flush(&mut self) -> Result<(), Error> {
+        let state = self.state;
+
+        loop {
+            if state.tx_buf.is_empty() {
+                return Ok(());
+            }
+        }
+    }
+
+    /// Check if UART is busy.
+    pub fn busy(&self) -> bool {
+        super::busy(self.info.regs)
+    }
+
+    /// Send break character
+    pub fn send_break(&mut self) {
+        let r = self.info.regs;
+
+        r.lcrh().modify(|w| {
+            w.set_brk(true);
+        });
+    }
+}
+
+impl Drop for BufferedUartTx<'_> {
+    fn drop(&mut self) {
+        if !self.reborrowed {
+            let state = self.state;
+
+            // SAFETY: TX is being dropped (and is not reborrowed), so the ring buffer must be deinitialized
+            // in order to meet the requirements of init.
+            unsafe {
+                state.tx_buf.deinit();
+            }
+
+            // RX is inactive if the buffer is not available. If this is true, then disable the
+            // interrupt handler since we are running in TX only mode.
+            if state.rx_buf.len() == 0 {
+                self.info.interrupt.disable();
+            }
+
+            self.tx.as_ref().map(|x| x.set_as_disconnected());
+            self.cts.as_ref().map(|x| x.set_as_disconnected());
+        }
+    }
+}
+
+impl embedded_io_async::ErrorType for BufferedUart<'_> {
+    type Error = Error;
+}
+
+impl embedded_io_async::ErrorType for BufferedUartRx<'_> {
+    type Error = Error;
+}
+
+impl embedded_io_async::ErrorType for BufferedUartTx<'_> {
+    type Error = Error;
+}
+
+impl embedded_io_async::Read for BufferedUart<'_> {
+    async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
+        self.rx.read(buf).await
+    }
+}
+
+impl embedded_io_async::Read for BufferedUartRx<'_> {
+    async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
+        self.read_inner(buf).await
+    }
+}
+
+impl embedded_io_async::ReadReady for BufferedUart<'_> {
+    fn read_ready(&mut self) -> Result<bool, Self::Error> {
+        self.rx.read_ready()
+    }
+}
+
+impl embedded_io_async::ReadReady for BufferedUartRx<'_> {
+    fn read_ready(&mut self) -> Result<bool, Self::Error> {
+        self.read_ready_inner()
+    }
+}
+
+impl embedded_io_async::BufRead for BufferedUart<'_> {
+    async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
+        self.rx.fill_buf().await
+    }
+
+    fn consume(&mut self, amt: usize) {
+        self.rx.consume(amt);
+    }
+}
+
+impl embedded_io_async::BufRead for BufferedUartRx<'_> {
+    async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
+        self.fill_buf_inner().await
+    }
+
+    fn consume(&mut self, amt: usize) {
+        self.consume_inner(amt);
+    }
+}
+
+impl embedded_io_async::Write for BufferedUart<'_> {
+    async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
+        self.tx.write_inner(buf).await
+    }
+}
+
+impl embedded_io_async::Write for BufferedUartTx<'_> {
+    async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
+        self.write_inner(buf).await
+    }
+
+    async fn flush(&mut self) -> Result<(), Self::Error> {
+        self.flush_inner().await
+    }
+}
+
+impl embedded_io::Read for BufferedUart<'_> {
+    fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
+        self.rx.read(buf)
+    }
+}
+
+impl embedded_io::Read for BufferedUartRx<'_> {
+    fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
+        self.blocking_read_inner(buf)
+    }
+}
+
+impl embedded_io::Write for BufferedUart<'_> {
+    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
+        self.tx.write(buf)
+    }
+
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        self.tx.flush()
+    }
+}
+
+impl embedded_io::Write for BufferedUartTx<'_> {
+    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
+        self.blocking_write_inner(buf)
+    }
+
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        self.blocking_flush()
+    }
+}
+
+impl embedded_hal_nb::serial::Error for Error {
+    fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
+        match self {
+            Error::Framing => embedded_hal_nb::serial::ErrorKind::FrameFormat,
+            Error::Noise => embedded_hal_nb::serial::ErrorKind::Noise,
+            Error::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun,
+            Error::Parity => embedded_hal_nb::serial::ErrorKind::Parity,
+            Error::Break => embedded_hal_nb::serial::ErrorKind::Other,
+        }
+    }
+}
+
+impl embedded_hal_nb::serial::ErrorType for BufferedUart<'_> {
+    type Error = Error;
+}
+
+impl embedded_hal_nb::serial::ErrorType for BufferedUartRx<'_> {
+    type Error = Error;
+}
+
+impl embedded_hal_nb::serial::ErrorType for BufferedUartTx<'_> {
+    type Error = Error;
+}
+
+impl embedded_hal_nb::serial::Read for BufferedUart<'_> {
+    fn read(&mut self) -> nb::Result<u8, Self::Error> {
+        self.rx.read()
+    }
+}
+
+impl embedded_hal_nb::serial::Read for BufferedUartRx<'_> {
+    fn read(&mut self) -> nb::Result<u8, Self::Error> {
+        if self.info.regs.stat().read().rxfe() {
+            return Err(nb::Error::WouldBlock);
+        }
+
+        super::read_with_error(self.info.regs).map_err(nb::Error::Other)
+    }
+}
+
+impl embedded_hal_nb::serial::Write for BufferedUart<'_> {
+    fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
+        self.tx.write(word)
+    }
+
+    fn flush(&mut self) -> nb::Result<(), Self::Error> {
+        self.tx.flush()
+    }
+}
+
+impl embedded_hal_nb::serial::Write for BufferedUartTx<'_> {
+    fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
+        self.blocking_write(&[word]).map(drop).map_err(nb::Error::Other)
+    }
+
+    fn flush(&mut self) -> nb::Result<(), Self::Error> {
+        self.blocking_flush().map_err(nb::Error::Other)
+    }
+}
+
+// Impl details
+
+/// Buffered UART state.
+pub(crate) struct BufferedState {
+    /// non-buffered UART state. This is inline in order to avoid [`BufferedUartRx`]/Tx
+    /// needing to carry around a 2nd static reference and waste another 4 bytes.
+    state: State,
+    rx_waker: AtomicWaker,
+    rx_buf: RingBuffer,
+    tx_waker: AtomicWaker,
+    tx_buf: RingBuffer,
+    rx_error: AtomicU8,
+}
+
+// these must match bits 8..12 in RXDATA, but shifted by 8 to the right
+const RXE_NOISE: u8 = 16;
+const RXE_OVERRUN: u8 = 8;
+const RXE_BREAK: u8 = 4;
+const RXE_PARITY: u8 = 2;
+const RXE_FRAMING: u8 = 1;
+
+impl BufferedState {
+    pub const fn new() -> Self {
+        Self {
+            state: State::new(),
+            rx_waker: AtomicWaker::new(),
+            rx_buf: RingBuffer::new(),
+            tx_waker: AtomicWaker::new(),
+            tx_buf: RingBuffer::new(),
+            rx_error: AtomicU8::new(0),
+        }
+    }
+}
+
+impl<'d> BufferedUart<'d> {
+    fn new_inner<T: Instance>(
+        _peri: Peri<'d, T>,
+        rx: Option<Peri<'d, AnyPin>>,
+        tx: Option<Peri<'d, AnyPin>>,
+        rts: Option<Peri<'d, AnyPin>>,
+        cts: Option<Peri<'d, AnyPin>>,
+        tx_buffer: &'d mut [u8],
+        rx_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Result<Self, ConfigError> {
+        let info = T::info();
+        let state = T::buffered_state();
+
+        let mut this = Self {
+            tx: BufferedUartTx {
+                info,
+                state,
+                tx,
+                cts,
+                reborrowed: false,
+            },
+            rx: BufferedUartRx {
+                info,
+                state,
+                rx,
+                rts,
+                reborrowed: false,
+            },
+        };
+        this.enable_and_configure(tx_buffer, rx_buffer, &config)?;
+
+        Ok(this)
+    }
+
+    fn enable_and_configure(
+        &mut self,
+        tx_buffer: &'d mut [u8],
+        rx_buffer: &'d mut [u8],
+        config: &Config,
+    ) -> Result<(), ConfigError> {
+        let info = self.rx.info;
+        let state = self.rx.state;
+
+        assert!(!tx_buffer.is_empty());
+        assert!(!rx_buffer.is_empty());
+
+        init_buffers(info, state, Some(tx_buffer), Some(rx_buffer));
+        super::enable(info.regs);
+        super::configure(
+            info,
+            &state.state,
+            config,
+            true,
+            self.rx.rts.is_some(),
+            true,
+            self.tx.cts.is_some(),
+        )?;
+
+        info.interrupt.unpend();
+        unsafe { info.interrupt.enable() };
+
+        Ok(())
+    }
+}
+
+impl<'d> BufferedUartRx<'d> {
+    fn new_inner<T: Instance>(
+        _peri: Peri<'d, T>,
+        rx: Option<Peri<'d, AnyPin>>,
+        rts: Option<Peri<'d, AnyPin>>,
+        rx_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Result<Self, ConfigError> {
+        let mut this = Self {
+            info: T::info(),
+            state: T::buffered_state(),
+            rx,
+            rts,
+            reborrowed: false,
+        };
+        this.enable_and_configure(rx_buffer, &config)?;
+
+        Ok(this)
+    }
+
+    fn enable_and_configure(&mut self, rx_buffer: &'d mut [u8], config: &Config) -> Result<(), ConfigError> {
+        let info = self.info;
+        let state = self.state;
+
+        init_buffers(info, state, None, Some(rx_buffer));
+        super::enable(info.regs);
+        super::configure(info, &self.state.state, config, true, self.rts.is_some(), false, false)?;
+
+        info.interrupt.unpend();
+        unsafe { info.interrupt.enable() };
+
+        Ok(())
+    }
+
+    async fn read_inner(&self, buf: &mut [u8]) -> Result<usize, Error> {
+        poll_fn(move |cx| {
+            let state = self.state;
+
+            if let Poll::Ready(r) = self.try_read(buf) {
+                return Poll::Ready(r);
+            }
+
+            state.rx_waker.register(cx.waker());
+            Poll::Pending
+        })
+        .await
+    }
+
+    fn blocking_read_inner(&self, buffer: &mut [u8]) -> Result<usize, Error> {
+        loop {
+            match self.try_read(buffer) {
+                Poll::Ready(res) => return res,
+                Poll::Pending => continue,
+            }
+        }
+    }
+
+    fn fill_buf_inner(&self) -> impl Future<Output = Result<&'_ [u8], Error>> {
+        poll_fn(move |cx| {
+            let mut rx_reader = unsafe { self.state.rx_buf.reader() };
+            let (p, n) = rx_reader.pop_buf();
+            let result = if n == 0 {
+                match Self::get_rx_error(self.state) {
+                    None => {
+                        self.state.rx_waker.register(cx.waker());
+                        return Poll::Pending;
+                    }
+                    Some(e) => Err(e),
+                }
+            } else {
+                let buf = unsafe { slice::from_raw_parts(p, n) };
+                Ok(buf)
+            };
+
+            Poll::Ready(result)
+        })
+    }
+
+    fn consume_inner(&self, amt: usize) {
+        let mut rx_reader = unsafe { self.state.rx_buf.reader() };
+        rx_reader.pop_done(amt);
+
+        // (Re-)Enable the interrupt to receive more data in case it was
+        // disabled because the buffer was full or errors were detected.
+        self.info.regs.cpu_int(0).imask().modify(|w| {
+            w.set_rxint(true);
+            w.set_rtout(true);
+        });
+    }
+
+    /// we are ready to read if there is data in the buffer
+    fn read_ready_inner(&self) -> Result<bool, Error> {
+        Ok(!self.state.rx_buf.is_empty())
+    }
+
+    fn try_read(&self, buf: &mut [u8]) -> Poll<Result<usize, Error>> {
+        let state = self.state;
+
+        if buf.is_empty() {
+            return Poll::Ready(Ok(0));
+        }
+
+        let mut rx_reader = unsafe { state.rx_buf.reader() };
+        let n = rx_reader.pop(|data| {
+            let n = data.len().min(buf.len());
+            buf[..n].copy_from_slice(&data[..n]);
+            n
+        });
+
+        let result = if n == 0 {
+            match Self::get_rx_error(state) {
+                None => return Poll::Pending,
+                Some(e) => Err(e),
+            }
+        } else {
+            Ok(n)
+        };
+
+        // (Re-)Enable the interrupt to receive more data in case it was
+        // disabled because the buffer was full or errors were detected.
+        self.info.regs.cpu_int(0).imask().modify(|w| {
+            w.set_rxint(true);
+            w.set_rtout(true);
+        });
+
+        Poll::Ready(result)
+    }
+
+    fn get_rx_error(state: &BufferedState) -> Option<Error> {
+        // Cortex-M0 has does not support atomic swap, so we must do two operations.
+        let errs = critical_section::with(|_cs| {
+            let errs = state.rx_error.load(Ordering::Relaxed);
+            state.rx_error.store(0, Ordering::Relaxed);
+
+            errs
+        });
+
+        if errs & RXE_NOISE != 0 {
+            Some(Error::Noise)
+        } else if errs & RXE_OVERRUN != 0 {
+            Some(Error::Overrun)
+        } else if errs & RXE_BREAK != 0 {
+            Some(Error::Break)
+        } else if errs & RXE_PARITY != 0 {
+            Some(Error::Parity)
+        } else if errs & RXE_FRAMING != 0 {
+            Some(Error::Framing)
+        } else {
+            None
+        }
+    }
+}
+
+impl<'d> BufferedUartTx<'d> {
+    fn new_inner<T: Instance>(
+        _peri: Peri<'d, T>,
+        tx: Option<Peri<'d, AnyPin>>,
+        cts: Option<Peri<'d, AnyPin>>,
+        tx_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Result<Self, ConfigError> {
+        let mut this = Self {
+            info: T::info(),
+            state: T::buffered_state(),
+            tx,
+            cts,
+            reborrowed: false,
+        };
+
+        this.enable_and_configure(tx_buffer, &config)?;
+
+        Ok(this)
+    }
+
+    async fn write_inner(&self, buf: &[u8]) -> Result<usize, Error> {
+        poll_fn(move |cx| {
+            let state = self.state;
+
+            if buf.is_empty() {
+                return Poll::Ready(Ok(0));
+            }
+
+            let mut tx_writer = unsafe { state.tx_buf.writer() };
+            let n = tx_writer.push(|data| {
+                let n = data.len().min(buf.len());
+                data[..n].copy_from_slice(&buf[..n]);
+                n
+            });
+
+            if n == 0 {
+                state.tx_waker.register(cx.waker());
+                return Poll::Pending;
+            }
+
+            // The TX interrupt only triggers when the there was data in the
+            // FIFO and the number of bytes drops below a threshold. When the
+            // FIFO was empty we have to manually pend the interrupt to shovel
+            // TX data from the buffer into the FIFO.
+            self.info.interrupt.pend();
+            Poll::Ready(Ok(n))
+        })
+        .await
+    }
+
+    fn blocking_write_inner(&self, buffer: &[u8]) -> Result<usize, Error> {
+        let state = self.state;
+
+        loop {
+            let empty = state.tx_buf.is_empty();
+
+            // SAFETY: tx buf must be initialized if BufferedUartTx exists.
+            let mut tx_writer = unsafe { state.tx_buf.writer() };
+            let data = tx_writer.push_slice();
+
+            if !data.is_empty() {
+                let n = data.len().min(buffer.len());
+                data[..n].copy_from_slice(&buffer[..n]);
+                tx_writer.push_done(n);
+
+                if empty {
+                    self.info.interrupt.pend();
+                }
+
+                return Ok(n);
+            }
+        }
+    }
+
+    async fn flush_inner(&self) -> Result<(), Error> {
+        poll_fn(move |cx| {
+            let state = self.state;
+
+            if !state.tx_buf.is_empty() {
+                state.tx_waker.register(cx.waker());
+                return Poll::Pending;
+            }
+
+            Poll::Ready(Ok(()))
+        })
+        .await
+    }
+
+    fn enable_and_configure(&mut self, tx_buffer: &'d mut [u8], config: &Config) -> Result<(), ConfigError> {
+        let info = self.info;
+        let state = self.state;
+
+        init_buffers(info, state, Some(tx_buffer), None);
+        super::enable(info.regs);
+        super::configure(info, &state.state, config, false, false, true, self.cts.is_some())?;
+
+        info.interrupt.unpend();
+        unsafe { info.interrupt.enable() };
+
+        Ok(())
+    }
+}
+
+fn init_buffers<'d>(
+    info: &Info,
+    state: &BufferedState,
+    tx_buffer: Option<&'d mut [u8]>,
+    rx_buffer: Option<&'d mut [u8]>,
+) {
+    if let Some(tx_buffer) = tx_buffer {
+        let len = tx_buffer.len();
+        unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
+    }
+
+    if let Some(rx_buffer) = rx_buffer {
+        let len = rx_buffer.len();
+        unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
+    }
+
+    info.regs.cpu_int(0).imask().modify(|w| {
+        w.set_nerr(true);
+        w.set_frmerr(true);
+        w.set_parerr(true);
+        w.set_brkerr(true);
+        w.set_ovrerr(true);
+    });
+}
+
+fn on_interrupt(r: Regs, state: &'static BufferedState) {
+    let int = r.cpu_int(0).mis().read();
+
+    // Per https://github.com/embassy-rs/embassy/pull/1458, both buffered and unbuffered handlers may be bound.
+    if super::dma_enabled(r) {
+        return;
+    }
+
+    // RX
+    if state.rx_buf.is_available() {
+        // SAFETY: RX must have been initialized if RXE is set.
+        let mut rx_writer = unsafe { state.rx_buf.writer() };
+        let rx_buf = rx_writer.push_slice();
+        let mut n_read = 0;
+        let mut error = false;
+
+        for rx_byte in rx_buf {
+            let stat = r.stat().read();
+
+            if stat.rxfe() {
+                break;
+            }
+
+            let data = r.rxdata().read();
+
+            if (data.0 >> 8) != 0 {
+                // Cortex-M0 does not support atomic fetch_or, must do 2 operations.
+                critical_section::with(|_cs| {
+                    let mut value = state.rx_error.load(Ordering::Relaxed);
+                    value |= (data.0 >> 8) as u8;
+                    state.rx_error.store(value, Ordering::Relaxed);
+                });
+                error = true;
+
+                // only fill the buffer with valid characters. the current character is fine
+                // if the error is an overrun, but if we add it to the buffer we'll report
+                // the overrun one character too late. drop it instead and pretend we were
+                // a bit slower at draining the rx fifo than we actually were.
+                // this is consistent with blocking uart error reporting.
+                break;
+            }
+
+            *rx_byte = data.data();
+            n_read += 1;
+        }
+
+        if n_read > 0 {
+            rx_writer.push_done(n_read);
+            state.rx_waker.wake();
+        } else if error {
+            state.rx_waker.wake();
+        }
+
+        // Disable any further RX interrupts when the buffer becomes full or
+        // errors have occurred. This lets us buffer additional errors in the
+        // fifo without needing more error storage locations, and most applications
+        // will want to do a full reset of their uart state anyway once an error
+        // has happened.
+        if state.rx_buf.is_full() || error {
+            r.cpu_int(0).imask().modify(|w| {
+                w.set_rxint(false);
+                w.set_rtout(false);
+            });
+        }
+    }
+
+    if int.eot() {
+        r.cpu_int(0).imask().modify(|w| {
+            w.set_eot(false);
+        });
+
+        r.cpu_int(0).iclr().write(|w| {
+            w.set_eot(true);
+        });
+
+        state.tx_waker.wake();
+    }
+
+    // TX
+    if state.tx_buf.is_available() {
+        // SAFETY: TX must have been initialized if TXE is set.
+        let mut tx_reader = unsafe { state.tx_buf.reader() };
+        let buf = tx_reader.pop_slice();
+        let mut n_written = 0;
+
+        for tx_byte in buf.iter_mut() {
+            let stat = r.stat().read();
+
+            if stat.txff() {
+                break;
+            }
+
+            r.txdata().write(|w| {
+                w.set_data(*tx_byte);
+            });
+            n_written += 1;
+        }
+
+        if n_written > 0 {
+            // EOT will wake.
+            r.cpu_int(0).imask().modify(|w| {
+                w.set_eot(true);
+            });
+
+            tx_reader.pop_done(n_written);
+        }
+    }
+
+    // Clear TX and error interrupt flags
+    // RX interrupt flags are cleared by writing to ICLR.
+    let mis = r.cpu_int(0).mis().read();
+    r.cpu_int(0).iclr().write(|w| {
+        w.set_nerr(mis.nerr());
+        w.set_frmerr(mis.frmerr());
+        w.set_parerr(mis.parerr());
+        w.set_brkerr(mis.brkerr());
+        w.set_ovrerr(mis.ovrerr());
+    });
+
+    // Errors
+    if mis.nerr() {
+        warn!("Noise error");
+    }
+    if mis.frmerr() {
+        warn!("Framing error");
+    }
+    if mis.parerr() {
+        warn!("Parity error");
+    }
+    if mis.brkerr() {
+        warn!("Break error");
+    }
+    if mis.ovrerr() {
+        warn!("Overrun error");
+    }
+}
diff --git a/embassy-mspm0/src/uart.rs b/embassy-mspm0/src/uart/mod.rs
index bc1d2e343..6599cea06 100644
--- a/embassy-mspm0/src/uart.rs
+++ b/embassy-mspm0/src/uart/mod.rs
@@ -1,8 +1,11 @@
 #![macro_use]
 
+mod buffered;
+
 use core::marker::PhantomData;
 use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
 
+pub use buffered::*;
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::PeripheralType;
 
@@ -128,8 +131,8 @@ pub struct Config {
     // pub manchester: bool,
 
     // TODO: majority voting
-
-    // TODO: fifo level select - need power domain info in metapac
+    /// If true: the built-in FIFO is enabled.
+    pub fifo_enable: bool,
 
     // TODO: glitch suppression
     /// If true: invert TX pin signal values (V<sub>DD</sub> = 0/mark, Gnd = 1/idle).
@@ -169,6 +172,7 @@ impl Default for Config {
             msb_order: BitOrder::LsbFirst,
             loop_back_enable: false,
             // manchester: false,
+            fifo_enable: false,
             invert_tx: false,
             invert_rx: false,
             invert_rts: false,
@@ -185,7 +189,7 @@ impl Default for Config {
 ///
 /// ### Notes on [`embedded_io::Read`]
 ///
-/// `embedded_io::Read` requires guarantees that the base [`UartRx`] cannot provide.
+/// [`embedded_io::Read`] requires guarantees that the base [`UartRx`] cannot provide.
 ///
 /// See [`UartRx`] for more details, and see [`BufferedUart`] and [`RingBufferedUartRx`]
 /// as alternatives that do provide the necessary guarantees for `embedded_io::Read`.
@@ -199,8 +203,7 @@ impl<'d, M: Mode> SetConfig for Uart<'d, M> {
     type ConfigError = ConfigError;
 
     fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
-        self.tx.set_config(config)?;
-        self.rx.set_config(config)
+        self.set_config(config)
     }
 }
 
@@ -236,6 +239,12 @@ impl core::fmt::Display for Error {
 
 impl core::error::Error for Error {}
 
+impl embedded_io::Error for Error {
+    fn kind(&self) -> embedded_io::ErrorKind {
+        embedded_io::ErrorKind::Other
+    }
+}
+
 /// Rx-only UART Driver.
 ///
 /// Can be obtained from [`Uart::split`], or can be constructed independently,
@@ -260,7 +269,7 @@ impl<'d, M: Mode> SetConfig for UartRx<'d, M> {
 impl<'d> UartRx<'d, Blocking> {
     /// Create a new rx-only UART with no hardware flow control.
     ///
-    /// Useful if you only want Uart Rx. It saves 1 pin .
+    /// Useful if you only want Uart Rx. It saves 1 pin.
     pub fn new_blocking<T: Instance>(
         peri: Peri<'d, T>,
         rx: Peri<'d, impl RxPin<T>>,
@@ -286,19 +295,6 @@ impl<'d> UartRx<'d, Blocking> {
 }
 
 impl<'d, M: Mode> UartRx<'d, M> {
-    /// Reconfigure the driver
-    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
-        if let Some(ref rx) = self.rx {
-            rx.update_pf(config.rx_pf());
-        }
-
-        if let Some(ref rts) = self.rts {
-            rts.update_pf(config.rts_pf());
-        }
-
-        reconfigure(self.info, self.state, config)
-    }
-
     /// Perform a blocking read into `buffer`
     pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
         let r = self.info.regs;
@@ -315,6 +311,19 @@ impl<'d, M: Mode> UartRx<'d, M> {
         Ok(())
     }
 
+    /// Reconfigure the driver
+    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
+        if let Some(ref rx) = self.rx {
+            rx.update_pf(config.rx_pf());
+        }
+
+        if let Some(ref rts) = self.rts {
+            rts.update_pf(config.rts_pf());
+        }
+
+        reconfigure(self.info, self.state, config)
+    }
+
     /// Set baudrate
     pub fn set_baudrate(&self, baudrate: u32) -> Result<(), ConfigError> {
         set_baudrate(&self.info, self.state.clock.load(Ordering::Relaxed), baudrate)
@@ -378,19 +387,6 @@ impl<'d> UartTx<'d, Blocking> {
 }
 
 impl<'d, M: Mode> UartTx<'d, M> {
-    /// Reconfigure the driver
-    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
-        if let Some(ref tx) = self.tx {
-            tx.update_pf(config.tx_pf());
-        }
-
-        if let Some(ref cts) = self.cts {
-            cts.update_pf(config.cts_pf());
-        }
-
-        reconfigure(self.info, self.state, config)
-    }
-
     /// Perform a blocking UART write
     pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
         let r = self.info.regs;
@@ -427,6 +423,24 @@ impl<'d, M: Mode> UartTx<'d, M> {
         });
     }
 
+    /// Check if UART is busy.
+    pub fn busy(&self) -> bool {
+        busy(self.info.regs)
+    }
+
+    /// Reconfigure the driver
+    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
+        if let Some(ref tx) = self.tx {
+            tx.update_pf(config.tx_pf());
+        }
+
+        if let Some(ref cts) = self.cts {
+            cts.update_pf(config.cts_pf());
+        }
+
+        reconfigure(self.info, self.state, config)
+    }
+
     /// Set baudrate
     pub fn set_baudrate(&self, baudrate: u32) -> Result<(), ConfigError> {
         set_baudrate(&self.info, self.state.clock.load(Ordering::Relaxed), baudrate)
@@ -489,6 +503,11 @@ impl<'d, M: Mode> Uart<'d, M> {
         self.tx.blocking_flush()
     }
 
+    /// Check if UART is busy.
+    pub fn busy(&self) -> bool {
+        self.tx.busy()
+    }
+
     /// Perform a blocking read into `buffer`
     pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
         self.rx.blocking_read(buffer)
@@ -508,6 +527,12 @@ impl<'d, M: Mode> Uart<'d, M> {
         (&mut self.tx, &mut self.rx)
     }
 
+    /// Reconfigure the driver
+    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
+        self.tx.set_config(config)?;
+        self.rx.set_config(config)
+    }
+
     /// Send break character
     pub fn send_break(&self) {
         self.tx.send_break();
@@ -557,8 +582,16 @@ pub(crate) struct Info {
 }
 
 pub(crate) struct State {
-    /// The clock rate of the UART. This might be configured.
-    pub(crate) clock: AtomicU32,
+    /// The clock rate of the UART in Hz.
+    clock: AtomicU32,
+}
+
+impl State {
+    pub const fn new() -> Self {
+        Self {
+            clock: AtomicU32::new(0),
+        }
+    }
 }
 
 impl<'d, M: Mode> UartRx<'d, M> {
@@ -746,7 +779,8 @@ fn configure(
 
     info.regs.ctl0().modify(|w| {
         w.set_lbe(config.loop_back_enable);
-        w.set_rxe(enable_rx);
+        // Errata UART_ERR_02, must set RXE to allow use of EOT.
+        w.set_rxe(enable_rx | enable_tx);
         w.set_txe(enable_tx);
         // RXD_OUT_EN and TXD_OUT_EN?
         w.set_menc(false);
@@ -754,13 +788,18 @@ fn configure(
         w.set_rtsen(enable_rts);
         w.set_ctsen(enable_cts);
         // oversampling is set later
-        // TODO: config
-        w.set_fen(false);
+        w.set_fen(config.fifo_enable);
         // TODO: config
         w.set_majvote(false);
         w.set_msbfirst(matches!(config.msb_order, BitOrder::MsbFirst));
     });
 
+    info.regs.ifls().modify(|w| {
+        // TODO: Need power domain info for other options.
+        w.set_txiflsel(vals::Iflssel::AT_LEAST_ONE);
+        w.set_rxiflsel(vals::Iflssel::AT_LEAST_ONE);
+    });
+
     info.regs.lcrh().modify(|w| {
         let eps = if matches!(config.parity, Parity::ParityEven) {
             vals::Eps::EVEN
@@ -1021,9 +1060,29 @@ fn read_with_error(r: Regs) -> Result<u8, Error> {
     Ok(rx.data())
 }
 
+/// This function assumes CTL0.ENABLE is set (for errata cases).
+fn busy(r: Regs) -> bool {
+    // Errata UART_ERR_08
+    if cfg!(any(
+        mspm0g151x, mspm0g351x, mspm0l110x, mspm0l130x, mspm0l134x, mspm0c110x,
+    )) {
+        let stat = r.stat().read();
+        // "Poll TXFIFO status and the CTL0.ENABLE register bit to identify BUSY status."
+        !stat.txfe()
+    } else {
+        r.stat().read().busy()
+    }
+}
+
+// TODO: Implement when dma uart is implemented.
+fn dma_enabled(_r: Regs) -> bool {
+    false
+}
+
 pub(crate) trait SealedInstance {
     fn info() -> &'static Info;
     fn state() -> &'static State;
+    fn buffered_state() -> &'static BufferedState;
 }
 
 macro_rules! impl_uart_instance {
@@ -1041,12 +1100,16 @@ macro_rules! impl_uart_instance {
             }
 
             fn state() -> &'static crate::uart::State {
-                use crate::interrupt::typelevel::Interrupt;
                 use crate::uart::State;
 
-                static STATE: State = State {
-                    clock: core::sync::atomic::AtomicU32::new(0),
-                };
+                static STATE: State = State::new();
+                &STATE
+            }
+
+            fn buffered_state() -> &'static crate::uart::BufferedState {
+                use crate::uart::BufferedState;
+
+                static STATE: BufferedState = BufferedState::new();
                 &STATE
             }
         }
diff --git a/embassy-net-adin1110/Cargo.toml b/embassy-net-adin1110/Cargo.toml
index a620928cb..9cda4dc5b 100644
--- a/embassy-net-adin1110/Cargo.toml
+++ b/embassy-net-adin1110/Cargo.toml
@@ -16,7 +16,7 @@ log = { version = "0.4", default-features = false, optional = true }
 embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
 embedded-hal-async = { version = "1.0" }
 embedded-hal-bus = { version = "0.1", features = ["async"] }
-embassy-net-driver-channel = { version = "0.3.0", path = "../embassy-net-driver-channel" }
+embassy-net-driver-channel = { version = "0.3.1", path = "../embassy-net-driver-channel" }
 embassy-time = { version = "0.4.0", path = "../embassy-time" }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
 bitfield = "0.14.0"
diff --git a/embassy-net-driver-channel/CHANGELOG.md b/embassy-net-driver-channel/CHANGELOG.md
index d7af7e55d..1189e50c3 100644
--- a/embassy-net-driver-channel/CHANGELOG.md
+++ b/embassy-net-driver-channel/CHANGELOG.md
@@ -5,7 +5,12 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## Unreleased
+<!-- next-header -->
+## Unreleased - ReleaseDate
+
+## 0.3.1 - 2025-07-16
+
+- Update `embassy-sync` to v0.7.0
 
 ## 0.3.0 - 2024-08-05
 
diff --git a/embassy-net-driver-channel/Cargo.toml b/embassy-net-driver-channel/Cargo.toml
index c16c4be74..386d492c6 100644
--- a/embassy-net-driver-channel/Cargo.toml
+++ b/embassy-net-driver-channel/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-net-driver-channel"
-version = "0.3.0"
+version = "0.3.1"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "High-level channel-based driver for the `embassy-net` async TCP/IP network stack."
diff --git a/embassy-net-driver-channel/release.toml b/embassy-net-driver-channel/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/embassy-net-driver-channel/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/embassy-net-esp-hosted/Cargo.toml b/embassy-net-esp-hosted/Cargo.toml
index dea74ed65..7ccef84e8 100644
--- a/embassy-net-esp-hosted/Cargo.toml
+++ b/embassy-net-esp-hosted/Cargo.toml
@@ -20,7 +20,7 @@ log = { version = "0.4.14", optional = true }
 embassy-time = { version = "0.4.0", path = "../embassy-time" }
 embassy-sync = { version = "0.7.0", path = "../embassy-sync"}
 embassy-futures = { version = "0.1.0", path = "../embassy-futures"}
-embassy-net-driver-channel = { version = "0.3.0", path = "../embassy-net-driver-channel"}
+embassy-net-driver-channel = { version = "0.3.1", path = "../embassy-net-driver-channel"}
 
 embedded-hal = { version = "1.0" }
 embedded-hal-async = { version = "1.0" }
diff --git a/embassy-net-nrf91/Cargo.toml b/embassy-net-nrf91/Cargo.toml
index 62813e546..f3c0a0078 100644
--- a/embassy-net-nrf91/Cargo.toml
+++ b/embassy-net-nrf91/Cargo.toml
@@ -23,7 +23,7 @@ cortex-m = "0.7.7"
 embassy-time = { version = "0.4.0", path = "../embassy-time" }
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
-embassy-net-driver-channel = { version = "0.3.0", path = "../embassy-net-driver-channel" }
+embassy-net-driver-channel = { version = "0.3.1", path = "../embassy-net-driver-channel" }
 
 heapless = "0.8"
 embedded-io = "0.6.1"
@@ -33,7 +33,7 @@ at-commands = "0.5.4"
 src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-nrf91-v$VERSION/embassy-net-nrf91/src/"
 src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-nrf91/src/"
 target = "thumbv7em-none-eabi"
-features = ["defmt"]
+features = ["defmt", "nrf-pac/nrf9160"]
 
 [package.metadata.docs.rs]
 features = ["defmt"]
diff --git a/embassy-net-nrf91/src/lib.rs b/embassy-net-nrf91/src/lib.rs
index 61fcaea1f..0bd9be0d9 100644
--- a/embassy-net-nrf91/src/lib.rs
+++ b/embassy-net-nrf91/src/lib.rs
@@ -119,14 +119,16 @@ async fn new_internal<'a>(
     let shmem_ptr = shmem.as_mut_ptr() as *mut u8;
 
     const SPU_REGION_SIZE: usize = 8192; // 8kb
-    assert!(shmem_len != 0);
+    trace!("  shmem_ptr = {}, shmem_len = {}", shmem_ptr, shmem_len);
+
+    assert!(shmem_len != 0, "shmem length must not be zero");
     assert!(
         shmem_len % SPU_REGION_SIZE == 0,
         "shmem length must be a multiple of 8kb"
     );
     assert!(
         (shmem_ptr as usize) % SPU_REGION_SIZE == 0,
-        "shmem length must be a multiple of 8kb"
+        "shmem pointer must be 8kb-aligned"
     );
     assert!(
         (shmem_ptr as usize + shmem_len) < 0x2002_0000,
@@ -135,8 +137,15 @@ async fn new_internal<'a>(
 
     let spu = pac::SPU_S;
     debug!("Setting IPC RAM as nonsecure...");
+    trace!(
+        "  SPU_REGION_SIZE={}, shmem_ptr=0x{:08X}, shmem_len={}",
+        SPU_REGION_SIZE,
+        shmem_ptr as usize,
+        shmem_len
+    );
     let region_start = (shmem_ptr as usize - 0x2000_0000) / SPU_REGION_SIZE;
     let region_end = region_start + shmem_len / SPU_REGION_SIZE;
+    trace!("  region_start={}, region_end={}", region_start, region_end);
     for i in region_start..region_end {
         spu.ramregion(i).perm().write(|w| {
             w.set_execute(true);
@@ -154,13 +163,18 @@ async fn new_internal<'a>(
         end: unsafe { shmem_ptr.add(shmem_len) },
         _phantom: PhantomData,
     };
-
-    let ipc = pac::IPC_NS;
-    let power = pac::POWER_S;
+    trace!(
+        "  Allocator: start=0x{:08X}, end=0x{:08X}",
+        alloc.start as usize,
+        alloc.end as usize
+    );
 
     let cb: &mut ControlBlock = alloc.alloc().write(unsafe { mem::zeroed() });
+
     let rx = alloc.alloc_bytes(RX_SIZE);
+    trace!("  RX buffer at {}, size={}", rx.as_ptr(), RX_SIZE);
     let trace = alloc.alloc_bytes(TRACE_SIZE);
+    trace!("  Trace buffer at {}, size={}", trace.as_ptr(), TRACE_SIZE);
 
     cb.version = 0x00010000;
     cb.rx_base = rx.as_mut_ptr() as _;
@@ -174,8 +188,10 @@ async fn new_internal<'a>(
     cb.trace.base = trace.as_mut_ptr() as _;
     cb.trace.size = TRACE_SIZE;
 
+    let ipc = pac::IPC_NS;
     ipc.gpmem(0).write_value(cb as *mut _ as u32);
     ipc.gpmem(1).write_value(0);
+    trace!("  GPMEM[0]={:#X}, GPMEM[1]={}", cb as *mut _ as u32, 0);
 
     // connect task/event i to channel i
     for i in 0..8 {
@@ -185,8 +201,9 @@ async fn new_internal<'a>(
 
     compiler_fence(Ordering::SeqCst);
 
+    let power = pac::POWER_S;
     // POWER.LTEMODEM.STARTN = 0
-    // The reg is missing in the PAC??
+    // TODO: The reg is missing in the PAC??
     let startn = unsafe { (power.as_ptr() as *mut u32).add(0x610 / 4) };
     unsafe { startn.write_volatile(0) }
 
@@ -202,6 +219,8 @@ async fn new_internal<'a>(
 
         rx_control_list: ptr::null_mut(),
         rx_data_list: ptr::null_mut(),
+        rx_control_len: 0,
+        rx_data_len: 0,
         rx_seq_no: 0,
         rx_check: PointerChecker {
             start: rx.as_mut_ptr() as *mut u8,
@@ -310,6 +329,10 @@ struct StateInner {
 
     rx_control_list: *mut List,
     rx_data_list: *mut List,
+    /// Number of entries in the control list
+    rx_control_len: usize,
+    /// Number of entries in the data list
+    rx_data_len: usize,
     rx_seq_no: u16,
     rx_check: PointerChecker,
 
@@ -346,8 +369,11 @@ impl StateInner {
                 self.rx_data_list = desc.data_list_ptr;
                 let rx_control_len = unsafe { addr_of!((*self.rx_control_list).len).read_volatile() };
                 let rx_data_len = unsafe { addr_of!((*self.rx_data_list).len).read_volatile() };
-                assert_eq!(rx_control_len, LIST_LEN);
-                assert_eq!(rx_data_len, LIST_LEN);
+
+                trace!("modem control list length: {}", rx_control_len);
+                trace!("modem data    list length: {}", rx_data_len);
+                self.rx_control_len = rx_control_len;
+                self.rx_data_len = rx_data_len;
                 self.init = true;
 
                 debug!("IPC initialized OK!");
@@ -463,7 +489,12 @@ impl StateInner {
 
     fn process(&mut self, list: *mut List, is_control: bool, ch: &mut ch::Runner<MTU>) -> bool {
         let mut did_work = false;
-        for i in 0..LIST_LEN {
+        let max = if is_control {
+            self.rx_control_len
+        } else {
+            self.rx_data_len
+        };
+        for i in 0..max {
             let item_ptr = unsafe { addr_of_mut!((*list).items[i]) };
             let preamble = unsafe { addr_of!((*item_ptr).state).read_volatile() };
             if preamble & 0xFF == 0x01 && preamble >> 16 == self.rx_seq_no as u32 {
@@ -947,7 +978,7 @@ impl<'a> Runner<'a> {
     }
 }
 
-const LIST_LEN: usize = 16;
+const LIST_LEN: usize = 32;
 
 #[repr(C)]
 struct ControlBlock {
diff --git a/embassy-net-ppp/Cargo.toml b/embassy-net-ppp/Cargo.toml
index 0936626eb..b724401c9 100644
--- a/embassy-net-ppp/Cargo.toml
+++ b/embassy-net-ppp/Cargo.toml
@@ -18,7 +18,7 @@ defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.14", optional = true }
 
 embedded-io-async = { version = "0.6.1" }
-embassy-net-driver-channel = { version = "0.3.0", path = "../embassy-net-driver-channel" }
+embassy-net-driver-channel = { version = "0.3.1", path = "../embassy-net-driver-channel" }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
 ppproto = { version = "0.2.1"}
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
diff --git a/embassy-net-wiznet/Cargo.toml b/embassy-net-wiznet/Cargo.toml
index a06a09302..3ff01f72b 100644
--- a/embassy-net-wiznet/Cargo.toml
+++ b/embassy-net-wiznet/Cargo.toml
@@ -12,7 +12,7 @@ documentation = "https://docs.embassy.dev/embassy-net-wiznet"
 [dependencies]
 embedded-hal = { version = "1.0" }
 embedded-hal-async = { version = "1.0" }
-embassy-net-driver-channel = { version = "0.3.0", path = "../embassy-net-driver-channel" }
+embassy-net-driver-channel = { version = "0.3.1", path = "../embassy-net-driver-channel" }
 embassy-time = { version = "0.4.0", path = "../embassy-time" }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
 defmt = { version = "1.0.1", optional = true }
diff --git a/embassy-net/src/udp.rs b/embassy-net/src/udp.rs
index 63c2f4c75..482eb0e56 100644
--- a/embassy-net/src/udp.rs
+++ b/embassy-net/src/udp.rs
@@ -172,7 +172,7 @@ impl<'a> UdpSocket<'a> {
     /// register the current task to be notified when a datagram is received.
     ///
     /// When a datagram is received, this method will call the provided function
-    /// with the number of bytes received and the remote endpoint and return
+    /// with a reference to the received bytes and the remote endpoint and return
     /// `Poll::Ready` with the function's returned value.
     pub async fn recv_from_with<F, R>(&mut self, f: F) -> R
     where
diff --git a/embassy-nrf/CHANGELOG.md b/embassy-nrf/CHANGELOG.md
index ffa7997f7..a4cb8ceaf 100644
--- a/embassy-nrf/CHANGELOG.md
+++ b/embassy-nrf/CHANGELOG.md
@@ -5,7 +5,27 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## Unreleased
+<!-- next-header -->
+## Unreleased - ReleaseDate
+
+## 0.5.0 - 2025-07-16
+
+- changed: update to latest embassy-usb-driver
+
+## 0.4.1 - 2025-07-14
+
+- changed: nrf52833: configure internal LDO
+- changed: nrf5340: add more options to clock config
+- bugfix: clean the SAADC's register while dropping
+- changed: Remove Peripheral trait, rename PeripheralRef->Peri.
+- changed: take pins before interrupts in buffered uart init
+- changed: nrf5340: add wdt support
+- changed: remove nrf radio BLE
+- changed: add Blocking/Async Mode param.
+- bugfix: fix PWM loop count
+- bugfix: fixing the nrf54l drive configuration bug
+- changed: add temp driver for nrf5340
+- changed: add support for rand 0.9
 
 ## 0.3.1 - 2025-01-09
 
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index 47eb92697..8fa20580d 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-nrf"
-version = "0.3.1"
+version = "0.5.0"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "Embassy Hardware Abstraction Layer (HAL) for nRF series microcontrollers"
@@ -144,9 +144,9 @@ embassy-time-driver = { version = "0.2", path = "../embassy-time-driver", option
 embassy-time-queue-utils = { version = "0.1", path = "../embassy-time-queue-utils", optional = true }
 embassy-time = { version = "0.4.0", path = "../embassy-time", optional = true }
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
-embassy-hal-internal = { version = "0.2.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-3"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../embassy-embedded-hal", default-features = false }
-embassy-usb-driver = { version = "0.1.0", path = "../embassy-usb-driver" }
+embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-3"] }
+embassy-embedded-hal = { version = "0.3.1", path = "../embassy-embedded-hal", default-features = false }
+embassy-usb-driver = { version = "0.2.0", path = "../embassy-usb-driver" }
 
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
 embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
diff --git a/embassy-nrf/release.toml b/embassy-nrf/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/embassy-nrf/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/embassy-nrf/src/gpio.rs b/embassy-nrf/src/gpio.rs
index d02da9ac5..65f2d99f7 100644
--- a/embassy-nrf/src/gpio.rs
+++ b/embassy-nrf/src/gpio.rs
@@ -292,7 +292,7 @@ pub(crate) fn convert_drive(w: &mut pac::gpio::regs::PinCnf, drive: OutputDrive)
         }
 
         w.set_drive0(convert(drive.low));
-        w.set_drive0(convert(drive.high));
+        w.set_drive1(convert(drive.high));
     }
 }
 
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 9d44ae7e6..ba8206d13 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -240,11 +240,13 @@ macro_rules! bind_interrupts {
             #[no_mangle]
             $(#[cfg($cond_irq)])?
             unsafe extern "C" fn $irq() {
-                $(
-                    $(#[cfg($cond_handler)])?
-                    <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
+                unsafe {
+                    $(
+                        $(#[cfg($cond_handler)])?
+                        <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
 
-                )*
+                    )*
+                }
             }
 
             $(#[cfg($cond_irq)])?
@@ -584,8 +586,12 @@ pub mod config {
 #[allow(unused)]
 mod consts {
     pub const UICR_APPROTECT: *mut u32 = 0x00FF8000 as *mut u32;
+    pub const UICR_HFXOSRC: *mut u32 = 0x00FF801C as *mut u32;
+    pub const UICR_HFXOCNT: *mut u32 = 0x00FF8020 as *mut u32;
     pub const UICR_SECUREAPPROTECT: *mut u32 = 0x00FF802C as *mut u32;
     pub const APPROTECT_ENABLED: u32 = 0x0000_0000;
+    #[cfg(feature = "_nrf9120")]
+    pub const APPROTECT_DISABLED: u32 = 0x50FA50FA;
 }
 
 #[cfg(feature = "_nrf5340-app")]
@@ -648,13 +654,18 @@ unsafe fn uicr_write_masked(address: *mut u32, value: u32, mask: u32) -> WriteRe
         return WriteResult::Failed;
     }
 
-    let nvmc = pac::NVMC;
-    nvmc.config().write(|w| w.set_wen(pac::nvmc::vals::Wen::WEN));
-    while !nvmc.ready().read().ready() {}
-    address.write_volatile(value | !mask);
-    while !nvmc.ready().read().ready() {}
-    nvmc.config().write(|_| {});
-    while !nvmc.ready().read().ready() {}
+    // Nrf9151 errata 7, need to disable interrups + use DSB https://docs.nordicsemi.com/bundle/errata_nRF9151_Rev2/page/ERR/nRF9151/Rev2/latest/anomaly_151_7.html
+    cortex_m::interrupt::free(|_cs| {
+        let nvmc = pac::NVMC;
+
+        nvmc.config().write(|w| w.set_wen(pac::nvmc::vals::Wen::WEN));
+        while !nvmc.ready().read().ready() {}
+        address.write_volatile(value | !mask);
+        cortex_m::asm::dsb();
+        while !nvmc.ready().read().ready() {}
+        nvmc.config().write(|_| {});
+        while !nvmc.ready().read().ready() {}
+    });
 
     WriteResult::Written
 }
@@ -672,6 +683,28 @@ pub fn init(config: config::Config) -> Peripherals {
     #[allow(unused_mut)]
     let mut needs_reset = false;
 
+    // Workaround used in the nrf mdk: file system_nrf91.c , function SystemInit(), after `#if !defined(NRF_SKIP_UICR_HFXO_WORKAROUND)`
+    #[cfg(all(feature = "_nrf91", feature = "_s"))]
+    {
+        let uicr = pac::UICR_S;
+        let hfxocnt = uicr.hfxocnt().read().hfxocnt().to_bits();
+        let hfxosrc = uicr.hfxosrc().read().hfxosrc().to_bits();
+
+        if hfxosrc == 1 {
+            unsafe {
+                let _ = uicr_write(consts::UICR_HFXOSRC, 0);
+            }
+            needs_reset = true;
+        }
+
+        if hfxocnt == 255 {
+            unsafe {
+                let _ = uicr_write(consts::UICR_HFXOCNT, 32);
+            }
+            needs_reset = true;
+        }
+    }
+
     // Setup debug protection.
     #[cfg(not(feature = "_nrf51"))]
     match config.debug {
@@ -768,6 +801,28 @@ pub fn init(config: config::Config) -> Peripherals {
             }
 
             // nothing to do on the nrf9160, debug is allowed by default.
+
+            // nrf9151, nrf9161 use the new-style approtect that requires writing a register.
+            #[cfg(feature = "nrf9120-s")]
+            unsafe {
+                let p = pac::APPROTECT_S;
+
+                let res = uicr_write(consts::UICR_APPROTECT, consts::APPROTECT_DISABLED);
+                needs_reset |= res == WriteResult::Written;
+                p.approtect()
+                    .disable()
+                    .write(|w| w.set_disable(pac::approtect::vals::ApprotectDisableDisable::SW_UNPROTECTED));
+
+                let res = uicr_write(consts::UICR_SECUREAPPROTECT, consts::APPROTECT_DISABLED);
+                needs_reset |= res == WriteResult::Written;
+                p.secureapprotect()
+                    .disable()
+                    .write(|w| w.set_disable(pac::approtect::vals::SecureapprotectDisableDisable::SW_UNPROTECTED));
+
+                // TODO: maybe add workaround for this errata
+                // It uses extra power, not sure how to let the user choose.
+                // https://docs.nordicsemi.com/bundle/errata_nRF9151_Rev1/page/ERR/nRF9151/Rev1/latest/anomaly_151_36.html#anomaly_151_36
+            }
         }
         config::Debug::Disallowed => {
             // TODO: Handle nRF54L
@@ -783,6 +838,13 @@ pub fn init(config: config::Config) -> Peripherals {
                     let res = uicr_write(consts::UICR_SECUREAPPROTECT, consts::APPROTECT_ENABLED);
                     needs_reset |= res == WriteResult::Written;
                 }
+
+                #[cfg(feature = "nrf9120-s")]
+                {
+                    let p = pac::APPROTECT_S;
+                    p.approtect().forceprotect().write(|w| w.set_forceprotect(true));
+                    p.secureapprotect().forceprotect().write(|w| w.set_forceprotect(true));
+                }
             }
         }
         config::Debug::NotConfigured => {}
diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs
index a2e153e26..3d76272ac 100644
--- a/embassy-nrf/src/pwm.rs
+++ b/embassy-nrf/src/pwm.rs
@@ -479,9 +479,8 @@ impl<'d, 's, T: Instance> Sequencer<'d, 's, T> {
         let seqstart_index = if start_seq == StartSequence::One { 1 } else { 0 };
 
         match times {
-            // just the one time, no loop count
-            SequenceMode::Loop(_) => {
-                r.loop_().write(|w| w.set_cnt(vals::LoopCnt::DISABLED));
+            SequenceMode::Loop(n) => {
+                r.loop_().write(|w| w.set_cnt(vals::LoopCnt(n)));
             }
             // to play infinitely, repeat the sequence one time, then have loops done self trigger seq0 again
             SequenceMode::Infinite => {
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index f377df49e..927a0ac08 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -245,7 +245,7 @@ impl<'d, T: Instance> Uarte<'d, T> {
     }
 
     /// Return the endtx event for use with PPI
-    pub fn event_endtx(&self) -> Event {
+    pub fn event_endtx(&self) -> Event<'_> {
         let r = T::regs();
         Event::from_reg(r.events_endtx())
     }
diff --git a/embassy-nrf/src/usb/mod.rs b/embassy-nrf/src/usb/mod.rs
index 6cc1b0111..c6970fc0f 100644
--- a/embassy-nrf/src/usb/mod.rs
+++ b/embassy-nrf/src/usb/mod.rs
@@ -121,10 +121,11 @@ impl<'d, T: Instance, V: VbusDetect + 'd> driver::Driver<'d> for Driver<'d, T, V
     fn alloc_endpoint_in(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointIn, driver::EndpointAllocError> {
-        let index = self.alloc_in.allocate(ep_type)?;
+        let index = self.alloc_in.allocate(ep_type, ep_addr)?;
         let ep_addr = EndpointAddress::from_parts(index, Direction::In);
         Ok(Endpoint::new(EndpointInfo {
             addr: ep_addr,
@@ -137,10 +138,11 @@ impl<'d, T: Instance, V: VbusDetect + 'd> driver::Driver<'d> for Driver<'d, T, V
     fn alloc_endpoint_out(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointOut, driver::EndpointAllocError> {
-        let index = self.alloc_out.allocate(ep_type)?;
+        let index = self.alloc_out.allocate(ep_type, ep_addr)?;
         let ep_addr = EndpointAddress::from_parts(index, Direction::Out);
         Ok(Endpoint::new(EndpointInfo {
             addr: ep_addr,
@@ -734,7 +736,11 @@ impl Allocator {
         Self { used: 0 }
     }
 
-    fn allocate(&mut self, ep_type: EndpointType) -> Result<usize, driver::EndpointAllocError> {
+    fn allocate(
+        &mut self,
+        ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
+    ) -> Result<usize, driver::EndpointAllocError> {
         // Endpoint addresses are fixed in hardware:
         // - 0x80 / 0x00 - Control        EP0
         // - 0x81 / 0x01 - Bulk/Interrupt EP1
@@ -748,16 +754,37 @@ impl Allocator {
 
         // Endpoint directions are allocated individually.
 
-        let alloc_index = match ep_type {
-            EndpointType::Isochronous => 8,
-            EndpointType::Control => return Err(driver::EndpointAllocError),
-            EndpointType::Interrupt | EndpointType::Bulk => {
-                // Find rightmost zero bit in 1..=7
-                let ones = (self.used >> 1).trailing_ones() as usize;
-                if ones >= 7 {
-                    return Err(driver::EndpointAllocError);
+        let alloc_index = if let Some(addr) = ep_addr {
+            // Use the specified endpoint address
+            let requested_index = addr.index();
+            // Validate the requested index based on endpoint type
+            match ep_type {
+                EndpointType::Isochronous => {
+                    if requested_index != 8 {
+                        return Err(driver::EndpointAllocError);
+                    }
+                }
+                EndpointType::Control => return Err(driver::EndpointAllocError),
+                EndpointType::Interrupt | EndpointType::Bulk => {
+                    if requested_index < 1 || requested_index > 7 {
+                        return Err(driver::EndpointAllocError);
+                    }
+                }
+            }
+            requested_index
+        } else {
+            // Allocate any available endpoint
+            match ep_type {
+                EndpointType::Isochronous => 8,
+                EndpointType::Control => return Err(driver::EndpointAllocError),
+                EndpointType::Interrupt | EndpointType::Bulk => {
+                    // Find rightmost zero bit in 1..=7
+                    let ones = (self.used >> 1).trailing_ones() as usize;
+                    if ones >= 7 {
+                        return Err(driver::EndpointAllocError);
+                    }
+                    ones + 1
                 }
-                ones + 1
             }
         };
 
diff --git a/embassy-nxp/Cargo.toml b/embassy-nxp/Cargo.toml
index 426af06a0..14fa7201d 100644
--- a/embassy-nxp/Cargo.toml
+++ b/embassy-nxp/Cargo.toml
@@ -3,18 +3,69 @@ name = "embassy-nxp"
 version = "0.1.0"
 edition = "2021"
 
+[package.metadata.embassy_docs]
+src_base = "https://github.com/embassy-rs/embassy/blob/embassy-nxp-v$VERSION/embassy-nxp/src/"
+src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-nxp/src/"
+features = ["defmt", "unstable-pac" ] # TODO: Add time-driver-any, as both lpc55 and mimxrt1xxx use different drivers.
+
+flavors = [
+    { regex_feature = "lpc55", target = "thumbv8m.main-none-eabihf" },
+    { regex_feature = "mimxrt.*", target = "thumbv7em-none-eabihf" },
+]
+
 [dependencies]
 cortex-m = "0.7.7"
 cortex-m-rt = "0.7.0"
 critical-section = "1.1.2"
-embassy-hal-internal = { version = "0.2.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-2"] }
+embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-2"] }
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
-lpc55-pac = "0.5.0"
 defmt = { version = "1", optional = true }
+log = { version = "0.4.27", optional = true }
+embassy-time = { version = "0.4.0", path = "../embassy-time", optional = true }
+embassy-time-driver = { version = "0.2", path = "../embassy-time-driver", optional = true }
+embassy-time-queue-utils = { version = "0.1", path = "../embassy-time-queue-utils", optional = true }
+
+## Chip dependencies
+lpc55-pac = { version = "0.5.0", optional = true }
+nxp-pac = { version = "0.1.0", optional = true, git = "https://github.com/i509VCB/nxp-pac", rev = "be4dd0936c20d5897364a381b1d95a99514c1e7e" }
+
+imxrt-rt = { version = "0.1.7", optional = true, features = ["device"] }
+
+[build-dependencies]
+cfg_aliases = "0.2.1"
+nxp-pac = { version = "0.1.0", git = "https://github.com/i509VCB/nxp-pac", rev = "be4dd0936c20d5897364a381b1d95a99514c1e7e", features = ["metadata"], optional = true }
+proc-macro2 = "1.0.95"
+quote = "1.0.15"
 
 [features]
 default = ["rt"]
-rt = ["lpc55-pac/rt"]
+# Enable PACs as optional dependencies, since some chip families will use different pac crates (temporarily).
+rt = ["lpc55-pac?/rt", "nxp-pac?/rt"]
 
 ## Enable [defmt support](https://docs.rs/defmt) and enables `defmt` debug-log messages and formatting in embassy drivers.
 defmt = ["dep:defmt", "embassy-hal-internal/defmt", "embassy-sync/defmt"]
+
+log = ["dep:log"]
+
+## Use Periodic Interrupt Timer (PIT) as the time driver for `embassy-time`, with a tick rate of 1 MHz
+time-driver-pit = ["_time_driver", "embassy-time?/tick-hz-1_000_000"]
+
+## Reexport the PAC for the currently enabled chip at `embassy_nxp::pac` (unstable)
+unstable-pac = []
+# This is unstable because semver-minor (non-breaking) releases of embassy-nxp may major-bump (breaking) the PAC version.
+# If this is an issue for you, you're encouraged to directly depend on a fixed version of the PAC.
+# There are no plans to make this stable.
+
+## internal use only
+#
+# This feature is unfortunately a hack around the fact that cfg_aliases cannot apply to the buildscript
+# that creates the aliases.
+_rt1xxx = []
+
+# A timer driver is enabled.
+_time_driver = ["dep:embassy-time-driver", "dep:embassy-time-queue-utils"]
+
+#! ### Chip selection features
+lpc55 = ["dep:lpc55-pac"]
+mimxrt1011 = ["nxp-pac/mimxrt1011", "_rt1xxx", "dep:imxrt-rt"]
+mimxrt1062 = ["nxp-pac/mimxrt1062", "_rt1xxx", "dep:imxrt-rt"]
diff --git a/embassy-nxp/build.rs b/embassy-nxp/build.rs
new file mode 100644
index 000000000..f3c062c87
--- /dev/null
+++ b/embassy-nxp/build.rs
@@ -0,0 +1,138 @@
+use std::io::Write;
+use std::path::{Path, PathBuf};
+use std::process::Command;
+use std::{env, fs};
+
+use cfg_aliases::cfg_aliases;
+#[cfg(feature = "_rt1xxx")]
+use nxp_pac::metadata;
+#[allow(unused)]
+use proc_macro2::TokenStream;
+#[allow(unused)]
+use quote::quote;
+
+#[path = "./build_common.rs"]
+mod common;
+
+fn main() {
+    let mut cfgs = common::CfgSet::new();
+    common::set_target_cfgs(&mut cfgs);
+
+    let chip_name = match env::vars()
+        .map(|(a, _)| a)
+        .filter(|x| x.starts_with("CARGO_FEATURE_MIMXRT") || x.starts_with("CARGO_FEATURE_LPC"))
+        .get_one()
+    {
+        Ok(x) => x,
+        Err(GetOneError::None) => panic!("No mimxrt/lpc Cargo feature enabled"),
+        Err(GetOneError::Multiple) => panic!("Multiple mimxrt/lpc Cargo features enabled"),
+    }
+    .strip_prefix("CARGO_FEATURE_")
+    .unwrap()
+    .to_ascii_lowercase();
+
+    cfg_aliases! {
+        rt1xxx: { any(feature = "mimxrt1011", feature = "mimxrt1062") },
+        gpio1: { any(feature = "mimxrt1011", feature = "mimxrt1062") },
+        gpio2: { any(feature = "mimxrt1011", feature = "mimxrt1062") },
+        gpio3: { feature = "mimxrt1062" },
+        gpio4: { feature = "mimxrt1062" },
+        gpio5: { any(feature = "mimxrt1011", feature = "mimxrt1062") },
+    }
+
+    eprintln!("chip: {chip_name}");
+
+    generate_code();
+}
+
+#[cfg(feature = "_rt1xxx")]
+fn generate_iomuxc() -> TokenStream {
+    use proc_macro2::{Ident, Span};
+
+    let pads = metadata::iomuxc::IOMUXC_REGISTERS.iter().map(|registers| {
+        let name = Ident::new(&registers.name, Span::call_site());
+        let address = registers.pad_ctl;
+
+        quote! {
+            pub const #name: u32 = #address;
+        }
+    });
+
+    let muxes = metadata::iomuxc::IOMUXC_REGISTERS.iter().map(|registers| {
+        let name = Ident::new(&registers.name, Span::call_site());
+        let address = registers.mux_ctl;
+
+        quote! {
+            pub const #name: u32 = #address;
+        }
+    });
+
+    quote! {
+        pub mod iomuxc {
+            pub mod pads {
+                #(#pads)*
+            }
+
+            pub mod muxes {
+                #(#muxes)*
+            }
+        }
+    }
+}
+
+fn generate_code() {
+    #[allow(unused)]
+    use std::fmt::Write;
+
+    let out_dir = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    #[allow(unused_mut)]
+    let mut output = String::new();
+
+    #[cfg(feature = "_rt1xxx")]
+    writeln!(&mut output, "{}", generate_iomuxc()).unwrap();
+
+    let out_file = out_dir.join("_generated.rs").to_string_lossy().to_string();
+    fs::write(&out_file, output).unwrap();
+    rustfmt(&out_file);
+}
+
+/// rustfmt a given path.
+/// Failures are logged to stderr and ignored.
+fn rustfmt(path: impl AsRef<Path>) {
+    let path = path.as_ref();
+    match Command::new("rustfmt").args([path]).output() {
+        Err(e) => {
+            eprintln!("failed to exec rustfmt {:?}: {:?}", path, e);
+        }
+        Ok(out) => {
+            if !out.status.success() {
+                eprintln!("rustfmt {:?} failed:", path);
+                eprintln!("=== STDOUT:");
+                std::io::stderr().write_all(&out.stdout).unwrap();
+                eprintln!("=== STDERR:");
+                std::io::stderr().write_all(&out.stderr).unwrap();
+            }
+        }
+    }
+}
+
+enum GetOneError {
+    None,
+    Multiple,
+}
+
+trait IteratorExt: Iterator {
+    fn get_one(self) -> Result<Self::Item, GetOneError>;
+}
+
+impl<T: Iterator> IteratorExt for T {
+    fn get_one(mut self) -> Result<Self::Item, GetOneError> {
+        match self.next() {
+            None => Err(GetOneError::None),
+            Some(res) => match self.next() {
+                Some(_) => Err(GetOneError::Multiple),
+                None => Ok(res),
+            },
+        }
+    }
+}
diff --git a/embassy-nxp/build_common.rs b/embassy-nxp/build_common.rs
new file mode 100644
index 000000000..4f24e6d37
--- /dev/null
+++ b/embassy-nxp/build_common.rs
@@ -0,0 +1,94 @@
+// NOTE: this file is copy-pasted between several Embassy crates, because there is no
+// straightforward way to share this code:
+// - it cannot be placed into the root of the repo and linked from each build.rs using `#[path =
+// "../build_common.rs"]`, because `cargo publish` requires that all files published with a crate
+// reside in the crate's directory,
+// - it cannot be symlinked from `embassy-xxx/build_common.rs` to `../build_common.rs`, because
+// symlinks don't work on Windows.
+
+use std::collections::HashSet;
+use std::env;
+
+/// Helper for emitting cargo instruction for enabling configs (`cargo:rustc-cfg=X`) and declaring
+/// them (`cargo:rust-check-cfg=cfg(X)`).
+#[derive(Debug)]
+pub struct CfgSet {
+    enabled: HashSet<String>,
+    declared: HashSet<String>,
+}
+
+impl CfgSet {
+    pub fn new() -> Self {
+        Self {
+            enabled: HashSet::new(),
+            declared: HashSet::new(),
+        }
+    }
+
+    /// Enable a config, which can then be used in `#[cfg(...)]` for conditional compilation.
+    ///
+    /// All configs that can potentially be enabled should be unconditionally declared using
+    /// [`Self::declare()`].
+    pub fn enable(&mut self, cfg: impl AsRef<str>) {
+        if self.enabled.insert(cfg.as_ref().to_owned()) {
+            println!("cargo:rustc-cfg={}", cfg.as_ref());
+        }
+    }
+
+    pub fn enable_all(&mut self, cfgs: &[impl AsRef<str>]) {
+        for cfg in cfgs.iter() {
+            self.enable(cfg.as_ref());
+        }
+    }
+
+    /// Declare a valid config for conditional compilation, without enabling it.
+    ///
+    /// This enables rustc to check that the configs in `#[cfg(...)]` attributes are valid.
+    pub fn declare(&mut self, cfg: impl AsRef<str>) {
+        if self.declared.insert(cfg.as_ref().to_owned()) {
+            println!("cargo:rustc-check-cfg=cfg({})", cfg.as_ref());
+        }
+    }
+
+    pub fn declare_all(&mut self, cfgs: &[impl AsRef<str>]) {
+        for cfg in cfgs.iter() {
+            self.declare(cfg.as_ref());
+        }
+    }
+
+    pub fn set(&mut self, cfg: impl Into<String>, enable: bool) {
+        let cfg = cfg.into();
+        if enable {
+            self.enable(cfg.clone());
+        }
+        self.declare(cfg);
+    }
+}
+
+/// Sets configs that describe the target platform.
+pub fn set_target_cfgs(cfgs: &mut CfgSet) {
+    let target = env::var("TARGET").unwrap();
+
+    if target.starts_with("thumbv6m-") {
+        cfgs.enable_all(&["cortex_m", "armv6m"]);
+    } else if target.starts_with("thumbv7m-") {
+        cfgs.enable_all(&["cortex_m", "armv7m"]);
+    } else if target.starts_with("thumbv7em-") {
+        cfgs.enable_all(&["cortex_m", "armv7m", "armv7em"]);
+    } else if target.starts_with("thumbv8m.base") {
+        cfgs.enable_all(&["cortex_m", "armv8m", "armv8m_base"]);
+    } else if target.starts_with("thumbv8m.main") {
+        cfgs.enable_all(&["cortex_m", "armv8m", "armv8m_main"]);
+    }
+    cfgs.declare_all(&[
+        "cortex_m",
+        "armv6m",
+        "armv7m",
+        "armv7em",
+        "armv8m",
+        "armv8m_base",
+        "armv8m_main",
+    ]);
+
+    cfgs.set("has_fpu", target.ends_with("-eabihf"));
+}
diff --git a/embassy-nxp/src/chips/lpc55.rs b/embassy-nxp/src/chips/lpc55.rs
new file mode 100644
index 000000000..c95218af0
--- /dev/null
+++ b/embassy-nxp/src/chips/lpc55.rs
@@ -0,0 +1,70 @@
+pub use lpc55_pac as pac;
+
+embassy_hal_internal::peripherals! {
+    // External pins. These are not only GPIOs, they are multi-purpose pins and can be used by other
+    // peripheral types (e.g. I2C).
+    PIO0_0,
+    PIO0_1,
+    PIO0_2,
+    PIO0_3,
+    PIO0_4,
+    PIO0_5,
+    PIO0_6,
+    PIO0_7,
+    PIO0_8,
+    PIO0_9,
+    PIO0_10,
+    PIO0_11,
+    PIO0_12,
+    PIO0_13,
+    PIO0_14,
+    PIO0_15,
+    PIO0_16,
+    PIO0_17,
+    PIO0_18,
+    PIO0_19,
+    PIO0_20,
+    PIO0_21,
+    PIO0_22,
+    PIO0_23,
+    PIO0_24,
+    PIO0_25,
+    PIO0_26,
+    PIO0_27,
+    PIO0_28,
+    PIO0_29,
+    PIO0_30,
+    PIO0_31,
+    PIO1_0,
+    PIO1_1,
+    PIO1_2,
+    PIO1_3,
+    PIO1_4,
+    PIO1_5,
+    PIO1_6,
+    PIO1_7,
+    PIO1_8,
+    PIO1_9,
+    PIO1_10,
+    PIO1_11,
+    PIO1_12,
+    PIO1_13,
+    PIO1_14,
+    PIO1_15,
+    PIO1_16,
+    PIO1_17,
+    PIO1_18,
+    PIO1_19,
+    PIO1_20,
+    PIO1_21,
+    PIO1_22,
+    PIO1_23,
+    PIO1_24,
+    PIO1_25,
+    PIO1_26,
+    PIO1_27,
+    PIO1_28,
+    PIO1_29,
+    PIO1_30,
+    PIO1_31,
+}
diff --git a/embassy-nxp/src/chips/mimxrt1011.rs b/embassy-nxp/src/chips/mimxrt1011.rs
new file mode 100644
index 000000000..a74d953fc
--- /dev/null
+++ b/embassy-nxp/src/chips/mimxrt1011.rs
@@ -0,0 +1,113 @@
+// This must be imported so that __preinit is defined.
+use imxrt_rt as _;
+pub use nxp_pac as pac;
+
+embassy_hal_internal::peripherals! {
+    // External pins. These are not only GPIOs, they are multi-purpose pins and can be used by other
+    // peripheral types (e.g. I2C).
+    GPIO_00,
+    GPIO_01,
+    GPIO_02,
+    GPIO_03,
+    GPIO_04,
+    GPIO_05,
+    GPIO_06,
+    GPIO_07,
+    GPIO_08,
+    GPIO_09,
+    GPIO_10,
+    GPIO_11,
+    GPIO_12,
+    GPIO_13,
+    GPIO_AD_00,
+    GPIO_AD_01,
+    GPIO_AD_02,
+    GPIO_AD_03,
+    GPIO_AD_04,
+    GPIO_AD_05,
+    GPIO_AD_06,
+    GPIO_AD_07,
+    GPIO_AD_08,
+    GPIO_AD_09,
+    GPIO_AD_10,
+    GPIO_AD_11,
+    GPIO_AD_12,
+    GPIO_AD_13,
+    GPIO_AD_14,
+    GPIO_SD_00,
+    GPIO_SD_01,
+    GPIO_SD_02,
+    GPIO_SD_03,
+    GPIO_SD_04,
+    GPIO_SD_05,
+    GPIO_SD_06,
+    GPIO_SD_07,
+    GPIO_SD_08,
+    GPIO_SD_09,
+    GPIO_SD_10,
+    GPIO_SD_11,
+    GPIO_SD_12,
+    GPIO_SD_13,
+    PMIC_ON_REQ,
+}
+
+impl_gpio! {
+    // GPIO Bank 1
+    GPIO_00(Gpio1, 0);
+    GPIO_01(Gpio1, 1);
+    GPIO_02(Gpio1, 2);
+    GPIO_03(Gpio1, 3);
+    GPIO_04(Gpio1, 4);
+    GPIO_05(Gpio1, 5);
+    GPIO_06(Gpio1, 6);
+    GPIO_07(Gpio1, 7);
+    GPIO_08(Gpio1, 8);
+    GPIO_09(Gpio1, 9);
+    GPIO_10(Gpio1, 10);
+    GPIO_11(Gpio1, 11);
+    GPIO_12(Gpio1, 12);
+    GPIO_13(Gpio1, 13);
+    GPIO_AD_00(Gpio1, 14);
+    GPIO_AD_01(Gpio1, 15);
+    GPIO_AD_02(Gpio1, 16);
+    GPIO_AD_03(Gpio1, 17);
+    GPIO_AD_04(Gpio1, 18);
+    GPIO_AD_05(Gpio1, 19);
+    GPIO_AD_06(Gpio1, 20);
+    GPIO_AD_07(Gpio1, 21);
+    GPIO_AD_08(Gpio1, 22);
+    GPIO_AD_09(Gpio1, 23);
+    GPIO_AD_10(Gpio1, 24);
+    GPIO_AD_11(Gpio1, 25);
+    GPIO_AD_12(Gpio1, 26);
+    GPIO_AD_13(Gpio1, 27);
+    GPIO_AD_14(Gpio1, 28);
+
+    // GPIO Bank 2
+    GPIO_SD_00(Gpio2, 0);
+    GPIO_SD_01(Gpio2, 1);
+    GPIO_SD_02(Gpio2, 2);
+    GPIO_SD_03(Gpio2, 3);
+    GPIO_SD_04(Gpio2, 4);
+    GPIO_SD_05(Gpio2, 5);
+    GPIO_SD_06(Gpio2, 6);
+    GPIO_SD_07(Gpio2, 7);
+    GPIO_SD_08(Gpio2, 8);
+    GPIO_SD_09(Gpio2, 9);
+    GPIO_SD_10(Gpio2, 10);
+    GPIO_SD_11(Gpio2, 11);
+    GPIO_SD_12(Gpio2, 12);
+    GPIO_SD_13(Gpio2, 13);
+
+    // GPIO Bank 5
+    PMIC_ON_REQ(Gpio5, 0);
+}
+
+pub(crate) mod _generated {
+    #![allow(dead_code)]
+    #![allow(unused_imports)]
+    #![allow(non_snake_case)]
+    #![allow(missing_docs)]
+
+    include!(concat!(env!("OUT_DIR"), "/_generated.rs"));
+}
diff --git a/embassy-nxp/src/chips/mimxrt1062.rs b/embassy-nxp/src/chips/mimxrt1062.rs
new file mode 100644
index 000000000..ef153bd66
--- /dev/null
+++ b/embassy-nxp/src/chips/mimxrt1062.rs
@@ -0,0 +1,282 @@
+// This must be imported so that __preinit is defined.
+use imxrt_rt as _;
+pub use nxp_pac as pac;
+
+embassy_hal_internal::peripherals! {
+    // External pins. These are not only GPIOs, they are multi-purpose pins and can be used by other
+    // peripheral types (e.g. I2C).
+    GPIO_AD_B0_00,
+    GPIO_AD_B0_01,
+    GPIO_AD_B0_02,
+    GPIO_AD_B0_03,
+    GPIO_AD_B0_04,
+    GPIO_AD_B0_05,
+    GPIO_AD_B0_06,
+    GPIO_AD_B0_07,
+    GPIO_AD_B0_08,
+    GPIO_AD_B0_09,
+    GPIO_AD_B0_10,
+    GPIO_AD_B0_11,
+    GPIO_AD_B0_12,
+    GPIO_AD_B0_13,
+    GPIO_AD_B0_14,
+    GPIO_AD_B0_15,
+    GPIO_AD_B1_00,
+    GPIO_AD_B1_01,
+    GPIO_AD_B1_02,
+    GPIO_AD_B1_03,
+    GPIO_AD_B1_04,
+    GPIO_AD_B1_05,
+    GPIO_AD_B1_06,
+    GPIO_AD_B1_07,
+    GPIO_AD_B1_08,
+    GPIO_AD_B1_09,
+    GPIO_AD_B1_10,
+    GPIO_AD_B1_11,
+    GPIO_AD_B1_12,
+    GPIO_AD_B1_13,
+    GPIO_AD_B1_14,
+    GPIO_AD_B1_15,
+    GPIO_B0_00,
+    GPIO_B0_01,
+    GPIO_B0_02,
+    GPIO_B0_03,
+    GPIO_B0_04,
+    GPIO_B0_05,
+    GPIO_B0_06,
+    GPIO_B0_07,
+    GPIO_B0_08,
+    GPIO_B0_09,
+    GPIO_B0_10,
+    GPIO_B0_11,
+    GPIO_B0_12,
+    GPIO_B0_13,
+    GPIO_B0_14,
+    GPIO_B0_15,
+    GPIO_B1_00,
+    GPIO_B1_01,
+    GPIO_B1_02,
+    GPIO_B1_03,
+    GPIO_B1_04,
+    GPIO_B1_05,
+    GPIO_B1_06,
+    GPIO_B1_07,
+    GPIO_B1_08,
+    GPIO_B1_09,
+    GPIO_B1_10,
+    GPIO_B1_11,
+    GPIO_B1_12,
+    GPIO_B1_13,
+    GPIO_B1_14,
+    GPIO_B1_15,
+    GPIO_EMC_00,
+    GPIO_EMC_01,
+    GPIO_EMC_02,
+    GPIO_EMC_03,
+    GPIO_EMC_04,
+    GPIO_EMC_05,
+    GPIO_EMC_06,
+    GPIO_EMC_07,
+    GPIO_EMC_08,
+    GPIO_EMC_09,
+    GPIO_EMC_10,
+    GPIO_EMC_11,
+    GPIO_EMC_12,
+    GPIO_EMC_13,
+    GPIO_EMC_14,
+    GPIO_EMC_15,
+    GPIO_EMC_16,
+    GPIO_EMC_17,
+    GPIO_EMC_18,
+    GPIO_EMC_19,
+    GPIO_EMC_20,
+    GPIO_EMC_21,
+    GPIO_EMC_22,
+    GPIO_EMC_23,
+    GPIO_EMC_24,
+    GPIO_EMC_25,
+    GPIO_EMC_26,
+    GPIO_EMC_27,
+    GPIO_EMC_28,
+    GPIO_EMC_29,
+    GPIO_EMC_30,
+    GPIO_EMC_31,
+    GPIO_EMC_32,
+    GPIO_EMC_33,
+    GPIO_EMC_34,
+    GPIO_EMC_35,
+    GPIO_EMC_36,
+    GPIO_EMC_37,
+    GPIO_EMC_38,
+    GPIO_EMC_39,
+    GPIO_EMC_40,
+    GPIO_EMC_41,
+    GPIO_SD_B0_00,
+    GPIO_SD_B0_01,
+    GPIO_SD_B0_02,
+    GPIO_SD_B0_03,
+    GPIO_SD_B0_04,
+    GPIO_SD_B0_05,
+    GPIO_SD_B1_00,
+    GPIO_SD_B1_01,
+    GPIO_SD_B1_02,
+    GPIO_SD_B1_03,
+    GPIO_SD_B1_04,
+    GPIO_SD_B1_05,
+    GPIO_SD_B1_06,
+    GPIO_SD_B1_07,
+    GPIO_SD_B1_08,
+    GPIO_SD_B1_09,
+    GPIO_SD_B1_10,
+    GPIO_SD_B1_11,
+    WAKEUP,
+    PMIC_ON_REQ,
+    PMIC_STBY_REQ,
+}
+
+impl_gpio! {
+    // GPIO Bank 1
+    GPIO_AD_B0_00(Gpio1, 0);
+    GPIO_AD_B0_01(Gpio1, 1);
+    GPIO_AD_B0_02(Gpio1, 2);
+    GPIO_AD_B0_03(Gpio1, 3);
+    GPIO_AD_B0_04(Gpio1, 4);
+    GPIO_AD_B0_05(Gpio1, 5);
+    GPIO_AD_B0_06(Gpio1, 6);
+    GPIO_AD_B0_07(Gpio1, 7);
+    GPIO_AD_B0_08(Gpio1, 8);
+    GPIO_AD_B0_09(Gpio1, 9);
+    GPIO_AD_B0_10(Gpio1, 10);
+    GPIO_AD_B0_11(Gpio1, 11);
+    GPIO_AD_B0_12(Gpio1, 12);
+    GPIO_AD_B0_13(Gpio1, 13);
+    GPIO_AD_B0_14(Gpio1, 14);
+    GPIO_AD_B0_15(Gpio1, 15);
+    GPIO_AD_B1_00(Gpio1, 16);
+    GPIO_AD_B1_01(Gpio1, 17);
+    GPIO_AD_B1_02(Gpio1, 18);
+    GPIO_AD_B1_03(Gpio1, 19);
+    GPIO_AD_B1_04(Gpio1, 20);
+    GPIO_AD_B1_05(Gpio1, 21);
+    GPIO_AD_B1_06(Gpio1, 22);
+    GPIO_AD_B1_07(Gpio1, 23);
+    GPIO_AD_B1_08(Gpio1, 24);
+    GPIO_AD_B1_09(Gpio1, 25);
+    GPIO_AD_B1_10(Gpio1, 26);
+    GPIO_AD_B1_11(Gpio1, 27);
+    GPIO_AD_B1_12(Gpio1, 28);
+    GPIO_AD_B1_13(Gpio1, 29);
+    GPIO_AD_B1_14(Gpio1, 30);
+    GPIO_AD_B1_15(Gpio1, 31);
+
+    // GPIO Bank 2
+    GPIO_B0_00(Gpio2, 0);
+    GPIO_B0_01(Gpio2, 1);
+    GPIO_B0_02(Gpio2, 2);
+    GPIO_B0_03(Gpio2, 3);
+    GPIO_B0_04(Gpio2, 4);
+    GPIO_B0_05(Gpio2, 5);
+    GPIO_B0_06(Gpio2, 6);
+    GPIO_B0_07(Gpio2, 7);
+    GPIO_B0_08(Gpio2, 8);
+    GPIO_B0_09(Gpio2, 9);
+    GPIO_B0_10(Gpio2, 10);
+    GPIO_B0_11(Gpio2, 11);
+    GPIO_B0_12(Gpio2, 12);
+    GPIO_B0_13(Gpio2, 13);
+    GPIO_B0_14(Gpio2, 14);
+    GPIO_B0_15(Gpio2, 15);
+    GPIO_B1_00(Gpio2, 16);
+    GPIO_B1_01(Gpio2, 17);
+    GPIO_B1_02(Gpio2, 18);
+    GPIO_B1_03(Gpio2, 19);
+    GPIO_B1_04(Gpio2, 20);
+    GPIO_B1_05(Gpio2, 21);
+    GPIO_B1_06(Gpio2, 22);
+    GPIO_B1_07(Gpio2, 23);
+    GPIO_B1_08(Gpio2, 24);
+    GPIO_B1_09(Gpio2, 25);
+    GPIO_B1_10(Gpio2, 26);
+    GPIO_B1_11(Gpio2, 27);
+    GPIO_B1_12(Gpio2, 28);
+    GPIO_B1_13(Gpio2, 29);
+    GPIO_B1_14(Gpio2, 30);
+    GPIO_B1_15(Gpio2, 31);
+
+    // GPIO Bank 4 (EMC is 4, then 3)
+    GPIO_EMC_00(Gpio4, 0);
+    GPIO_EMC_01(Gpio4, 1);
+    GPIO_EMC_02(Gpio4, 2);
+    GPIO_EMC_03(Gpio4, 3);
+    GPIO_EMC_04(Gpio4, 4);
+    GPIO_EMC_05(Gpio4, 5);
+    GPIO_EMC_06(Gpio4, 6);
+    GPIO_EMC_07(Gpio4, 7);
+    GPIO_EMC_08(Gpio4, 8);
+    GPIO_EMC_09(Gpio4, 9);
+    GPIO_EMC_10(Gpio4, 10);
+    GPIO_EMC_11(Gpio4, 11);
+    GPIO_EMC_12(Gpio4, 12);
+    GPIO_EMC_13(Gpio4, 13);
+    GPIO_EMC_14(Gpio4, 14);
+    GPIO_EMC_15(Gpio4, 15);
+    GPIO_EMC_16(Gpio4, 16);
+    GPIO_EMC_17(Gpio4, 17);
+    GPIO_EMC_18(Gpio4, 18);
+    GPIO_EMC_19(Gpio4, 19);
+    GPIO_EMC_20(Gpio4, 20);
+    GPIO_EMC_21(Gpio4, 21);
+    GPIO_EMC_22(Gpio4, 22);
+    GPIO_EMC_23(Gpio4, 23);
+    GPIO_EMC_24(Gpio4, 24);
+    GPIO_EMC_25(Gpio4, 25);
+    GPIO_EMC_26(Gpio4, 26);
+    GPIO_EMC_27(Gpio4, 27);
+    GPIO_EMC_28(Gpio4, 28);
+    GPIO_EMC_29(Gpio4, 29);
+    GPIO_EMC_30(Gpio4, 30);
+    GPIO_EMC_31(Gpio4, 31);
+
+    // GPIO Bank 3
+    GPIO_EMC_32(Gpio3, 18);
+    GPIO_EMC_33(Gpio3, 19);
+    GPIO_EMC_34(Gpio3, 20);
+    GPIO_EMC_35(Gpio3, 21);
+    GPIO_EMC_36(Gpio3, 22);
+    GPIO_EMC_37(Gpio3, 23);
+    GPIO_EMC_38(Gpio3, 24);
+    GPIO_EMC_39(Gpio3, 25);
+    GPIO_EMC_40(Gpio3, 26);
+    GPIO_EMC_41(Gpio3, 27);
+    GPIO_SD_B0_00(Gpio3, 12);
+    GPIO_SD_B0_01(Gpio3, 13);
+    GPIO_SD_B0_02(Gpio3, 14);
+    GPIO_SD_B0_03(Gpio3, 15);
+    GPIO_SD_B0_04(Gpio3, 16);
+    GPIO_SD_B0_05(Gpio3, 17);
+    GPIO_SD_B1_00(Gpio3, 0);
+    GPIO_SD_B1_01(Gpio3, 1);
+    GPIO_SD_B1_02(Gpio3, 2);
+    GPIO_SD_B1_03(Gpio3, 3);
+    GPIO_SD_B1_04(Gpio3, 4);
+    GPIO_SD_B1_05(Gpio3, 5);
+    GPIO_SD_B1_06(Gpio3, 6);
+    GPIO_SD_B1_07(Gpio3, 7);
+    GPIO_SD_B1_08(Gpio3, 8);
+    GPIO_SD_B1_09(Gpio3, 9);
+    GPIO_SD_B1_10(Gpio3, 10);
+    GPIO_SD_B1_11(Gpio3, 11);
+
+    WAKEUP(Gpio5, 0);
+    PMIC_ON_REQ(Gpio5, 1);
+    PMIC_STBY_REQ(Gpio5, 2);
+}
+
+pub(crate) mod _generated {
+    #![allow(dead_code)]
+    #![allow(unused_imports)]
+    #![allow(non_snake_case)]
+    #![allow(missing_docs)]
+
+    include!(concat!(env!("OUT_DIR"), "/_generated.rs"));
+}
diff --git a/embassy-nxp/src/fmt.rs b/embassy-nxp/src/fmt.rs
new file mode 100644
index 000000000..27d41ace6
--- /dev/null
+++ b/embassy-nxp/src/fmt.rs
@@ -0,0 +1,284 @@
+//! Copied from embassy-rp
+
+#![macro_use]
+#![allow(unused)]
+
+use core::fmt::{Debug, Display, LowerHex};
+
+#[cfg(all(feature = "defmt", feature = "log"))]
+compile_error!("You may not enable both `defmt` and `log` features.");
+
+#[collapse_debuginfo(yes)]
+macro_rules! assert {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::assert!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::assert!($($x)*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! assert_eq {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::assert_eq!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::assert_eq!($($x)*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! assert_ne {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::assert_ne!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::assert_ne!($($x)*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! debug_assert {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::debug_assert!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug_assert!($($x)*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! debug_assert_eq {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::debug_assert_eq!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug_assert_eq!($($x)*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! debug_assert_ne {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::debug_assert_ne!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug_assert_ne!($($x)*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! todo {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::todo!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::todo!($($x)*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! unreachable {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::unreachable!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::unreachable!($($x)*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! unimplemented {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::unimplemented!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::unimplemented!($($x)*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! panic {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "defmt"))]
+            ::core::panic!($($x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::panic!($($x)*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! trace {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::trace!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::trace!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! debug {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::debug!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::debug!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! info {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::info!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::info!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! warn {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::warn!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::warn!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+#[collapse_debuginfo(yes)]
+macro_rules! error {
+    ($s:literal $(, $x:expr)* $(,)?) => {
+        {
+            #[cfg(feature = "log")]
+            ::log::error!($s $(, $x)*);
+            #[cfg(feature = "defmt")]
+            ::defmt::error!($s $(, $x)*);
+            #[cfg(not(any(feature = "log", feature="defmt")))]
+            let _ = ($( & $x ),*);
+        }
+    };
+}
+
+#[cfg(feature = "defmt")]
+#[collapse_debuginfo(yes)]
+macro_rules! unwrap {
+    ($($x:tt)*) => {
+        ::defmt::unwrap!($($x)*)
+    };
+}
+
+#[cfg(not(feature = "defmt"))]
+#[collapse_debuginfo(yes)]
+macro_rules! unwrap {
+    ($arg:expr) => {
+        match $crate::fmt::Try::into_result($arg) {
+            ::core::result::Result::Ok(t) => t,
+            ::core::result::Result::Err(e) => {
+                ::core::panic!("unwrap of `{}` failed: {:?}", ::core::stringify!($arg), e);
+            }
+        }
+    };
+    ($arg:expr, $($msg:expr),+ $(,)? ) => {
+        match $crate::fmt::Try::into_result($arg) {
+            ::core::result::Result::Ok(t) => t,
+            ::core::result::Result::Err(e) => {
+                ::core::panic!("unwrap of `{}` failed: {}: {:?}", ::core::stringify!($arg), ::core::format_args!($($msg,)*), e);
+            }
+        }
+    }
+}
+
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+pub struct NoneError;
+
+pub trait Try {
+    type Ok;
+    type Error;
+    fn into_result(self) -> Result<Self::Ok, Self::Error>;
+}
+
+impl<T> Try for Option<T> {
+    type Ok = T;
+    type Error = NoneError;
+
+    #[inline]
+    fn into_result(self) -> Result<T, NoneError> {
+        self.ok_or(NoneError)
+    }
+}
+
+impl<T, E> Try for Result<T, E> {
+    type Ok = T;
+    type Error = E;
+
+    #[inline]
+    fn into_result(self) -> Self {
+        self
+    }
+}
+
+pub(crate) struct Bytes<'a>(pub &'a [u8]);
+
+impl<'a> Debug for Bytes<'a> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "{:#02x?}", self.0)
+    }
+}
+
+impl<'a> Display for Bytes<'a> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "{:#02x?}", self.0)
+    }
+}
+
+impl<'a> LowerHex for Bytes<'a> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "{:#02x?}", self.0)
+    }
+}
+
+#[cfg(feature = "defmt")]
+impl<'a> defmt::Format for Bytes<'a> {
+    fn format(&self, fmt: defmt::Formatter) {
+        defmt::write!(fmt, "{:02x}", self.0)
+    }
+}
diff --git a/embassy-nxp/src/gpio.rs b/embassy-nxp/src/gpio.rs
index c7c78ce61..3049cc12d 100644
--- a/embassy-nxp/src/gpio.rs
+++ b/embassy-nxp/src/gpio.rs
@@ -1,354 +1,7 @@
-use embassy_hal_internal::{impl_peripheral, PeripheralType};
+//! General purpose input/output (GPIO) driver.
+#![macro_use]
 
-use crate::pac_utils::*;
-use crate::{peripherals, Peri};
-
-pub(crate) fn init() {
-    // Enable clocks for GPIO, PINT, and IOCON
-    syscon_reg()
-        .ahbclkctrl0
-        .modify(|_, w| w.gpio0().enable().gpio1().enable().mux().enable().iocon().enable());
-}
-
-/// The GPIO pin level for pins set on "Digital" mode.
-#[derive(Debug, Eq, PartialEq, Clone, Copy)]
-pub enum Level {
-    /// Logical low. Corresponds to 0V.
-    Low,
-    /// Logical high. Corresponds to VDD.
-    High,
-}
-
-/// Pull setting for a GPIO input set on "Digital" mode.
-#[derive(Debug, Clone, Copy, Eq, PartialEq)]
-pub enum Pull {
-    /// No pull.
-    None,
-    /// Internal pull-up resistor.
-    Up,
-    /// Internal pull-down resistor.
-    Down,
-}
-
-/// The LPC55 boards have two GPIO banks, each with 32 pins. This enum represents the two banks.
-#[derive(Debug, Eq, PartialEq, Clone, Copy)]
-pub enum Bank {
-    Bank0 = 0,
-    Bank1 = 1,
-}
-
-/// GPIO output driver. Internally, this is a specialized [Flex] pin.
-pub struct Output<'d> {
-    pub(crate) pin: Flex<'d>,
-}
-
-impl<'d> Output<'d> {
-    /// Create GPIO output driver for a [Pin] with the provided [initial output](Level).
-    #[inline]
-    pub fn new(pin: Peri<'d, impl Pin>, initial_output: Level) -> Self {
-        let mut pin = Flex::new(pin);
-        pin.set_as_output();
-        let mut result = Self { pin };
-
-        match initial_output {
-            Level::High => result.set_high(),
-            Level::Low => result.set_low(),
-        };
-
-        result
-    }
-
-    pub fn set_high(&mut self) {
-        gpio_reg().set[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
-    }
-
-    pub fn set_low(&mut self) {
-        gpio_reg().clr[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
-    }
-
-    pub fn toggle(&mut self) {
-        gpio_reg().not[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
-    }
-
-    /// Get the current output level of the pin. Note that the value returned by this function is
-    /// the voltage level reported by the pin, not the value set by the output driver.
-    pub fn level(&self) -> Level {
-        let bits = gpio_reg().pin[self.pin.pin_bank() as usize].read().bits();
-        if bits & self.pin.bit() != 0 {
-            Level::High
-        } else {
-            Level::Low
-        }
-    }
-}
-
-/// GPIO input driver. Internally, this is a specialized [Flex] pin.
-pub struct Input<'d> {
-    pub(crate) pin: Flex<'d>,
-}
-
-impl<'d> Input<'d> {
-    /// Create GPIO output driver for a [Pin] with the provided [Pull].
-    #[inline]
-    pub fn new(pin: Peri<'d, impl Pin>, pull: Pull) -> Self {
-        let mut pin = Flex::new(pin);
-        pin.set_as_input();
-        let mut result = Self { pin };
-        result.set_pull(pull);
-
-        result
-    }
-
-    /// Set the pull configuration for the pin. To disable the pull, use [Pull::None].
-    pub fn set_pull(&mut self, pull: Pull) {
-        match_iocon!(register, iocon_reg(), self.pin.pin_bank(), self.pin.pin_number(), {
-            register.modify(|_, w| match pull {
-                Pull::None => w.mode().inactive(),
-                Pull::Up => w.mode().pull_up(),
-                Pull::Down => w.mode().pull_down(),
-            });
-        });
-    }
-
-    /// Get the current input level of the pin.
-    pub fn read(&self) -> Level {
-        let bits = gpio_reg().pin[self.pin.pin_bank() as usize].read().bits();
-        if bits & self.pin.bit() != 0 {
-            Level::High
-        } else {
-            Level::Low
-        }
-    }
-}
-
-/// A flexible GPIO (digital mode) pin whose mode is not yet determined. Under the hood, this is a
-/// reference to a type-erased pin called ["AnyPin"](AnyPin).
-pub struct Flex<'d> {
-    pub(crate) pin: Peri<'d, AnyPin>,
-}
-
-impl<'d> Flex<'d> {
-    /// Wrap the pin in a `Flex`.
-    ///
-    /// Note: you cannot assume that the pin will be in Digital mode after this call.
-    #[inline]
-    pub fn new(pin: Peri<'d, impl Pin>) -> Self {
-        Self { pin: pin.into() }
-    }
-
-    /// Get the bank of this pin. See also [Bank].
-    ///
-    /// # Example
-    ///
-    /// ```
-    /// use embassy_nxp::gpio::{Bank, Flex};
-    ///
-    /// let p = embassy_nxp::init(Default::default());
-    /// let pin = Flex::new(p.PIO1_15);
-    ///
-    /// assert_eq!(pin.pin_bank(), Bank::Bank1);
-    /// ```
-    pub fn pin_bank(&self) -> Bank {
-        self.pin.pin_bank()
-    }
-
-    /// Get the number of this pin within its bank. See also [Bank].
-    ///
-    /// # Example
-    ///
-    /// ```
-    /// use embassy_nxp::gpio::Flex;
-    ///
-    /// let p = embassy_nxp::init(Default::default());
-    /// let pin = Flex::new(p.PIO1_15);
-    ///
-    /// assert_eq!(pin.pin_number(), 15 as u8);
-    /// ```
-    pub fn pin_number(&self) -> u8 {
-        self.pin.pin_number()
-    }
-
-    /// Get the bit mask for this pin. Useful for setting or clearing bits in a register. Note:
-    /// PIOx_0 is bit 0, PIOx_1 is bit 1, etc.
-    ///
-    /// # Example
-    ///
-    /// ```
-    /// use embassy_nxp::gpio::Flex;
-    ///
-    /// let p = embassy_nxp::init(Default::default());
-    /// let pin = Flex::new(p.PIO1_3);
-    ///
-    /// assert_eq!(pin.bit(), 0b0000_1000);
-    /// ```
-    pub fn bit(&self) -> u32 {
-        1 << self.pin.pin_number()
-    }
-
-    /// Set the pin to digital mode. This is required for using a pin as a GPIO pin. The default
-    /// setting for pins is (usually) non-digital.
-    fn set_as_digital(&mut self) {
-        match_iocon!(register, iocon_reg(), self.pin_bank(), self.pin_number(), {
-            register.modify(|_, w| w.digimode().digital());
-        });
-    }
-
-    /// Set the pin in output mode. This implies setting the pin to digital mode, which this
-    /// function handles itself.
-    pub fn set_as_output(&mut self) {
-        self.set_as_digital();
-        gpio_reg().dirset[self.pin.pin_bank() as usize].write(|w| unsafe { w.dirsetp().bits(self.bit()) })
-    }
-
-    pub fn set_as_input(&mut self) {
-        self.set_as_digital();
-        gpio_reg().dirclr[self.pin.pin_bank() as usize].write(|w| unsafe { w.dirclrp().bits(self.bit()) })
-    }
-}
-
-/// Sealed trait for pins. This trait is sealed and cannot be implemented outside of this crate.
-pub(crate) trait SealedPin: Sized {
-    fn pin_bank(&self) -> Bank;
-    fn pin_number(&self) -> u8;
-}
-
-/// Interface for a Pin that can be configured by an [Input] or [Output] driver, or converted to an
-/// [AnyPin]. By default, this trait is sealed and cannot be implemented outside of the
-/// `embassy-nxp` crate due to the [SealedPin] trait.
-#[allow(private_bounds)]
-pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
-    /// Returns the pin number within a bank
-    #[inline]
-    fn pin(&self) -> u8 {
-        self.pin_number()
-    }
-
-    /// Returns the bank of this pin
-    #[inline]
-    fn bank(&self) -> Bank {
-        self.pin_bank()
-    }
-}
-
-/// Type-erased GPIO pin.
-pub struct AnyPin {
-    pin_bank: Bank,
-    pin_number: u8,
-}
-
-impl AnyPin {
-    /// Unsafely create a new type-erased pin.
-    ///
-    /// # Safety
-    ///
-    /// You must ensure that you’re only using one instance of this type at a time.
-    pub unsafe fn steal(pin_bank: Bank, pin_number: u8) -> Peri<'static, Self> {
-        Peri::new_unchecked(Self { pin_bank, pin_number })
-    }
-}
-
-impl_peripheral!(AnyPin);
-
-impl Pin for AnyPin {}
-impl SealedPin for AnyPin {
-    #[inline]
-    fn pin_bank(&self) -> Bank {
-        self.pin_bank
-    }
-
-    #[inline]
-    fn pin_number(&self) -> u8 {
-        self.pin_number
-    }
-}
-
-macro_rules! impl_pin {
-    ($name:ident, $bank:expr, $pin_num:expr) => {
-        impl Pin for peripherals::$name {}
-        impl SealedPin for peripherals::$name {
-            #[inline]
-            fn pin_bank(&self) -> Bank {
-                $bank
-            }
-
-            #[inline]
-            fn pin_number(&self) -> u8 {
-                $pin_num
-            }
-        }
-
-        impl From<peripherals::$name> for crate::gpio::AnyPin {
-            fn from(val: peripherals::$name) -> Self {
-                Self {
-                    pin_bank: val.pin_bank(),
-                    pin_number: val.pin_number(),
-                }
-            }
-        }
-    };
-}
-
-impl_pin!(PIO0_0, Bank::Bank0, 0);
-impl_pin!(PIO0_1, Bank::Bank0, 1);
-impl_pin!(PIO0_2, Bank::Bank0, 2);
-impl_pin!(PIO0_3, Bank::Bank0, 3);
-impl_pin!(PIO0_4, Bank::Bank0, 4);
-impl_pin!(PIO0_5, Bank::Bank0, 5);
-impl_pin!(PIO0_6, Bank::Bank0, 6);
-impl_pin!(PIO0_7, Bank::Bank0, 7);
-impl_pin!(PIO0_8, Bank::Bank0, 8);
-impl_pin!(PIO0_9, Bank::Bank0, 9);
-impl_pin!(PIO0_10, Bank::Bank0, 10);
-impl_pin!(PIO0_11, Bank::Bank0, 11);
-impl_pin!(PIO0_12, Bank::Bank0, 12);
-impl_pin!(PIO0_13, Bank::Bank0, 13);
-impl_pin!(PIO0_14, Bank::Bank0, 14);
-impl_pin!(PIO0_15, Bank::Bank0, 15);
-impl_pin!(PIO0_16, Bank::Bank0, 16);
-impl_pin!(PIO0_17, Bank::Bank0, 17);
-impl_pin!(PIO0_18, Bank::Bank0, 18);
-impl_pin!(PIO0_19, Bank::Bank0, 19);
-impl_pin!(PIO0_20, Bank::Bank0, 20);
-impl_pin!(PIO0_21, Bank::Bank0, 21);
-impl_pin!(PIO0_22, Bank::Bank0, 22);
-impl_pin!(PIO0_23, Bank::Bank0, 23);
-impl_pin!(PIO0_24, Bank::Bank0, 24);
-impl_pin!(PIO0_25, Bank::Bank0, 25);
-impl_pin!(PIO0_26, Bank::Bank0, 26);
-impl_pin!(PIO0_27, Bank::Bank0, 27);
-impl_pin!(PIO0_28, Bank::Bank0, 28);
-impl_pin!(PIO0_29, Bank::Bank0, 29);
-impl_pin!(PIO0_30, Bank::Bank0, 30);
-impl_pin!(PIO0_31, Bank::Bank0, 31);
-impl_pin!(PIO1_0, Bank::Bank1, 0);
-impl_pin!(PIO1_1, Bank::Bank1, 1);
-impl_pin!(PIO1_2, Bank::Bank1, 2);
-impl_pin!(PIO1_3, Bank::Bank1, 3);
-impl_pin!(PIO1_4, Bank::Bank1, 4);
-impl_pin!(PIO1_5, Bank::Bank1, 5);
-impl_pin!(PIO1_6, Bank::Bank1, 6);
-impl_pin!(PIO1_7, Bank::Bank1, 7);
-impl_pin!(PIO1_8, Bank::Bank1, 8);
-impl_pin!(PIO1_9, Bank::Bank1, 9);
-impl_pin!(PIO1_10, Bank::Bank1, 10);
-impl_pin!(PIO1_11, Bank::Bank1, 11);
-impl_pin!(PIO1_12, Bank::Bank1, 12);
-impl_pin!(PIO1_13, Bank::Bank1, 13);
-impl_pin!(PIO1_14, Bank::Bank1, 14);
-impl_pin!(PIO1_15, Bank::Bank1, 15);
-impl_pin!(PIO1_16, Bank::Bank1, 16);
-impl_pin!(PIO1_17, Bank::Bank1, 17);
-impl_pin!(PIO1_18, Bank::Bank1, 18);
-impl_pin!(PIO1_19, Bank::Bank1, 19);
-impl_pin!(PIO1_20, Bank::Bank1, 20);
-impl_pin!(PIO1_21, Bank::Bank1, 21);
-impl_pin!(PIO1_22, Bank::Bank1, 22);
-impl_pin!(PIO1_23, Bank::Bank1, 23);
-impl_pin!(PIO1_24, Bank::Bank1, 24);
-impl_pin!(PIO1_25, Bank::Bank1, 25);
-impl_pin!(PIO1_26, Bank::Bank1, 26);
-impl_pin!(PIO1_27, Bank::Bank1, 27);
-impl_pin!(PIO1_28, Bank::Bank1, 28);
-impl_pin!(PIO1_29, Bank::Bank1, 29);
-impl_pin!(PIO1_30, Bank::Bank1, 30);
-impl_pin!(PIO1_31, Bank::Bank1, 31);
+#[cfg_attr(feature = "lpc55", path = "./gpio/lpc55.rs")]
+#[cfg_attr(rt1xxx, path = "./gpio/rt1xxx.rs")]
+mod inner;
+pub use inner::*;
diff --git a/embassy-nxp/src/pac_utils.rs b/embassy-nxp/src/gpio/lpc55.rs
index 86a807f6c..8f407bb3a 100644
--- a/embassy-nxp/src/pac_utils.rs
+++ b/embassy-nxp/src/gpio/lpc55.rs
@@ -1,3 +1,267 @@
+use embassy_hal_internal::{impl_peripheral, PeripheralType};
+
+use crate::{peripherals, Peri};
+
+pub(crate) fn init() {
+    // Enable clocks for GPIO, PINT, and IOCON
+    syscon_reg()
+        .ahbclkctrl0
+        .modify(|_, w| w.gpio0().enable().gpio1().enable().mux().enable().iocon().enable());
+    info!("GPIO initialized");
+}
+
+/// The GPIO pin level for pins set on "Digital" mode.
+#[derive(Debug, Eq, PartialEq, Clone, Copy)]
+pub enum Level {
+    /// Logical low. Corresponds to 0V.
+    Low,
+    /// Logical high. Corresponds to VDD.
+    High,
+}
+
+/// Pull setting for a GPIO input set on "Digital" mode.
+#[derive(Debug, Clone, Copy, Eq, PartialEq)]
+pub enum Pull {
+    /// No pull.
+    None,
+    /// Internal pull-up resistor.
+    Up,
+    /// Internal pull-down resistor.
+    Down,
+}
+
+/// The LPC55 boards have two GPIO banks, each with 32 pins. This enum represents the two banks.
+#[derive(Debug, Eq, PartialEq, Clone, Copy)]
+pub enum Bank {
+    Bank0 = 0,
+    Bank1 = 1,
+}
+
+/// GPIO output driver. Internally, this is a specialized [Flex] pin.
+pub struct Output<'d> {
+    pub(crate) pin: Flex<'d>,
+}
+
+impl<'d> Output<'d> {
+    /// Create GPIO output driver for a [Pin] with the provided [initial output](Level).
+    #[inline]
+    pub fn new(pin: Peri<'d, impl Pin>, initial_output: Level) -> Self {
+        let mut pin = Flex::new(pin);
+        pin.set_as_output();
+        let mut result = Self { pin };
+
+        match initial_output {
+            Level::High => result.set_high(),
+            Level::Low => result.set_low(),
+        };
+
+        result
+    }
+
+    pub fn set_high(&mut self) {
+        gpio_reg().set[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
+    }
+
+    pub fn set_low(&mut self) {
+        gpio_reg().clr[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
+    }
+
+    pub fn toggle(&mut self) {
+        gpio_reg().not[self.pin.pin_bank() as usize].write(|w| unsafe { w.bits(self.pin.bit()) })
+    }
+
+    /// Get the current output level of the pin. Note that the value returned by this function is
+    /// the voltage level reported by the pin, not the value set by the output driver.
+    pub fn level(&self) -> Level {
+        let bits = gpio_reg().pin[self.pin.pin_bank() as usize].read().bits();
+        if bits & self.pin.bit() != 0 {
+            Level::High
+        } else {
+            Level::Low
+        }
+    }
+}
+
+/// GPIO input driver. Internally, this is a specialized [Flex] pin.
+pub struct Input<'d> {
+    pub(crate) pin: Flex<'d>,
+}
+
+impl<'d> Input<'d> {
+    /// Create GPIO output driver for a [Pin] with the provided [Pull].
+    #[inline]
+    pub fn new(pin: Peri<'d, impl Pin>, pull: Pull) -> Self {
+        let mut pin = Flex::new(pin);
+        pin.set_as_input();
+        let mut result = Self { pin };
+        result.set_pull(pull);
+
+        result
+    }
+
+    /// Set the pull configuration for the pin. To disable the pull, use [Pull::None].
+    pub fn set_pull(&mut self, pull: Pull) {
+        match_iocon!(register, iocon_reg(), self.pin.pin_bank(), self.pin.pin_number(), {
+            register.modify(|_, w| match pull {
+                Pull::None => w.mode().inactive(),
+                Pull::Up => w.mode().pull_up(),
+                Pull::Down => w.mode().pull_down(),
+            });
+        });
+    }
+
+    /// Get the current input level of the pin.
+    pub fn read(&self) -> Level {
+        let bits = gpio_reg().pin[self.pin.pin_bank() as usize].read().bits();
+        if bits & self.pin.bit() != 0 {
+            Level::High
+        } else {
+            Level::Low
+        }
+    }
+}
+
+/// A flexible GPIO (digital mode) pin whose mode is not yet determined. Under the hood, this is a
+/// reference to a type-erased pin called ["AnyPin"](AnyPin).
+pub struct Flex<'d> {
+    pub(crate) pin: Peri<'d, AnyPin>,
+}
+
+impl<'d> Flex<'d> {
+    /// Wrap the pin in a `Flex`.
+    ///
+    /// Note: you cannot assume that the pin will be in Digital mode after this call.
+    #[inline]
+    pub fn new(pin: Peri<'d, impl Pin>) -> Self {
+        Self { pin: pin.into() }
+    }
+
+    /// Get the bank of this pin. See also [Bank].
+    ///
+    /// # Example
+    ///
+    /// ```
+    /// use embassy_nxp::gpio::{Bank, Flex};
+    ///
+    /// let p = embassy_nxp::init(Default::default());
+    /// let pin = Flex::new(p.PIO1_15);
+    ///
+    /// assert_eq!(pin.pin_bank(), Bank::Bank1);
+    /// ```
+    pub fn pin_bank(&self) -> Bank {
+        self.pin.pin_bank()
+    }
+
+    /// Get the number of this pin within its bank. See also [Bank].
+    ///
+    /// # Example
+    ///
+    /// ```
+    /// use embassy_nxp::gpio::Flex;
+    ///
+    /// let p = embassy_nxp::init(Default::default());
+    /// let pin = Flex::new(p.PIO1_15);
+    ///
+    /// assert_eq!(pin.pin_number(), 15 as u8);
+    /// ```
+    pub fn pin_number(&self) -> u8 {
+        self.pin.pin_number()
+    }
+
+    /// Get the bit mask for this pin. Useful for setting or clearing bits in a register. Note:
+    /// PIOx_0 is bit 0, PIOx_1 is bit 1, etc.
+    ///
+    /// # Example
+    ///
+    /// ```
+    /// use embassy_nxp::gpio::Flex;
+    ///
+    /// let p = embassy_nxp::init(Default::default());
+    /// let pin = Flex::new(p.PIO1_3);
+    ///
+    /// assert_eq!(pin.bit(), 0b0000_1000);
+    /// ```
+    pub fn bit(&self) -> u32 {
+        1 << self.pin.pin_number()
+    }
+
+    /// Set the pin to digital mode. This is required for using a pin as a GPIO pin. The default
+    /// setting for pins is (usually) non-digital.
+    fn set_as_digital(&mut self) {
+        match_iocon!(register, iocon_reg(), self.pin_bank(), self.pin_number(), {
+            register.modify(|_, w| w.digimode().digital());
+        });
+    }
+
+    /// Set the pin in output mode. This implies setting the pin to digital mode, which this
+    /// function handles itself.
+    pub fn set_as_output(&mut self) {
+        self.set_as_digital();
+        gpio_reg().dirset[self.pin.pin_bank() as usize].write(|w| unsafe { w.dirsetp().bits(self.bit()) })
+    }
+
+    pub fn set_as_input(&mut self) {
+        self.set_as_digital();
+        gpio_reg().dirclr[self.pin.pin_bank() as usize].write(|w| unsafe { w.dirclrp().bits(self.bit()) })
+    }
+}
+
+/// Sealed trait for pins. This trait is sealed and cannot be implemented outside of this crate.
+pub(crate) trait SealedPin: Sized {
+    fn pin_bank(&self) -> Bank;
+    fn pin_number(&self) -> u8;
+}
+
+/// Interface for a Pin that can be configured by an [Input] or [Output] driver, or converted to an
+/// [AnyPin]. By default, this trait is sealed and cannot be implemented outside of the
+/// `embassy-nxp` crate due to the [SealedPin] trait.
+#[allow(private_bounds)]
+pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
+    /// Returns the pin number within a bank
+    #[inline]
+    fn pin(&self) -> u8 {
+        self.pin_number()
+    }
+
+    /// Returns the bank of this pin
+    #[inline]
+    fn bank(&self) -> Bank {
+        self.pin_bank()
+    }
+}
+
+/// Type-erased GPIO pin.
+pub struct AnyPin {
+    pin_bank: Bank,
+    pin_number: u8,
+}
+
+impl AnyPin {
+    /// Unsafely create a new type-erased pin.
+    ///
+    /// # Safety
+    ///
+    /// You must ensure that you’re only using one instance of this type at a time.
+    pub unsafe fn steal(pin_bank: Bank, pin_number: u8) -> Peri<'static, Self> {
+        Peri::new_unchecked(Self { pin_bank, pin_number })
+    }
+}
+
+impl_peripheral!(AnyPin);
+
+impl Pin for AnyPin {}
+impl SealedPin for AnyPin {
+    #[inline]
+    fn pin_bank(&self) -> Bank {
+        self.pin_bank
+    }
+
+    #[inline]
+    fn pin_number(&self) -> u8 {
+        self.pin_number
+    }
+}
+
 /// Get the GPIO register block. This is used to configure all GPIO pins.
 ///
 /// # Safety
@@ -321,3 +585,94 @@ macro_rules! match_iocon {
 }
 
 pub(crate) use match_iocon;
+
+macro_rules! impl_pin {
+    ($name:ident, $bank:expr, $pin_num:expr) => {
+        impl Pin for peripherals::$name {}
+        impl SealedPin for peripherals::$name {
+            #[inline]
+            fn pin_bank(&self) -> Bank {
+                $bank
+            }
+
+            #[inline]
+            fn pin_number(&self) -> u8 {
+                $pin_num
+            }
+        }
+
+        impl From<peripherals::$name> for crate::gpio::AnyPin {
+            fn from(val: peripherals::$name) -> Self {
+                Self {
+                    pin_bank: val.pin_bank(),
+                    pin_number: val.pin_number(),
+                }
+            }
+        }
+    };
+}
+
+impl_pin!(PIO0_0, Bank::Bank0, 0);
+impl_pin!(PIO0_1, Bank::Bank0, 1);
+impl_pin!(PIO0_2, Bank::Bank0, 2);
+impl_pin!(PIO0_3, Bank::Bank0, 3);
+impl_pin!(PIO0_4, Bank::Bank0, 4);
+impl_pin!(PIO0_5, Bank::Bank0, 5);
+impl_pin!(PIO0_6, Bank::Bank0, 6);
+impl_pin!(PIO0_7, Bank::Bank0, 7);
+impl_pin!(PIO0_8, Bank::Bank0, 8);
+impl_pin!(PIO0_9, Bank::Bank0, 9);
+impl_pin!(PIO0_10, Bank::Bank0, 10);
+impl_pin!(PIO0_11, Bank::Bank0, 11);
+impl_pin!(PIO0_12, Bank::Bank0, 12);
+impl_pin!(PIO0_13, Bank::Bank0, 13);
+impl_pin!(PIO0_14, Bank::Bank0, 14);
+impl_pin!(PIO0_15, Bank::Bank0, 15);
+impl_pin!(PIO0_16, Bank::Bank0, 16);
+impl_pin!(PIO0_17, Bank::Bank0, 17);
+impl_pin!(PIO0_18, Bank::Bank0, 18);
+impl_pin!(PIO0_19, Bank::Bank0, 19);
+impl_pin!(PIO0_20, Bank::Bank0, 20);
+impl_pin!(PIO0_21, Bank::Bank0, 21);
+impl_pin!(PIO0_22, Bank::Bank0, 22);
+impl_pin!(PIO0_23, Bank::Bank0, 23);
+impl_pin!(PIO0_24, Bank::Bank0, 24);
+impl_pin!(PIO0_25, Bank::Bank0, 25);
+impl_pin!(PIO0_26, Bank::Bank0, 26);
+impl_pin!(PIO0_27, Bank::Bank0, 27);
+impl_pin!(PIO0_28, Bank::Bank0, 28);
+impl_pin!(PIO0_29, Bank::Bank0, 29);
+impl_pin!(PIO0_30, Bank::Bank0, 30);
+impl_pin!(PIO0_31, Bank::Bank0, 31);
+impl_pin!(PIO1_0, Bank::Bank1, 0);
+impl_pin!(PIO1_1, Bank::Bank1, 1);
+impl_pin!(PIO1_2, Bank::Bank1, 2);
+impl_pin!(PIO1_3, Bank::Bank1, 3);
+impl_pin!(PIO1_4, Bank::Bank1, 4);
+impl_pin!(PIO1_5, Bank::Bank1, 5);
+impl_pin!(PIO1_6, Bank::Bank1, 6);
+impl_pin!(PIO1_7, Bank::Bank1, 7);
+impl_pin!(PIO1_8, Bank::Bank1, 8);
+impl_pin!(PIO1_9, Bank::Bank1, 9);
+impl_pin!(PIO1_10, Bank::Bank1, 10);
+impl_pin!(PIO1_11, Bank::Bank1, 11);
+impl_pin!(PIO1_12, Bank::Bank1, 12);
+impl_pin!(PIO1_13, Bank::Bank1, 13);
+impl_pin!(PIO1_14, Bank::Bank1, 14);
+impl_pin!(PIO1_15, Bank::Bank1, 15);
+impl_pin!(PIO1_16, Bank::Bank1, 16);
+impl_pin!(PIO1_17, Bank::Bank1, 17);
+impl_pin!(PIO1_18, Bank::Bank1, 18);
+impl_pin!(PIO1_19, Bank::Bank1, 19);
+impl_pin!(PIO1_20, Bank::Bank1, 20);
+impl_pin!(PIO1_21, Bank::Bank1, 21);
+impl_pin!(PIO1_22, Bank::Bank1, 22);
+impl_pin!(PIO1_23, Bank::Bank1, 23);
+impl_pin!(PIO1_24, Bank::Bank1, 24);
+impl_pin!(PIO1_25, Bank::Bank1, 25);
+impl_pin!(PIO1_26, Bank::Bank1, 26);
+impl_pin!(PIO1_27, Bank::Bank1, 27);
+impl_pin!(PIO1_28, Bank::Bank1, 28);
+impl_pin!(PIO1_29, Bank::Bank1, 29);
+impl_pin!(PIO1_30, Bank::Bank1, 30);
+impl_pin!(PIO1_31, Bank::Bank1, 31);
diff --git a/embassy-nxp/src/gpio/rt1xxx.rs b/embassy-nxp/src/gpio/rt1xxx.rs
new file mode 100644
index 000000000..1d60a0d51
--- /dev/null
+++ b/embassy-nxp/src/gpio/rt1xxx.rs
@@ -0,0 +1,945 @@
+#![macro_use]
+
+use core::future::Future;
+use core::ops::Not;
+use core::pin::Pin as FuturePin;
+use core::task::{Context, Poll};
+
+use embassy_hal_internal::{impl_peripheral, Peri, PeripheralType};
+use embassy_sync::waitqueue::AtomicWaker;
+use nxp_pac::gpio::vals::Icr;
+use nxp_pac::iomuxc::vals::Pus;
+
+use crate::chip::{mux_address, pad_address};
+use crate::pac::common::{Reg, RW};
+use crate::pac::gpio::Gpio;
+#[cfg(feature = "rt")]
+use crate::pac::interrupt;
+use crate::pac::iomuxc::regs::{Ctl, MuxCtl};
+use crate::pac::{self};
+
+/// The GPIO pin level for pins set on "Digital" mode.
+#[derive(Debug, Eq, PartialEq, Clone, Copy)]
+pub enum Level {
+    /// Logical low. Corresponds to 0V.
+    Low,
+    /// Logical high. Corresponds to VDD.
+    High,
+}
+
+impl From<bool> for Level {
+    fn from(val: bool) -> Self {
+        match val {
+            true => Self::High,
+            false => Self::Low,
+        }
+    }
+}
+
+impl From<Level> for bool {
+    fn from(level: Level) -> bool {
+        match level {
+            Level::Low => false,
+            Level::High => true,
+        }
+    }
+}
+
+impl Not for Level {
+    type Output = Self;
+
+    fn not(self) -> Self::Output {
+        match self {
+            Level::Low => Level::High,
+            Level::High => Level::Low,
+        }
+    }
+}
+
+/// Pull setting for a GPIO input set on "Digital" mode.
+#[derive(Debug, Clone, Copy, Eq, PartialEq)]
+pub enum Pull {
+    /// No pull.
+    None,
+
+    // TODO: What Does PUE::KEEPER mean here?
+
+    // 22 kOhm pull-up resistor.
+    Up22K,
+
+    // 47 kOhm pull-up resistor.
+    Up47K,
+
+    // 100 kOhm pull-up resistor.
+    Up100K,
+
+    // 100 kOhm pull-down resistor.
+    Down100K,
+}
+
+/// Drive strength of an output
+#[derive(Copy, Clone, Debug, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Drive {
+    Disabled,
+    _150R,
+    _75R,
+    _50R,
+    _37R,
+    _30R,
+    _25R,
+    _20R,
+}
+
+/// Slew rate of an output
+#[derive(Copy, Clone, Debug, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum SlewRate {
+    Slow,
+
+    Fast,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Bank {
+    /// Bank 1
+    #[cfg(gpio1)]
+    Gpio1,
+
+    /// Bank 2
+    #[cfg(gpio2)]
+    Gpio2,
+
+    /// Bank 3
+    #[cfg(gpio3)]
+    Gpio3,
+
+    /// Bank 4
+    #[cfg(gpio4)]
+    Gpio4,
+
+    /// Bank 5
+    #[cfg(gpio5)]
+    Gpio5,
+}
+
+/// GPIO flexible pin.
+///
+/// This pin can either be a disconnected, input, or output pin, or both. The level register bit will remain
+/// set while not in output mode, so the pin's level will be 'remembered' when it is not in output
+/// mode.
+pub struct Flex<'d> {
+    pub(crate) pin: Peri<'d, AnyPin>,
+}
+
+impl<'d> Flex<'d> {
+    /// Wrap the pin in a `Flex`.
+    ///
+    /// The pin remains disconnected. The initial output level is unspecified, but can be changed
+    /// before the pin is put into output mode.
+    #[inline]
+    pub fn new(pin: Peri<'d, impl Pin>) -> Self {
+        Self { pin: pin.into() }
+    }
+
+    /// Set the pin's pull.
+    #[inline]
+    pub fn set_pull(&mut self, pull: Pull) {
+        let (pke, pue, pus) = match pull {
+            Pull::None => (false, true, Pus::PUS_0_100K_OHM_PULL_DOWN),
+            Pull::Up22K => (true, true, Pus::PUS_3_22K_OHM_PULL_UP),
+            Pull::Up47K => (true, true, Pus::PUS_1_47K_OHM_PULL_UP),
+            Pull::Up100K => (true, true, Pus::PUS_2_100K_OHM_PULL_UP),
+            Pull::Down100K => (true, true, Pus::PUS_0_100K_OHM_PULL_DOWN),
+        };
+
+        self.pin.pad().modify(|w| {
+            w.set_pke(pke);
+            w.set_pue(pue);
+            w.set_pus(pus);
+        });
+    }
+
+    // Set the pin's slew rate.
+    #[inline]
+    pub fn set_slewrate(&mut self, rate: SlewRate) {
+        self.pin.pad().modify(|w| {
+            w.set_sre(match rate {
+                SlewRate::Slow => false,
+                SlewRate::Fast => true,
+            });
+        });
+    }
+
+    /// Set the pin's Schmitt trigger.
+    #[inline]
+    pub fn set_schmitt(&mut self, enable: bool) {
+        self.pin.pad().modify(|w| {
+            w.set_hys(enable);
+        });
+    }
+
+    /// Put the pin into input mode.
+    ///
+    /// The pull setting is left unchanged.
+    #[inline]
+    pub fn set_as_input(&mut self) {
+        self.pin.mux().modify(|w| {
+            w.set_mux_mode(GPIO_MUX_MODE);
+        });
+
+        // Setting direction is RMW
+        critical_section::with(|_cs| {
+            self.pin.block().gdir().modify(|w| {
+                w.set_gdir(self.pin.pin_number() as usize, false);
+            });
+        })
+    }
+
+    /// Put the pin into output mode.
+    ///
+    /// The pin level will be whatever was set before (or low by default). If you want it to begin
+    /// at a specific level, call `set_high`/`set_low` on the pin first.
+    #[inline]
+    pub fn set_as_output(&mut self) {
+        self.pin.mux().modify(|w| {
+            w.set_mux_mode(GPIO_MUX_MODE);
+        });
+
+        // Setting direction is RMW
+        critical_section::with(|_cs| {
+            self.pin.block().gdir().modify(|w| {
+                w.set_gdir(self.pin.pin_number() as usize, true);
+            });
+        })
+    }
+
+    /// Put the pin into input + open-drain output mode.
+    ///
+    /// The hardware will drive the line low if you set it to low, and will leave it floating if you set
+    /// it to high, in which case you can read the input to figure out whether another device
+    /// is driving the line low.
+    ///
+    /// The pin level will be whatever was set before (or low by default). If you want it to begin
+    /// at a specific level, call `set_high`/`set_low` on the pin first.
+    ///
+    /// The internal weak pull-up and pull-down resistors will be disabled.
+    #[inline]
+    pub fn set_as_input_output(&mut self) {
+        self.pin.pad().modify(|w| {
+            w.set_ode(true);
+        });
+    }
+
+    /// Set the pin as "disconnected", ie doing nothing and consuming the lowest
+    /// amount of power possible.
+    ///
+    /// This is currently the same as [`Self::set_as_analog()`] but is semantically different
+    /// really. Drivers should `set_as_disconnected()` pins when dropped.
+    ///
+    /// Note that this also disables the pull-up and pull-down resistors.
+    #[inline]
+    pub fn set_as_disconnected(&mut self) {
+        self.pin.pad().modify(|w| {
+            w.set_ode(false);
+            w.set_pke(false);
+            w.set_pue(false);
+            w.set_pus(Pus::PUS_0_100K_OHM_PULL_DOWN);
+        });
+    }
+
+    /// Get whether the pin input level is high.
+    #[inline]
+    pub fn is_high(&self) -> bool {
+        self.pin.block().psr().read().psr(self.pin.pin_number() as usize)
+    }
+
+    /// Get whether the pin input level is low.
+    #[inline]
+    pub fn is_low(&self) -> bool {
+        !self.is_high()
+    }
+
+    /// Returns current pin level
+    #[inline]
+    pub fn get_level(&self) -> Level {
+        self.is_high().into()
+    }
+
+    /// Set the output as high.
+    #[inline]
+    pub fn set_high(&mut self) {
+        self.pin.block().dr_set().write(|w| {
+            w.set_dr_set(self.pin.pin_number() as usize, true);
+        });
+    }
+
+    /// Set the output as low.
+    #[inline]
+    pub fn set_low(&mut self) {
+        self.pin.block().dr_clear().write(|w| {
+            w.set_dr_clear(self.pin.pin_number() as usize, true);
+        });
+    }
+
+    /// Toggle pin output
+    #[inline]
+    pub fn toggle(&mut self) {
+        self.pin.block().dr_toggle().write(|w| {
+            w.set_dr_toggle(self.pin.pin_number() as usize, true);
+        });
+    }
+
+    /// Set the output level.
+    #[inline]
+    pub fn set_level(&mut self, level: Level) {
+        match level {
+            Level::Low => self.set_low(),
+            Level::High => self.set_high(),
+        }
+    }
+
+    /// Get the current pin output level.
+    #[inline]
+    pub fn get_output_level(&self) -> Level {
+        self.is_set_high().into()
+    }
+
+    /// Is the output level high?
+    ///
+    /// If the [`Flex`] is set as an input, then this is equivalent to [`Flex::is_high`].
+    #[inline]
+    pub fn is_set_high(&self) -> bool {
+        self.pin.block().dr().read().dr(self.pin.pin_number() as usize)
+    }
+
+    /// Is the output level low?
+    ///
+    /// If the [`Flex`] is set as an input, then this is equivalent to [`Flex::is_low`].
+    #[inline]
+    pub fn is_set_low(&self) -> bool {
+        !self.is_set_high()
+    }
+
+    /// Wait until the pin is high. If it is already high, return immediately.
+    #[inline]
+    pub async fn wait_for_high(&mut self) {
+        InputFuture::new(self.pin.reborrow(), InterruptConfiguration::High).await
+    }
+
+    /// Wait until the pin is low. If it is already low, return immediately.
+    #[inline]
+    pub async fn wait_for_low(&mut self) {
+        InputFuture::new(self.pin.reborrow(), InterruptConfiguration::Low).await
+    }
+
+    /// Wait for the pin to undergo a transition from low to high.
+    #[inline]
+    pub async fn wait_for_rising_edge(&mut self) {
+        InputFuture::new(self.pin.reborrow(), InterruptConfiguration::RisingEdge).await
+    }
+
+    /// Wait for the pin to undergo a transition from high to low.
+    #[inline]
+    pub async fn wait_for_falling_edge(&mut self) {
+        InputFuture::new(self.pin.reborrow(), InterruptConfiguration::FallingEdge).await
+    }
+
+    /// Wait for the pin to undergo any transition, i.e low to high OR high to low.
+    #[inline]
+    pub async fn wait_for_any_edge(&mut self) {
+        InputFuture::new(self.pin.reborrow(), InterruptConfiguration::AnyEdge).await
+    }
+}
+
+impl<'d> Drop for Flex<'d> {
+    fn drop(&mut self) {
+        self.set_as_disconnected();
+    }
+}
+
+/// GPIO input driver.
+pub struct Input<'d> {
+    pin: Flex<'d>,
+}
+
+impl<'d> Input<'d> {
+    /// Create GPIO input driver for a [Pin] with the provided [Pull] configuration.
+    #[inline]
+    pub fn new(pin: Peri<'d, impl Pin>, pull: Pull) -> Self {
+        let mut pin = Flex::new(pin);
+        pin.set_as_input();
+        pin.set_pull(pull);
+        Self { pin }
+    }
+
+    /// Get whether the pin input level is high.
+    #[inline]
+    pub fn is_high(&self) -> bool {
+        self.pin.is_high()
+    }
+
+    /// Get whether the pin input level is low.
+    #[inline]
+    pub fn is_low(&self) -> bool {
+        self.pin.is_low()
+    }
+
+    /// Get the current pin input level.
+    #[inline]
+    pub fn get_level(&self) -> Level {
+        self.pin.get_level()
+    }
+
+    /// Wait until the pin is high. If it is already high, return immediately.
+    #[inline]
+    pub async fn wait_for_high(&mut self) {
+        self.pin.wait_for_high().await
+    }
+
+    /// Wait until the pin is low. If it is already low, return immediately.
+    #[inline]
+    pub async fn wait_for_low(&mut self) {
+        self.pin.wait_for_low().await
+    }
+
+    /// Wait for the pin to undergo a transition from low to high.
+    #[inline]
+    pub async fn wait_for_rising_edge(&mut self) {
+        self.pin.wait_for_rising_edge().await
+    }
+
+    /// Wait for the pin to undergo a transition from high to low.
+    #[inline]
+    pub async fn wait_for_falling_edge(&mut self) {
+        self.pin.wait_for_falling_edge().await
+    }
+
+    /// Wait for the pin to undergo any transition, i.e low to high OR high to low.
+    #[inline]
+    pub async fn wait_for_any_edge(&mut self) {
+        self.pin.wait_for_any_edge().await
+    }
+}
+
+/// GPIO output driver.
+///
+/// Note that pins will **return to their floating state** when `Output` is dropped.
+/// If pins should retain their state indefinitely, either keep ownership of the
+/// `Output`, or pass it to [`core::mem::forget`].
+pub struct Output<'d> {
+    pin: Flex<'d>,
+}
+
+impl<'d> Output<'d> {
+    /// Create GPIO output driver for a [Pin] with the provided [Level] configuration.
+    #[inline]
+    pub fn new(pin: Peri<'d, impl Pin>, initial_output: Level) -> Self {
+        let mut pin = Flex::new(pin);
+        pin.set_as_output();
+        pin.set_level(initial_output);
+        Self { pin }
+    }
+
+    /// Set the output as high.
+    #[inline]
+    pub fn set_high(&mut self) {
+        self.pin.set_high();
+    }
+
+    /// Set the output as low.
+    #[inline]
+    pub fn set_low(&mut self) {
+        self.pin.set_low();
+    }
+
+    /// Set the output level.
+    #[inline]
+    pub fn set_level(&mut self, level: Level) {
+        self.pin.set_level(level)
+    }
+
+    /// Is the output pin set as high?
+    #[inline]
+    pub fn is_set_high(&self) -> bool {
+        self.pin.is_set_high()
+    }
+
+    /// Is the output pin set as low?
+    #[inline]
+    pub fn is_set_low(&self) -> bool {
+        self.pin.is_set_low()
+    }
+
+    /// What level output is set to
+    #[inline]
+    pub fn get_output_level(&self) -> Level {
+        self.pin.get_output_level()
+    }
+
+    /// Toggle pin output
+    #[inline]
+    pub fn toggle(&mut self) {
+        self.pin.toggle();
+    }
+}
+
+/// GPIO output open-drain driver.
+///
+/// Note that pins will **return to their floating state** when `OutputOpenDrain` is dropped.
+/// If pins should retain their state indefinitely, either keep ownership of the
+/// `OutputOpenDrain`, or pass it to [`core::mem::forget`].
+pub struct OutputOpenDrain<'d> {
+    pin: Flex<'d>,
+}
+
+impl<'d> OutputOpenDrain<'d> {
+    /// Create a new GPIO open drain output driver for a [Pin] with the provided [Level].
+    #[inline]
+    pub fn new(pin: Peri<'d, impl Pin>, initial_output: Level) -> Self {
+        let mut pin = Flex::new(pin);
+        pin.set_level(initial_output);
+        pin.set_as_input_output();
+        Self { pin }
+    }
+
+    /// Get whether the pin input level is high.
+    #[inline]
+    pub fn is_high(&self) -> bool {
+        !self.pin.is_low()
+    }
+
+    /// Get whether the pin input level is low.
+    #[inline]
+    pub fn is_low(&self) -> bool {
+        self.pin.is_low()
+    }
+
+    /// Get the current pin input level.
+    #[inline]
+    pub fn get_level(&self) -> Level {
+        self.pin.get_level()
+    }
+
+    /// Set the output as high.
+    #[inline]
+    pub fn set_high(&mut self) {
+        self.pin.set_high();
+    }
+
+    /// Set the output as low.
+    #[inline]
+    pub fn set_low(&mut self) {
+        self.pin.set_low();
+    }
+
+    /// Set the output level.
+    #[inline]
+    pub fn set_level(&mut self, level: Level) {
+        self.pin.set_level(level);
+    }
+
+    /// Get whether the output level is set to high.
+    #[inline]
+    pub fn is_set_high(&self) -> bool {
+        self.pin.is_set_high()
+    }
+
+    /// Get whether the output level is set to low.
+    #[inline]
+    pub fn is_set_low(&self) -> bool {
+        self.pin.is_set_low()
+    }
+
+    /// Get the current output level.
+    #[inline]
+    pub fn get_output_level(&self) -> Level {
+        self.pin.get_output_level()
+    }
+
+    /// Toggle pin output
+    #[inline]
+    pub fn toggle(&mut self) {
+        self.pin.toggle()
+    }
+
+    /// Wait until the pin is high. If it is already high, return immediately.
+    #[inline]
+    pub async fn wait_for_high(&mut self) {
+        self.pin.wait_for_high().await
+    }
+
+    /// Wait until the pin is low. If it is already low, return immediately.
+    #[inline]
+    pub async fn wait_for_low(&mut self) {
+        self.pin.wait_for_low().await
+    }
+
+    /// Wait for the pin to undergo a transition from low to high.
+    #[inline]
+    pub async fn wait_for_rising_edge(&mut self) {
+        self.pin.wait_for_rising_edge().await
+    }
+
+    /// Wait for the pin to undergo a transition from high to low.
+    #[inline]
+    pub async fn wait_for_falling_edge(&mut self) {
+        self.pin.wait_for_falling_edge().await
+    }
+
+    /// Wait for the pin to undergo any transition, i.e low to high OR high to low.
+    #[inline]
+    pub async fn wait_for_any_edge(&mut self) {
+        self.pin.wait_for_any_edge().await
+    }
+}
+
+#[allow(private_bounds)]
+pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
+    /// Returns the pin number within a bank
+    #[inline]
+    fn pin(&self) -> u8 {
+        self.pin_number()
+    }
+
+    #[inline]
+    fn bank(&self) -> Bank {
+        self._bank()
+    }
+}
+
+/// Type-erased GPIO pin.
+pub struct AnyPin {
+    pub(crate) pin_number: u8,
+    pub(crate) bank: Bank,
+}
+
+impl AnyPin {
+    /// Unsafely create a new type-erased pin.
+    ///
+    /// # Safety
+    ///
+    /// You must ensure that you’re only using one instance of this type at a time.
+    pub unsafe fn steal(bank: Bank, pin_number: u8) -> Peri<'static, Self> {
+        Peri::new_unchecked(Self { pin_number, bank })
+    }
+}
+
+impl_peripheral!(AnyPin);
+
+impl Pin for AnyPin {}
+impl SealedPin for AnyPin {
+    #[inline]
+    fn pin_number(&self) -> u8 {
+        self.pin_number
+    }
+
+    #[inline]
+    fn _bank(&self) -> Bank {
+        self.bank
+    }
+}
+
+// Impl details
+
+/// Mux mode for GPIO pins. This is constant across all RT1xxx parts.
+const GPIO_MUX_MODE: u8 = 0b101;
+
+// FIXME: These don't always need to be 32 entries. GPIO5 on RT1101 contains a single pin and GPIO2 only 14.
+#[cfg(gpio1)]
+static GPIO1_WAKERS: [AtomicWaker; 32] = [const { AtomicWaker::new() }; 32];
+#[cfg(gpio2)]
+static GPIO2_WAKERS: [AtomicWaker; 32] = [const { AtomicWaker::new() }; 32];
+#[cfg(gpio3)]
+static GPIO3_WAKERS: [AtomicWaker; 32] = [const { AtomicWaker::new() }; 32];
+#[cfg(gpio4)]
+static GPIO4_WAKERS: [AtomicWaker; 32] = [const { AtomicWaker::new() }; 32];
+#[cfg(gpio5)]
+static GPIO5_WAKERS: [AtomicWaker; 32] = [const { AtomicWaker::new() }; 32];
+
+/// Sealed trait for pins. This trait is sealed and cannot be implemented outside of this crate.
+pub(crate) trait SealedPin: Sized {
+    fn pin_number(&self) -> u8;
+
+    fn _bank(&self) -> Bank;
+
+    #[inline]
+    fn block(&self) -> Gpio {
+        match self._bank() {
+            #[cfg(gpio1)]
+            Bank::Gpio1 => pac::GPIO1,
+            #[cfg(gpio2)]
+            Bank::Gpio2 => pac::GPIO2,
+            #[cfg(gpio3)]
+            Bank::Gpio3 => pac::GPIO3,
+            #[cfg(gpio4)]
+            Bank::Gpio4 => pac::GPIO4,
+            #[cfg(gpio5)]
+            Bank::Gpio5 => pac::GPIO5,
+        }
+    }
+
+    #[inline]
+    fn mux(&self) -> Reg<MuxCtl, RW> {
+        // SAFETY: The generated mux address table is valid since it is generated from the SVD files.
+        let address = unsafe { mux_address(self._bank(), self.pin_number()).unwrap_unchecked() };
+
+        // SAFETY: The register at the address is an instance of MuxCtl.
+        unsafe { Reg::from_ptr(address as *mut _) }
+    }
+
+    #[inline]
+    fn pad(&self) -> Reg<Ctl, RW> {
+        // SAFETY: The generated pad address table is valid since it is generated from the SVD files.
+        let address = unsafe { pad_address(self._bank(), self.pin_number()).unwrap_unchecked() };
+
+        // SAFETY: The register at the address is an instance of Ctl.
+        unsafe { Reg::from_ptr(address as *mut _) }
+    }
+
+    fn waker(&self) -> &AtomicWaker {
+        match self._bank() {
+            #[cfg(gpio1)]
+            Bank::Gpio1 => &GPIO1_WAKERS[self.pin_number() as usize],
+            #[cfg(gpio2)]
+            Bank::Gpio2 => &GPIO2_WAKERS[self.pin_number() as usize],
+            #[cfg(gpio3)]
+            Bank::Gpio3 => &GPIO3_WAKERS[self.pin_number() as usize],
+            #[cfg(gpio4)]
+            Bank::Gpio4 => &GPIO4_WAKERS[self.pin_number() as usize],
+            #[cfg(gpio5)]
+            Bank::Gpio5 => &GPIO5_WAKERS[self.pin_number() as usize],
+        }
+    }
+}
+
+/// This enum matches the layout of Icr.
+enum InterruptConfiguration {
+    Low,
+    High,
+    RisingEdge,
+    FallingEdge,
+    AnyEdge,
+}
+
+#[must_use = "futures do nothing unless you `.await` or poll them"]
+struct InputFuture<'d> {
+    pin: Peri<'d, AnyPin>,
+}
+
+impl<'d> InputFuture<'d> {
+    fn new(pin: Peri<'d, AnyPin>, config: InterruptConfiguration) -> Self {
+        let block = pin.block();
+
+        let (icr, edge_sel) = match config {
+            InterruptConfiguration::Low => (Icr::LOW_LEVEL, false),
+            InterruptConfiguration::High => (Icr::HIGH_LEVEL, false),
+            InterruptConfiguration::RisingEdge => (Icr::RISING_EDGE, false),
+            InterruptConfiguration::FallingEdge => (Icr::FALLING_EDGE, false),
+            InterruptConfiguration::AnyEdge => (Icr::FALLING_EDGE, true),
+        };
+
+        let index = if pin.pin_number() > 15 { 1 } else { 0 };
+
+        // Interrupt configuration performs RMW
+        critical_section::with(|_cs| {
+            // Disable interrupt so a level/edge detection change does not cause ISR to be set.
+            block.imr().modify(|w| {
+                w.set_imr(pin.pin_number() as usize, false);
+            });
+
+            block.icr(index).modify(|w| {
+                w.set_pin(pin.pin_number() as usize, icr);
+            });
+
+            block.edge_sel().modify(|w| {
+                w.set_edge_sel(pin.pin_number() as usize, edge_sel);
+            });
+
+            // Clear the previous interrupt.
+            block.isr().modify(|w| {
+                // "Status flags are cleared by writing a 1 to the corresponding bit position."
+                w.set_isr(pin.pin_number() as usize, true);
+            });
+        });
+
+        Self { pin }
+    }
+}
+
+impl<'d> Future for InputFuture<'d> {
+    type Output = ();
+
+    fn poll(self: FuturePin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
+        // We need to register/re-register the waker for each poll because any
+        // calls to wake will deregister the waker.
+        let waker = self.pin.waker();
+        waker.register(cx.waker());
+
+        // Enabling interrupt is RMW
+        critical_section::with(|_cs| {
+            self.pin.block().imr().modify(|w| {
+                w.set_imr(self.pin.pin_number() as usize, true);
+            });
+        });
+
+        let isr = self.pin.block().isr().read();
+
+        if isr.isr(self.pin.pin_number() as usize) {
+            return Poll::Ready(());
+        }
+
+        Poll::Pending
+    }
+}
+
+/// A macro to generate all GPIO pins.
+///
+/// This generates a lookup table for IOMUX register addresses.
+macro_rules! impl_gpio {
+    (
+        $($name: ident($bank: ident, $pin_number: expr);)*
+    ) => {
+        #[inline]
+        pub(crate) const fn pad_address(bank: crate::gpio::Bank, pin: u8) -> Option<u32> {
+            match (bank, pin) {
+                $(
+                    (crate::gpio::Bank::$bank, $pin_number) => Some(crate::chip::_generated::iomuxc::pads::$name),
+                )*
+                _ => None
+            }
+        }
+
+        #[inline]
+        pub(crate) const fn mux_address(bank: crate::gpio::Bank, pin: u8) -> Option<u32> {
+            match (bank, pin) {
+                $(
+                    (crate::gpio::Bank::$bank, $pin_number) => Some(crate::chip::_generated::iomuxc::muxes::$name),
+                )*
+                _ => None
+            }
+        }
+
+        $(
+            impl_pin!($name, $bank, $pin_number);
+        )*
+    };
+}
+
+macro_rules! impl_pin {
+    ($name: ident, $bank: ident, $pin_num: expr) => {
+        impl crate::gpio::Pin for crate::peripherals::$name {}
+        impl crate::gpio::SealedPin for crate::peripherals::$name {
+            #[inline]
+            fn pin_number(&self) -> u8 {
+                $pin_num
+            }
+
+            #[inline]
+            fn _bank(&self) -> crate::gpio::Bank {
+                crate::gpio::Bank::$bank
+            }
+        }
+
+        impl From<peripherals::$name> for crate::gpio::AnyPin {
+            fn from(val: peripherals::$name) -> Self {
+                use crate::gpio::SealedPin;
+
+                Self {
+                    pin_number: val.pin_number(),
+                    bank: val._bank(),
+                }
+            }
+        }
+    };
+}
+
+pub(crate) fn init() {
+    #[cfg(feature = "rt")]
+    unsafe {
+        use embassy_hal_internal::interrupt::InterruptExt;
+
+        pac::Interrupt::GPIO1_COMBINED_0_15.enable();
+        pac::Interrupt::GPIO1_COMBINED_16_31.enable();
+        pac::Interrupt::GPIO2_COMBINED_0_15.enable();
+        pac::Interrupt::GPIO5_COMBINED_0_15.enable();
+    }
+}
+
+/// IRQ handler for GPIO pins.
+///
+/// If `high_bits` is false, then the interrupt is for pins 0 through 15. If true, then the interrupt
+/// is for pins 16 through 31
+#[cfg(feature = "rt")]
+fn irq_handler(block: Gpio, wakers: &[AtomicWaker; 32], high_bits: bool) {
+    use crate::BitIter;
+
+    let isr = block.isr().read().0;
+    let imr = block.imr().read().0;
+    let mask = if high_bits { 0xFFFF_0000 } else { 0x0000_FFFF };
+    let bits = isr & imr & mask;
+
+    for bit in BitIter(bits) {
+        wakers[bit as usize].wake();
+
+        // Disable further interrupts for this pin. The input future will check ISR (which is kept
+        // until reset).
+        block.imr().modify(|w| {
+            w.set_imr(bit as usize, false);
+        });
+    }
+}
+
+#[cfg(all(any(feature = "mimxrt1011", feature = "mimxrt1062"), feature = "rt"))]
+#[interrupt]
+fn GPIO1_COMBINED_0_15() {
+    irq_handler(pac::GPIO1, &GPIO1_WAKERS, false);
+}
+
+#[cfg(all(any(feature = "mimxrt1011", feature = "mimxrt1062"), feature = "rt"))]
+#[interrupt]
+fn GPIO1_COMBINED_16_31() {
+    irq_handler(pac::GPIO1, &GPIO1_WAKERS, true);
+}
+
+#[cfg(all(any(feature = "mimxrt1011", feature = "mimxrt1062"), feature = "rt"))]
+#[interrupt]
+fn GPIO2_COMBINED_0_15() {
+    irq_handler(pac::GPIO2, &GPIO2_WAKERS, false);
+}
+
+#[cfg(all(feature = "mimxrt1062", feature = "rt"))]
+#[interrupt]
+fn GPIO2_COMBINED_16_31() {
+    irq_handler(pac::GPIO2, &GPIO2_WAKERS, true);
+}
+
+#[cfg(all(feature = "mimxrt1062", feature = "rt"))]
+#[interrupt]
+fn GPIO3_COMBINED_0_15() {
+    irq_handler(pac::GPIO3, &GPIO3_WAKERS, false);
+}
+
+#[cfg(all(feature = "mimxrt1062", feature = "rt"))]
+#[interrupt]
+fn GPIO3_COMBINED_16_31() {
+    irq_handler(pac::GPIO3, &GPIO3_WAKERS, true);
+}
+
+#[cfg(all(feature = "mimxrt1062", feature = "rt"))]
+#[interrupt]
+fn GPIO4_COMBINED_0_15() {
+    irq_handler(pac::GPIO4, &GPIO4_WAKERS, false);
+}
+
+#[cfg(all(feature = "mimxrt1062", feature = "rt"))]
+#[interrupt]
+fn GPIO4_COMBINED_16_31() {
+    irq_handler(pac::GPIO4, &GPIO4_WAKERS, true);
+}
+
+#[cfg(all(any(feature = "mimxrt1011", feature = "mimxrt1062"), feature = "rt"))]
+#[interrupt]
+fn GPIO5_COMBINED_0_15() {
+    irq_handler(pac::GPIO5, &GPIO5_WAKERS, false);
+}
diff --git a/embassy-nxp/src/lib.rs b/embassy-nxp/src/lib.rs
index ad2056c06..5e77fc0db 100644
--- a/embassy-nxp/src/lib.rs
+++ b/embassy-nxp/src/lib.rs
@@ -1,11 +1,28 @@
 #![no_std]
 
+// This mod MUST go first, so that the others see its macros.
+pub(crate) mod fmt;
+
 pub mod gpio;
-mod pac_utils;
+#[cfg(feature = "lpc55")]
 pub mod pint;
 
-pub use embassy_hal_internal::Peri;
-pub use lpc55_pac as pac;
+#[cfg(feature = "_time_driver")]
+#[cfg_attr(feature = "time-driver-pit", path = "time_driver/pit.rs")]
+mod time_driver;
+
+// This mod MUST go last, so that it sees all the `impl_foo!` macros
+#[cfg_attr(feature = "lpc55", path = "chips/lpc55.rs")]
+#[cfg_attr(feature = "mimxrt1011", path = "chips/mimxrt1011.rs")]
+#[cfg_attr(feature = "mimxrt1062", path = "chips/mimxrt1062.rs")]
+mod chip;
+
+#[cfg(feature = "unstable-pac")]
+pub use chip::pac;
+#[cfg(not(feature = "unstable-pac"))]
+pub(crate) use chip::pac;
+pub use chip::{peripherals, Peripherals};
+pub use embassy_hal_internal::{Peri, PeripheralType};
 
 /// Initialize the `embassy-nxp` HAL with the provided configuration.
 ///
@@ -13,79 +30,66 @@ pub use lpc55_pac as pac;
 ///
 /// This should only be called once and at startup, otherwise it panics.
 pub fn init(_config: config::Config) -> Peripherals {
+    // Do this first, so that it panics if user is calling `init` a second time
+    // before doing anything important.
+    let peripherals = Peripherals::take();
+
+    #[cfg(feature = "mimxrt1011")]
+    {
+        // The RT1010 Reference manual states that core clock root must be switched before
+        // reprogramming PLL2.
+        pac::CCM.cbcdr().modify(|w| {
+            w.set_periph_clk_sel(pac::ccm::vals::PeriphClkSel::PERIPH_CLK_SEL_1);
+        });
+
+        while matches!(
+            pac::CCM.cdhipr().read().periph_clk_sel_busy(),
+            pac::ccm::vals::PeriphClkSelBusy::PERIPH_CLK_SEL_BUSY_1
+        ) {}
+
+        info!("Core clock root switched");
+
+        // 480 * 18 / 24 = 360
+        pac::CCM_ANALOG.pfd_480().modify(|x| x.set_pfd2_frac(12));
+
+        //480*18/24(pfd0)/4
+        pac::CCM_ANALOG.pfd_480().modify(|x| x.set_pfd0_frac(24));
+        pac::CCM.cscmr1().modify(|x| x.set_flexspi_podf(3.into()));
+
+        // CPU Core
+        pac::CCM_ANALOG.pfd_528().modify(|x| x.set_pfd3_frac(18));
+        cortex_m::asm::delay(500_000);
+
+        // Clock core clock with PLL 2.
+        pac::CCM
+            .cbcdr()
+            .modify(|x| x.set_periph_clk_sel(pac::ccm::vals::PeriphClkSel::PERIPH_CLK_SEL_0)); // false
+
+        while matches!(
+            pac::CCM.cdhipr().read().periph_clk_sel_busy(),
+            pac::ccm::vals::PeriphClkSelBusy::PERIPH_CLK_SEL_BUSY_1
+        ) {}
+
+        pac::CCM
+            .cbcmr()
+            .write(|v| v.set_pre_periph_clk_sel(pac::ccm::vals::PrePeriphClkSel::PRE_PERIPH_CLK_SEL_0));
+
+        // TODO: Some for USB PLLs
+
+        // DCDC clock?
+        pac::CCM.ccgr6().modify(|v| v.set_cg0(1));
+    }
+
+    #[cfg(any(feature = "lpc55", rt1xxx))]
     gpio::init();
+
+    #[cfg(feature = "lpc55")]
     pint::init();
 
-    crate::Peripherals::take()
-}
+    #[cfg(feature = "_time_driver")]
+    time_driver::init();
 
-embassy_hal_internal::peripherals! {
-    // External pins. These are not only GPIOs, they are multi-purpose pins and can be used by other
-    // peripheral types (e.g. I2C).
-    PIO0_0,
-    PIO0_1,
-    PIO0_2,
-    PIO0_3,
-    PIO0_4,
-    PIO0_5,
-    PIO0_6,
-    PIO0_7,
-    PIO0_8,
-    PIO0_9,
-    PIO0_10,
-    PIO0_11,
-    PIO0_12,
-    PIO0_13,
-    PIO0_14,
-    PIO0_15,
-    PIO0_16,
-    PIO0_17,
-    PIO0_18,
-    PIO0_19,
-    PIO0_20,
-    PIO0_21,
-    PIO0_22,
-    PIO0_23,
-    PIO0_24,
-    PIO0_25,
-    PIO0_26,
-    PIO0_27,
-    PIO0_28,
-    PIO0_29,
-    PIO0_30,
-    PIO0_31,
-    PIO1_0,
-    PIO1_1,
-    PIO1_2,
-    PIO1_3,
-    PIO1_4,
-    PIO1_5,
-    PIO1_6,
-    PIO1_7,
-    PIO1_8,
-    PIO1_9,
-    PIO1_10,
-    PIO1_11,
-    PIO1_12,
-    PIO1_13,
-    PIO1_14,
-    PIO1_15,
-    PIO1_16,
-    PIO1_17,
-    PIO1_18,
-    PIO1_19,
-    PIO1_20,
-    PIO1_21,
-    PIO1_22,
-    PIO1_23,
-    PIO1_24,
-    PIO1_25,
-    PIO1_26,
-    PIO1_27,
-    PIO1_28,
-    PIO1_29,
-    PIO1_30,
-    PIO1_31,
+    peripherals
 }
 
 /// HAL configuration for the NXP board.
@@ -93,3 +97,20 @@ pub mod config {
     #[derive(Default)]
     pub struct Config {}
 }
+
+#[allow(unused)]
+struct BitIter(u32);
+
+impl Iterator for BitIter {
+    type Item = u32;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        match self.0.trailing_zeros() {
+            32 => None,
+            b => {
+                self.0 &= !(1 << b);
+                Some(b)
+            }
+        }
+    }
+}
diff --git a/embassy-nxp/src/pint.rs b/embassy-nxp/src/pint.rs
index 8d6dc1277..ff414b4e6 100644
--- a/embassy-nxp/src/pint.rs
+++ b/embassy-nxp/src/pint.rs
@@ -7,9 +7,8 @@ use core::task::{Context, Poll};
 use critical_section::Mutex;
 use embassy_sync::waitqueue::AtomicWaker;
 
-use crate::gpio::{self, AnyPin, Level, SealedPin};
+use crate::gpio::{self, inputmux_reg, pint_reg, syscon_reg, AnyPin, Level, SealedPin};
 use crate::pac::interrupt;
-use crate::pac_utils::*;
 use crate::Peri;
 
 struct PinInterrupt {
@@ -102,6 +101,8 @@ pub(crate) fn init() {
         crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT6);
         crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT7);
     };
+
+    info!("Pin interrupts initialized");
 }
 
 #[must_use = "futures do nothing unless you `.await` or poll them"]
diff --git a/embassy-nxp/src/time_driver/pit.rs b/embassy-nxp/src/time_driver/pit.rs
new file mode 100644
index 000000000..985e5e815
--- /dev/null
+++ b/embassy-nxp/src/time_driver/pit.rs
@@ -0,0 +1,187 @@
+//! Time driver using Periodic Interrupt Timer (PIT)
+//!
+//! This driver is used with the iMXRT1xxx parts.
+//!
+//! The PIT is run in lifetime mode. Timer 1 is chained to timer 0 to provide a free-running 64-bit timer.
+//! The 64-bit timer is used to track how many ticks since boot.
+//!
+//! Timer 2 counts how many ticks there are within the current u32::MAX tick period. Timer 2 is restarted when
+//! a new alarm is set (or every u32::MAX ticks). One caveat is that an alarm could be a few ticks late due to
+//! restart. However the Cortex-M7 cores run at 500 MHz easily and the PIT will generally run at 1 MHz or lower.
+//! Along with the fact that scheduling an alarm takes a critical section worst case an alarm may be a few
+//! microseconds late.
+//!
+//! All PIT timers are clocked in lockstep, so the late start will not cause the now() count to drift.
+
+use core::cell::{Cell, RefCell};
+use core::task::Waker;
+
+use critical_section::{CriticalSection, Mutex};
+use embassy_hal_internal::interrupt::InterruptExt;
+use embassy_time_driver::Driver as _;
+use embassy_time_queue_utils::Queue;
+
+use crate::pac::{self, interrupt};
+
+struct Driver {
+    alarm: Mutex<Cell<u64>>,
+    queue: Mutex<RefCell<Queue>>,
+}
+
+impl embassy_time_driver::Driver for Driver {
+    fn now(&self) -> u64 {
+        loop {
+            // Even though reading LTMR64H will latch LTMR64L if another thread preempts between any of the
+            // three reads and calls now() then the value in LTMR64L will be wrong when execution returns to
+            // thread which was preempted.
+            let hi = pac::PIT.ltmr64h().read().lth();
+            let lo = pac::PIT.ltmr64l().read().ltl();
+            let hi2 = pac::PIT.ltmr64h().read().lth();
+
+            if hi == hi2 {
+                // PIT timers always count down.
+                return u64::MAX - ((hi as u64) << 32 | (lo as u64));
+            }
+        }
+    }
+
+    fn schedule_wake(&self, at: u64, waker: &Waker) {
+        critical_section::with(|cs| {
+            let mut queue = self.queue.borrow(cs).borrow_mut();
+
+            if queue.schedule_wake(at, waker) {
+                let mut next = queue.next_expiration(self.now());
+
+                while !self.set_alarm(cs, next) {
+                    next = queue.next_expiration(self.now());
+                }
+            }
+        })
+    }
+}
+
+impl Driver {
+    fn init(&'static self) {
+        // Disable PIT clock during mux configuration.
+        pac::CCM.ccgr1().modify(|r| r.set_cg6(0b00));
+
+        // TODO: This forces the PIT to be driven by the oscillator. However that isn't the only option as you
+        // could divide the clock root by up to 64.
+        pac::CCM.cscmr1().modify(|r| {
+            // 1 MHz
+            r.set_perclk_podf(pac::ccm::vals::PerclkPodf::DIVIDE_24);
+            r.set_perclk_clk_sel(pac::ccm::vals::PerclkClkSel::PERCLK_CLK_SEL_1);
+        });
+
+        pac::CCM.ccgr1().modify(|r| r.set_cg6(0b11));
+
+        // Disable clock during init.
+        //
+        // It is important that the PIT clock is prepared to not exceed limit (50 MHz on RT1011), or else
+        // you will need to recover the device with boot mode switches when using any PIT registers.
+        pac::PIT.mcr().modify(|w| {
+            w.set_mdis(true);
+        });
+
+        pac::PIT.timer(0).ldval().write_value(u32::MAX);
+        pac::PIT.timer(1).ldval().write_value(u32::MAX);
+        pac::PIT.timer(2).ldval().write_value(0);
+        pac::PIT.timer(3).ldval().write_value(0);
+
+        pac::PIT.timer(1).tctrl().write(|w| {
+            // In lifetime mode, timer 1 is chained to timer 0 to form a 64-bit timer.
+            w.set_chn(true);
+            w.set_ten(true);
+            w.set_tie(false);
+        });
+
+        pac::PIT.timer(0).tctrl().write(|w| {
+            w.set_chn(false);
+            w.set_ten(true);
+            w.set_tie(false);
+        });
+
+        pac::PIT.timer(2).tctrl().write(|w| {
+            w.set_tie(true);
+        });
+
+        unsafe { interrupt::PIT.enable() };
+
+        pac::PIT.mcr().write(|w| {
+            w.set_mdis(false);
+        });
+    }
+
+    fn set_alarm(&self, cs: CriticalSection, timestamp: u64) -> bool {
+        let alarm = self.alarm.borrow(cs);
+        alarm.set(timestamp);
+
+        let timer = pac::PIT.timer(2);
+        let now = self.now();
+
+        if timestamp <= now {
+            alarm.set(u64::MAX);
+
+            return false;
+        }
+
+        timer.tctrl().modify(|x| x.set_ten(false));
+        timer.tflg().modify(|x| x.set_tif(true));
+
+        // If the next alarm happens in more than u32::MAX cycles then the alarm will be restarted later.
+        timer.ldval().write_value((timestamp - now) as u32);
+        timer.tctrl().modify(|x| x.set_ten(true));
+
+        true
+    }
+
+    fn trigger_alarm(&self, cs: CriticalSection) {
+        let mut next = self.queue.borrow_ref_mut(cs).next_expiration(self.now());
+
+        while !self.set_alarm(cs, next) {
+            next = self.queue.borrow_ref_mut(cs).next_expiration(self.now());
+        }
+    }
+
+    fn on_interrupt(&self) {
+        critical_section::with(|cs| {
+            let timer = pac::PIT.timer(2);
+            let alarm = self.alarm.borrow(cs);
+            let interrupted = timer.tflg().read().tif();
+            timer.tflg().write(|r| r.set_tif(true));
+
+            if interrupted {
+                // A new load value will not apply until the next timer expiration.
+                //
+                // The expiry may be up to u32::MAX cycles away, so the timer must be restarted.
+                timer.tctrl().modify(|r| r.set_ten(false));
+
+                let now = self.now();
+                let timestamp = alarm.get();
+
+                if timestamp <= now {
+                    self.trigger_alarm(cs);
+                } else {
+                    // The alarm is not ready. Wait for u32::MAX cycles and check again or set the next alarm.
+                    timer.ldval().write_value((timestamp - now) as u32);
+                    timer.tctrl().modify(|r| r.set_ten(true));
+                }
+            }
+        });
+    }
+}
+
+embassy_time_driver::time_driver_impl!(static DRIVER: Driver = Driver {
+    alarm: Mutex::new(Cell::new(0)),
+    queue: Mutex::new(RefCell::new(Queue::new()))
+});
+
+pub(crate) fn init() {
+    DRIVER.init();
+}
+
+#[cfg(feature = "rt")]
+#[interrupt]
+fn PIT() {
+    DRIVER.on_interrupt();
+}
diff --git a/embassy-rp/CHANGELOG.md b/embassy-rp/CHANGELOG.md
index 7ac0a47cb..36e1ea9b4 100644
--- a/embassy-rp/CHANGELOG.md
+++ b/embassy-rp/CHANGELOG.md
@@ -5,7 +5,40 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## Unreleased
+<!-- next-header -->
+## Unreleased - ReleaseDate
+
+## 0.6.0 - 2025-07-16
+
+- update to latest embassy-usb-driver
+
+## 0.5.0 - 2025-07-15
+
+- Fix wrong `funcsel` on RP2350 gpout/gpin ([#3975](https://github.com/embassy-rs/embassy/pull/3975))
+- Fix potential race condition in `ADC::wait_for_ready` ([#4012](https://github.com/embassy-rs/embassy/pull/4012))
+- `flash`: rename `BOOTROM_BASE` to `BOOTRAM_BASE` ([#4014](https://github.com/embassy-rs/embassy/pull/4014))
+- Remove `Peripheral` trait & rename `PeripheralRef` to `Peri` ([#3999](https://github.com/embassy-rs/embassy/pull/3999))
+- Fix watchdog count on RP235x ([#4021](https://github.com/embassy-rs/embassy/pull/4021))
+- I2C: ensure that wakers are registered before checking status of `wait_on` helpers ([#4043](https://github.com/embassy-rs/embassy/pull/4043))
+- Modify `Uarte` and `BufferedUarte` initialization to take pins before interrupts ([#3983](https://github.com/embassy-rs/embassy/pull/3983))
+- `uart`: increase RX FIFO watermark from 1/8 to 7/8 ([#4055](https://github.com/embassy-rs/embassy/pull/4055))
+- Add `spinlock_mutex` ([#4017](https://github.com/embassy-rs/embassy/pull/4017))
+- Enable input mode for PWM pins on RP235x and disable it on drop ([#4093](https://github.com/embassy-rs/embassy/pull/4093))
+- Add `impl rand_core::CryptoRng for Trng` ([#4096](https://github.com/embassy-rs/embassy/pull/4096))
+- `pwm`: enable pull-down resistors for pins in `Drop` implementation ([#4115](https://github.com/embassy-rs/embassy/pull/4115))
+- Rewrite PIO onewire implementation ([#4128](https://github.com/embassy-rs/embassy/pull/4128))
+- Implement RP2040 overclocking ([#4150](https://github.com/embassy-rs/embassy/pull/4150))
+- Implement RP235x overclocking ([#4187](https://github.com/embassy-rs/embassy/pull/4187))
+- `trng`: improve error handling ([#4139](https://github.com/embassy-rs/embassy/pull/4139))
+- Remove `<T: Instance>` from `Uart` and `BufferedUart` ([#4155](https://github.com/embassy-rs/embassy/pull/4155))
+- Make bit-depth of I2S PIO program configurable ([#4193](https://github.com/embassy-rs/embassy/pull/4193))
+- Add the possibility to document `bind_interrupts` `struct`s ([#4206](https://github.com/embassy-rs/embassy/pull/4206))
+- Add missing `Debug` and `defmt::Format` `derive`s for ADC & `AnyPin` ([#4205](https://github.com/embassy-rs/embassy/pull/4205))
+- Add `rand-core` v0.9 support ([#4217](https://github.com/embassy-rs/embassy/pull/4217))
+- Update `embassy-sync` to v0.7.0 ([#4234](https://github.com/embassy-rs/embassy/pull/4234))
+- Add compatibility with ws2812 leds that have 4 addressable lights ([#4236](https://github.com/embassy-rs/embassy/pull/4236))
+- Implement input/output inversion ([#4237](https://github.com/embassy-rs/embassy/pull/4237))
+- Add `multicore::current_core` API ([#4362](https://github.com/embassy-rs/embassy/pull/4362))
 
 ## 0.4.0 - 2025-03-09
 
diff --git a/embassy-rp/Cargo.toml b/embassy-rp/Cargo.toml
index 5df9e154c..dcf4e7178 100644
--- a/embassy-rp/Cargo.toml
+++ b/embassy-rp/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-rp"
-version = "0.4.0"
+version = "0.6.0"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "Embassy Hardware Abstraction Layer (HAL) for the Raspberry Pi RP2040 or RP235x microcontroller"
@@ -141,9 +141,9 @@ embassy-time-driver = { version = "0.2", path = "../embassy-time-driver", option
 embassy-time-queue-utils = { version = "0.1", path = "../embassy-time-queue-utils", optional = true }
 embassy-time = { version = "0.4.0", path = "../embassy-time" }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
-embassy-hal-internal = { version = "0.2.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-2"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../embassy-embedded-hal" }
-embassy-usb-driver = { version = "0.1.0", path = "../embassy-usb-driver" }
+embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-2"] }
+embassy-embedded-hal = { version = "0.3.1", path = "../embassy-embedded-hal" }
+embassy-usb-driver = { version = "0.2.0", path = "../embassy-usb-driver" }
 atomic-polyfill = "1.0.1"
 defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.14", optional = true }
diff --git a/embassy-rp/release.toml b/embassy-rp/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/embassy-rp/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/embassy-rp/src/flash.rs b/embassy-rp/src/flash.rs
index ef1cd9212..8c809090e 100644
--- a/embassy-rp/src/flash.rs
+++ b/embassy-rp/src/flash.rs
@@ -482,7 +482,11 @@ mod ram_helpers {
     /// # Safety
     ///
     /// `boot2` must contain a valid 2nd stage boot loader which can be called to re-initialize XIP mode
-    unsafe fn flash_function_pointers_with_boot2(erase: bool, write: bool, boot2: &[u32; 64]) -> FlashFunctionPointers {
+    unsafe fn flash_function_pointers_with_boot2(
+        erase: bool,
+        write: bool,
+        boot2: &[u32; 64],
+    ) -> FlashFunctionPointers<'_> {
         let boot2_fn_ptr = (boot2 as *const u32 as *const u8).offset(1);
         let boot2_fn: unsafe extern "C" fn() -> () = core::mem::transmute(boot2_fn_ptr);
         FlashFunctionPointers {
diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs
index 9b5faac15..f79bf8948 100644
--- a/embassy-rp/src/gpio.rs
+++ b/embassy-rp/src/gpio.rs
@@ -26,6 +26,7 @@ static QSPI_WAKERS: [AtomicWaker; QSPI_PIN_COUNT] = [const { AtomicWaker::new()
 
 /// Represents a digital input or output level.
 #[derive(Debug, Eq, PartialEq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Level {
     /// Logical low.
     Low,
@@ -53,6 +54,7 @@ impl From<Level> for bool {
 
 /// Represents a pull setting for an input.
 #[derive(Debug, Clone, Copy, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Pull {
     /// No pull.
     None,
@@ -64,6 +66,7 @@ pub enum Pull {
 
 /// Drive strength of an output
 #[derive(Debug, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Drive {
     /// 2 mA drive.
     _2mA,
@@ -76,6 +79,7 @@ pub enum Drive {
 }
 /// Slew rate of an output
 #[derive(Debug, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum SlewRate {
     /// Fast slew rate.
     Fast,
@@ -85,6 +89,7 @@ pub enum SlewRate {
 
 /// A GPIO bank with up to 32 pins.
 #[derive(Debug, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Bank {
     /// Bank 0.
     Bank0 = 0,
@@ -108,6 +113,8 @@ pub struct DormantWakeConfig {
 }
 
 /// GPIO input driver.
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Input<'d> {
     pin: Flex<'d>,
 }
@@ -358,6 +365,8 @@ impl<'d> Future for InputFuture<'d> {
 }
 
 /// GPIO output driver.
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Output<'d> {
     pin: Flex<'d>,
 }
@@ -445,6 +454,8 @@ impl<'d> Output<'d> {
 }
 
 /// GPIO output open-drain.
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct OutputOpenDrain<'d> {
     pin: Flex<'d>,
 }
@@ -592,6 +603,8 @@ impl<'d> OutputOpenDrain<'d> {
 /// This pin can be either an input or output pin. The output level register bit will remain
 /// set while not in output mode, so the pin's level will be 'remembered' when it is not in output
 /// mode.
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Flex<'d> {
     pin: Peri<'d, AnyPin>,
 }
@@ -864,6 +877,8 @@ impl<'d> Drop for Flex<'d> {
 }
 
 /// Dormant wake driver.
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct DormantWake<'w> {
     pin: Peri<'w, AnyPin>,
     cfg: DormantWakeConfig,
diff --git a/embassy-rp/src/i2c.rs b/embassy-rp/src/i2c.rs
index a983b7bc3..172193a07 100644
--- a/embassy-rp/src/i2c.rs
+++ b/embassy-rp/src/i2c.rs
@@ -76,6 +76,7 @@ impl Default for Config {
 pub const FIFO_SIZE: u8 = 16;
 
 /// I2C driver.
+#[derive(Debug)]
 pub struct I2c<'d, T: Instance, M: Mode> {
     phantom: PhantomData<(&'d mut T, M)>,
 }
diff --git a/embassy-rp/src/lib.rs b/embassy-rp/src/lib.rs
index f3c5a35bb..eb497de1a 100644
--- a/embassy-rp/src/lib.rs
+++ b/embassy-rp/src/lib.rs
@@ -189,11 +189,13 @@ macro_rules! bind_interrupts {
             #[no_mangle]
             $(#[cfg($cond_irq)])?
             unsafe extern "C" fn $irq() {
-                $(
-                    $(#[cfg($cond_handler)])?
-                    <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
+                unsafe {
+                    $(
+                        $(#[cfg($cond_handler)])?
+                        <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
 
-                )*
+                    )*
+                }
             }
 
             $(#[cfg($cond_irq)])?
@@ -567,7 +569,7 @@ unsafe fn install_stack_guard(stack_bottom: *mut usize) -> Result<(), ()> {
     unsafe {
         core.MPU.ctrl.write(5); // enable mpu with background default map
         core.MPU.rbar.write(stack_bottom as u32 & !0xff); // set address
-        core.MPU.rlar.write(1); // enable region
+        core.MPU.rlar.write(((stack_bottom as usize + 255) as u32) | 1);
     }
     Ok(())
 }
diff --git a/embassy-rp/src/multicore.rs b/embassy-rp/src/multicore.rs
index d10b6837c..64065fcba 100644
--- a/embassy-rp/src/multicore.rs
+++ b/embassy-rp/src/multicore.rs
@@ -57,6 +57,26 @@ const PAUSE_TOKEN: u32 = 0xDEADBEEF;
 const RESUME_TOKEN: u32 = !0xDEADBEEF;
 static IS_CORE1_INIT: AtomicBool = AtomicBool::new(false);
 
+/// Represents a partiticular CPU core (SIO_CPUID)
+#[derive(Debug, PartialEq, Eq, Clone, Copy, Hash)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(u8)]
+pub enum CoreId {
+    /// Core 0
+    Core0 = 0x0,
+    /// Core 1
+    Core1 = 0x1,
+}
+
+/// Gets which core we are currently executing from
+pub fn current_core() -> CoreId {
+    if pac::SIO.cpuid().read() == 0 {
+        CoreId::Core0
+    } else {
+        CoreId::Core1
+    }
+}
+
 #[inline(always)]
 unsafe fn core1_setup(stack_bottom: *mut usize) {
     if install_stack_guard(stack_bottom).is_err() {
diff --git a/embassy-rp/src/relocate.rs b/embassy-rp/src/relocate.rs
index 34487819f..6ff40ddd7 100644
--- a/embassy-rp/src/relocate.rs
+++ b/embassy-rp/src/relocate.rs
@@ -39,7 +39,7 @@ pub struct RelocatedProgram<'a, const PROGRAM_SIZE: usize> {
 }
 
 impl<'a, const PROGRAM_SIZE: usize> RelocatedProgram<'a, PROGRAM_SIZE> {
-    pub fn new_with_origin(program: &Program<PROGRAM_SIZE>, origin: u8) -> RelocatedProgram<PROGRAM_SIZE> {
+    pub fn new_with_origin(program: &Program<PROGRAM_SIZE>, origin: u8) -> RelocatedProgram<'_, PROGRAM_SIZE> {
         RelocatedProgram { program, origin }
     }
 
diff --git a/embassy-rp/src/rom_data/mod.rs b/embassy-rp/src/rom_data/mod.rs
index e5fcf8e3c..a4aba5737 100644
--- a/embassy-rp/src/rom_data/mod.rs
+++ b/embassy-rp/src/rom_data/mod.rs
@@ -1,29 +1,29 @@
 #![cfg_attr(
     feature = "rp2040",
     doc = r"
-//! Functions and data from the RPI Bootrom.
-//!
-//! From the [RP2040 datasheet](https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf), Section 2.8.2.1:
-//!
-//! > The Bootrom contains a number of public functions that provide useful
-//! > RP2040 functionality that might be needed in the absence of any other code
-//! > on the device, as well as highly optimized versions of certain key
-//! > functionality that would otherwise have to take up space in most user
-//! > binaries.
+Functions and data from the RPI Bootrom.
+
+From the [RP2040 datasheet](https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf), Section 2.8.2.1:
+
+> The Bootrom contains a number of public functions that provide useful
+> RP2040 functionality that might be needed in the absence of any other code
+> on the device, as well as highly optimized versions of certain key
+> functionality that would otherwise have to take up space in most user
+> binaries.
 "
 )]
 #![cfg_attr(
     feature = "_rp235x",
     doc = r"
-//! Functions and data from the RPI Bootrom.
-//!
-//! From [Section 5.4](https://rptl.io/rp2350-datasheet#section_bootrom) of the
-//! RP2350 datasheet:
-//!
-//! > Whilst some ROM space is dedicated to the implementation of the boot
-//! > sequence and USB/UART boot interfaces, the bootrom also contains public
-//! > functions that provide useful RP2350 functionality that may be useful for
-//! > any code or runtime running on the device
+Functions and data from the RPI Bootrom.
+
+From [Section 5.4](https://rptl.io/rp2350-datasheet#section_bootrom) of the
+RP2350 datasheet:
+
+> Whilst some ROM space is dedicated to the implementation of the boot
+> sequence and USB/UART boot interfaces, the bootrom also contains public
+> functions that provide useful RP2350 functionality that may be useful for
+> any code or runtime running on the device
 "
 )]
 
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index c3a15fda5..6f4e2ee07 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -495,52 +495,58 @@ impl<'d> UartRx<'d, Async> {
         unreachable!("unrecognized rx error");
     }
 
-    /// Read from the UART, waiting for a line break.
+    /// Read from the UART, waiting for a break.
     ///
     /// We read until one of the following occurs:
     ///
-    /// * We read `buffer.len()` bytes without a line break
+    /// * We read `buffer.len()` bytes without a break
     ///     * returns `Err(ReadToBreakError::MissingBreak(buffer.len()))`
-    /// * We read `n` bytes then a line break occurs
+    /// * We read `n` bytes then a break occurs
     ///     * returns `Ok(n)`
-    /// * We encounter some error OTHER than a line break
+    /// * We encounter some error OTHER than a break
     ///     * returns `Err(ReadToBreakError::Other(error))`
     ///
     /// **NOTE**: you MUST provide a buffer one byte larger than your largest expected
     /// message to reliably detect the framing on one single call to `read_to_break()`.
     ///
-    /// * If you expect a message of 20 bytes + line break, and provide a 20-byte buffer:
+    /// * If you expect a message of 20 bytes + break, and provide a 20-byte buffer:
     ///     * The first call to `read_to_break()` will return `Err(ReadToBreakError::MissingBreak(20))`
-    ///     * The next call to `read_to_break()` will immediately return `Ok(0)`, from the "stale" line break
-    /// * If you expect a message of 20 bytes + line break, and provide a 21-byte buffer:
+    ///     * The next call to `read_to_break()` will immediately return `Ok(0)`, from the "stale" break
+    /// * If you expect a message of 20 bytes + break, and provide a 21-byte buffer:
     ///     * The first call to `read_to_break()` will return `Ok(20)`.
     ///     * The next call to `read_to_break()` will work as expected
+    ///
+    /// **NOTE**: In the UART context, a break refers to a break condition (the line being held low for
+    /// for longer than a single character), not an ASCII line break.
     pub async fn read_to_break(&mut self, buffer: &mut [u8]) -> Result<usize, ReadToBreakError> {
         self.read_to_break_with_count(buffer, 0).await
     }
 
-    /// Read from the UART, waiting for a line break as soon as at least `min_count` bytes have been read.
+    /// Read from the UART, waiting for a break as soon as at least `min_count` bytes have been read.
     ///
     /// We read until one of the following occurs:
     ///
-    /// * We read `buffer.len()` bytes without a line break
+    /// * We read `buffer.len()` bytes without a break
     ///     * returns `Err(ReadToBreakError::MissingBreak(buffer.len()))`
-    /// * We read `n > min_count` bytes then a line break occurs
+    /// * We read `n > min_count` bytes then a break occurs
     ///     * returns `Ok(n)`
-    /// * We encounter some error OTHER than a line break
+    /// * We encounter some error OTHER than a break
     ///     * returns `Err(ReadToBreakError::Other(error))`
     ///
-    /// If a line break occurs before `min_count` bytes have been read, the break will be ignored and the read will continue
+    /// If a break occurs before `min_count` bytes have been read, the break will be ignored and the read will continue
     ///
     /// **NOTE**: you MUST provide a buffer one byte larger than your largest expected
     /// message to reliably detect the framing on one single call to `read_to_break()`.
     ///
-    /// * If you expect a message of 20 bytes + line break, and provide a 20-byte buffer:
+    /// * If you expect a message of 20 bytes + break, and provide a 20-byte buffer:
     ///     * The first call to `read_to_break()` will return `Err(ReadToBreakError::MissingBreak(20))`
     ///     * The next call to `read_to_break()` will immediately return `Ok(0)`, from the "stale" line break
-    /// * If you expect a message of 20 bytes + line break, and provide a 21-byte buffer:
+    /// * If you expect a message of 20 bytes + break, and provide a 21-byte buffer:
     ///     * The first call to `read_to_break()` will return `Ok(20)`.
     ///     * The next call to `read_to_break()` will work as expected
+    ///
+    /// **NOTE**: In the UART context, a break refers to a break condition (the line being held low for
+    /// for longer than a single character), not an ASCII line break.
     pub async fn read_to_break_with_count(
         &mut self,
         buffer: &mut [u8],
diff --git a/embassy-rp/src/usb.rs b/embassy-rp/src/usb.rs
index 96541ade6..671ecbd32 100644
--- a/embassy-rp/src/usb.rs
+++ b/embassy-rp/src/usb.rs
@@ -153,6 +153,7 @@ impl<'d, T: Instance> Driver<'d, T> {
     fn alloc_endpoint<D: Dir>(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Endpoint<'d, T, D>, driver::EndpointAllocError> {
@@ -169,12 +170,25 @@ impl<'d, T: Instance> Driver<'d, T> {
             Direction::In => &mut self.ep_in,
         };
 
-        let index = alloc.iter_mut().enumerate().find(|(i, ep)| {
-            if *i == 0 {
-                return false; // reserved for control pipe
+        let index = if let Some(addr) = ep_addr {
+            // Use the specified endpoint address
+            let requested_index = addr.index();
+            if requested_index == 0 || requested_index >= EP_COUNT {
+                return Err(EndpointAllocError);
             }
-            !ep.used
-        });
+            if alloc[requested_index].used {
+                return Err(EndpointAllocError);
+            }
+            Some((requested_index, &mut alloc[requested_index]))
+        } else {
+            // Find any available endpoint
+            alloc.iter_mut().enumerate().find(|(i, ep)| {
+                if *i == 0 {
+                    return false; // reserved for control pipe
+                }
+                !ep.used
+            })
+        };
 
         let (index, ep) = index.ok_or(EndpointAllocError)?;
         assert!(!ep.used);
@@ -299,19 +313,21 @@ impl<'d, T: Instance> driver::Driver<'d> for Driver<'d, T> {
     fn alloc_endpoint_in(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointIn, driver::EndpointAllocError> {
-        self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
+        self.alloc_endpoint(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn alloc_endpoint_out(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointOut, driver::EndpointAllocError> {
-        self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
+        self.alloc_endpoint(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn start(self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
diff --git a/embassy-stm32-wpan/Cargo.toml b/embassy-stm32-wpan/Cargo.toml
index b749625aa..a16aa4b54 100644
--- a/embassy-stm32-wpan/Cargo.toml
+++ b/embassy-stm32-wpan/Cargo.toml
@@ -23,8 +23,8 @@ embassy-stm32 = { version = "0.2.0", path = "../embassy-stm32" }
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
 embassy-time = { version = "0.4.0", path = "../embassy-time", optional = true }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
-embassy-hal-internal = { version = "0.2.0", path = "../embassy-hal-internal" }
-embassy-embedded-hal = { version = "0.3.0", path = "../embassy-embedded-hal" }
+embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal" }
+embassy-embedded-hal = { version = "0.3.1", path = "../embassy-embedded-hal" }
 embassy-net-driver = { version = "0.2.0", path = "../embassy-net-driver", optional=true }
 
 defmt = { version = "1.0.1", optional = true }
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index b6781905e..c4c2cd013 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased
 - Modify BufferedUart initialization to take pins before interrupts ([#3983](https://github.com/embassy-rs/embassy/pull/3983))
 - Added a 'single-bank' and a 'dual-bank' feature so chips with configurable flash bank setups are be supported in embassy ([#4125](https://github.com/embassy-rs/embassy/pull/4125))
+- Add automatic setting of remap bits when using alternate DMA channels on STM32F0 and STM32F3 devices ([#3653](https://github.com/embassy-rs/embassy/pull/3653))
 
 ## 0.2.0 - 2025-01-10
 
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 034f51df9..02e75733e 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -53,11 +53,11 @@ embassy-time = { version = "0.4.0", path = "../embassy-time", optional = true }
 embassy-time-driver = { version = "0.2", path = "../embassy-time-driver", optional = true }
 embassy-time-queue-utils = { version = "0.1", path = "../embassy-time-queue-utils", optional = true }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
-embassy-hal-internal = { version = "0.2.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-4"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../embassy-embedded-hal", default-features = false }
+embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-4"] }
+embassy-embedded-hal = { version = "0.3.1", path = "../embassy-embedded-hal", default-features = false }
 embassy-net-driver = { version = "0.2.0", path = "../embassy-net-driver" }
-embassy-usb-driver = { version = "0.1.0", path = "../embassy-usb-driver" }
-embassy-usb-synopsys-otg = { version = "0.2.0", path = "../embassy-usb-synopsys-otg" }
+embassy-usb-driver = { version = "0.2.0", path = "../embassy-usb-driver" }
+embassy-usb-synopsys-otg = { version = "0.3.0", path = "../embassy-usb-synopsys-otg" }
 embassy-executor = { version = "0.7.0", path = "../embassy-executor", optional = true }
 
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
@@ -81,7 +81,7 @@ futures-util = { version = "0.3.30", default-features = false }
 sdio-host = "0.9.0"
 critical-section = "1.1"
 #stm32-metapac = { version = "16" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-27ef8fba3483187e852eaf3796d827259f61e8ec" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9fc86ca7b3a8bc05182bf1ce3045602df1f5dce3" }
 
 vcell = "0.1.3"
 nb = "1.0.0"
@@ -110,7 +110,7 @@ proc-macro2 = "1.0.36"
 quote = "1.0.15"
 
 #stm32-metapac = { version = "16", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-27ef8fba3483187e852eaf3796d827259f61e8ec", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9fc86ca7b3a8bc05182bf1ce3045602df1f5dce3", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]
@@ -129,6 +129,7 @@ defmt = [
     "embassy-net-driver/defmt",
     "embassy-time?/defmt",
     "embassy-usb-synopsys-otg/defmt",
+    "stm32-metapac/defmt"
 ]
 
 exti = []
@@ -237,6 +238,47 @@ stm32c031g4 = [ "stm32-metapac/stm32c031g4" ]
 stm32c031g6 = [ "stm32-metapac/stm32c031g6" ]
 stm32c031k4 = [ "stm32-metapac/stm32c031k4" ]
 stm32c031k6 = [ "stm32-metapac/stm32c031k6" ]
+stm32c051c6 = [ "stm32-metapac/stm32c051c6" ]
+stm32c051c8 = [ "stm32-metapac/stm32c051c8" ]
+stm32c051d8 = [ "stm32-metapac/stm32c051d8" ]
+stm32c051f6 = [ "stm32-metapac/stm32c051f6" ]
+stm32c051f8 = [ "stm32-metapac/stm32c051f8" ]
+stm32c051g6 = [ "stm32-metapac/stm32c051g6" ]
+stm32c051g8 = [ "stm32-metapac/stm32c051g8" ]
+stm32c051k6 = [ "stm32-metapac/stm32c051k6" ]
+stm32c051k8 = [ "stm32-metapac/stm32c051k8" ]
+stm32c071c8 = [ "stm32-metapac/stm32c071c8" ]
+stm32c071cb = [ "stm32-metapac/stm32c071cb" ]
+stm32c071f8 = [ "stm32-metapac/stm32c071f8" ]
+stm32c071fb = [ "stm32-metapac/stm32c071fb" ]
+stm32c071g8 = [ "stm32-metapac/stm32c071g8" ]
+stm32c071gb = [ "stm32-metapac/stm32c071gb" ]
+stm32c071k8 = [ "stm32-metapac/stm32c071k8" ]
+stm32c071kb = [ "stm32-metapac/stm32c071kb" ]
+stm32c071r8 = [ "stm32-metapac/stm32c071r8" ]
+stm32c071rb = [ "stm32-metapac/stm32c071rb" ]
+stm32c091cb = [ "stm32-metapac/stm32c091cb" ]
+stm32c091cc = [ "stm32-metapac/stm32c091cc" ]
+stm32c091ec = [ "stm32-metapac/stm32c091ec" ]
+stm32c091fb = [ "stm32-metapac/stm32c091fb" ]
+stm32c091fc = [ "stm32-metapac/stm32c091fc" ]
+stm32c091gb = [ "stm32-metapac/stm32c091gb" ]
+stm32c091gc = [ "stm32-metapac/stm32c091gc" ]
+stm32c091kb = [ "stm32-metapac/stm32c091kb" ]
+stm32c091kc = [ "stm32-metapac/stm32c091kc" ]
+stm32c091rb = [ "stm32-metapac/stm32c091rb" ]
+stm32c091rc = [ "stm32-metapac/stm32c091rc" ]
+stm32c092cb = [ "stm32-metapac/stm32c092cb" ]
+stm32c092cc = [ "stm32-metapac/stm32c092cc" ]
+stm32c092ec = [ "stm32-metapac/stm32c092ec" ]
+stm32c092fb = [ "stm32-metapac/stm32c092fb" ]
+stm32c092fc = [ "stm32-metapac/stm32c092fc" ]
+stm32c092gb = [ "stm32-metapac/stm32c092gb" ]
+stm32c092gc = [ "stm32-metapac/stm32c092gc" ]
+stm32c092kb = [ "stm32-metapac/stm32c092kb" ]
+stm32c092kc = [ "stm32-metapac/stm32c092kc" ]
+stm32c092rb = [ "stm32-metapac/stm32c092rb" ]
+stm32c092rc = [ "stm32-metapac/stm32c092rc" ]
 stm32f030c6 = [ "stm32-metapac/stm32f030c6" ]
 stm32f030c8 = [ "stm32-metapac/stm32f030c8" ]
 stm32f030cc = [ "stm32-metapac/stm32f030cc" ]
@@ -1634,6 +1676,24 @@ stm32wba55he = [ "stm32-metapac/stm32wba55he" ]
 stm32wba55hg = [ "stm32-metapac/stm32wba55hg" ]
 stm32wba55ue = [ "stm32-metapac/stm32wba55ue" ]
 stm32wba55ug = [ "stm32-metapac/stm32wba55ug" ]
+stm32wba62cg = [ "stm32-metapac/stm32wba62cg" ]
+stm32wba62ci = [ "stm32-metapac/stm32wba62ci" ]
+stm32wba62mg = [ "stm32-metapac/stm32wba62mg" ]
+stm32wba62mi = [ "stm32-metapac/stm32wba62mi" ]
+stm32wba62pg = [ "stm32-metapac/stm32wba62pg" ]
+stm32wba62pi = [ "stm32-metapac/stm32wba62pi" ]
+stm32wba63cg = [ "stm32-metapac/stm32wba63cg" ]
+stm32wba63ci = [ "stm32-metapac/stm32wba63ci" ]
+stm32wba64cg = [ "stm32-metapac/stm32wba64cg" ]
+stm32wba64ci = [ "stm32-metapac/stm32wba64ci" ]
+stm32wba65cg = [ "stm32-metapac/stm32wba65cg" ]
+stm32wba65ci = [ "stm32-metapac/stm32wba65ci" ]
+stm32wba65mg = [ "stm32-metapac/stm32wba65mg" ]
+stm32wba65mi = [ "stm32-metapac/stm32wba65mi" ]
+stm32wba65pg = [ "stm32-metapac/stm32wba65pg" ]
+stm32wba65pi = [ "stm32-metapac/stm32wba65pi" ]
+stm32wba65rg = [ "stm32-metapac/stm32wba65rg" ]
+stm32wba65ri = [ "stm32-metapac/stm32wba65ri" ]
 stm32wl54cc-cm4 = [ "stm32-metapac/stm32wl54cc-cm4", "_dual-core", "_core-cm4" ]
 stm32wl54cc-cm0p = [ "stm32-metapac/stm32wl54cc-cm0p", "_dual-core", "_core-cm0p" ]
 stm32wl54jc-cm4 = [ "stm32-metapac/stm32wl54jc-cm4", "_dual-core", "_core-cm4" ]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index bb5ef53d7..73860c64a 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -505,6 +505,13 @@ fn main() {
                 field: "CLK48SEL",
             },
         );
+        clock_gen.chained_muxes.insert(
+            "RFWKP",
+            &PeripheralRccRegister {
+                register: "CSR",
+                field: "RFWKPSEL",
+            },
+        );
     }
     if chip_name.starts_with("stm32f7") {
         clock_gen.chained_muxes.insert(
@@ -1090,21 +1097,21 @@ fn main() {
         (("fmc", "CLK"), quote!(crate::fmc::ClkPin)),
         (("fmc", "BA0"), quote!(crate::fmc::BA0Pin)),
         (("fmc", "BA1"), quote!(crate::fmc::BA1Pin)),
-        (("timer", "CH1"), quote!(crate::timer::Channel1Pin)),
-        (("timer", "CH1N"), quote!(crate::timer::Channel1ComplementaryPin)),
-        (("timer", "CH2"), quote!(crate::timer::Channel2Pin)),
-        (("timer", "CH2N"), quote!(crate::timer::Channel2ComplementaryPin)),
-        (("timer", "CH3"), quote!(crate::timer::Channel3Pin)),
-        (("timer", "CH3N"), quote!(crate::timer::Channel3ComplementaryPin)),
-        (("timer", "CH4"), quote!(crate::timer::Channel4Pin)),
-        (("timer", "CH4N"), quote!(crate::timer::Channel4ComplementaryPin)),
+        (("timer", "CH1"), quote!(crate::timer::TimerPin<Ch1>)),
+        (("timer", "CH1N"), quote!(crate::timer::TimerComplementaryPin<Ch1>)),
+        (("timer", "CH2"), quote!(crate::timer::TimerPin<Ch2>)),
+        (("timer", "CH2N"), quote!(crate::timer::TimerComplementaryPin<Ch2>)),
+        (("timer", "CH3"), quote!(crate::timer::TimerPin<Ch3>)),
+        (("timer", "CH3N"), quote!(crate::timer::TimerComplementaryPin<Ch3>)),
+        (("timer", "CH4"), quote!(crate::timer::TimerPin<Ch4>)),
+        (("timer", "CH4N"), quote!(crate::timer::TimerComplementaryPin<Ch4>)),
         (("timer", "ETR"), quote!(crate::timer::ExternalTriggerPin)),
-        (("timer", "BKIN"), quote!(crate::timer::BreakInputPin)),
-        (("timer", "BKIN_COMP1"), quote!(crate::timer::BreakInputComparator1Pin)),
-        (("timer", "BKIN_COMP2"), quote!(crate::timer::BreakInputComparator2Pin)),
-        (("timer", "BKIN2"), quote!(crate::timer::BreakInput2Pin)),
-        (("timer", "BKIN2_COMP1"), quote!(crate::timer::BreakInput2Comparator1Pin)),
-        (("timer", "BKIN2_COMP2"), quote!(crate::timer::BreakInput2Comparator2Pin)),
+        (("timer", "BKIN"), quote!(crate::timer::BreakInputPin<BkIn1>)),
+        (("timer", "BKIN_COMP1"), quote!(crate::timer::BreakInputComparator1Pin<BkIn1>)),
+        (("timer", "BKIN_COMP2"), quote!(crate::timer::BreakInputComparator2Pin<BkIn1>)),
+        (("timer", "BKIN2"), quote!(crate::timer::BreakInputPin<BkIn2>)),
+        (("timer", "BKIN2_COMP1"), quote!(crate::timer::BreakInputComparator1Pin<BkIn2>)),
+        (("timer", "BKIN2_COMP2"), quote!(crate::timer::BreakInputComparator2Pin<BkIn2>)),
         (("hrtim", "CHA1"), quote!(crate::hrtim::ChannelAPin)),
         (("hrtim", "CHA2"), quote!(crate::hrtim::ChannelAComplementaryPin)),
         (("hrtim", "CHB1"), quote!(crate::hrtim::ChannelBPin)),
@@ -1402,31 +1409,24 @@ fn main() {
                 }
 
                 if regs.kind == "opamp" {
-                    if pin.signal.starts_with("VP") {
-                        // Impl NonInvertingPin for the VP* signals (VP0, VP1, VP2, etc)
-                        let peri = format_ident!("{}", p.name);
-                        let pin_name = format_ident!("{}", pin.pin);
-                        let ch: u8 = pin.signal.strip_prefix("VP").unwrap().parse().unwrap();
-
-                        g.extend(quote! {
-                            impl_opamp_vp_pin!( #peri, #pin_name, #ch);
-                        })
-                    } else if pin.signal.starts_with("VINM") {
-                        // Impl NonInvertingPin for the VINM* signals ( VINM0, VINM1, etc)
-                        // STM32G4
-                        let peri = format_ident!("{}", p.name);
-                        let pin_name = format_ident!("{}", pin.pin);
-                        let ch: Result<u8, _> = pin.signal.strip_prefix("VINM").unwrap().parse();
-
-                        if let Ok(ch) = ch {
+                    let peri = format_ident!("{}", p.name);
+                    let pin_name = format_ident!("{}", pin.pin);
+                    if let Some(ch_str) = pin.signal.strip_prefix("VINP") {
+                        // Impl NonInvertingPin for VINP0, VINP1 etc.
+                        if let Ok(ch) = ch_str.parse::<u8>() {
+                            g.extend(quote! {
+                                impl_opamp_vp_pin!( #peri, #pin_name, #ch );
+                            });
+                        }
+                    } else if let Some(ch_str) = pin.signal.strip_prefix("VINM") {
+                        // Impl InvertingPin for VINM0, VINM1 etc.
+                        if let Ok(ch) = ch_str.parse::<u8>() {
                             g.extend(quote! {
                                 impl_opamp_vn_pin!( #peri, #pin_name, #ch);
-                            })
+                            });
                         }
                     } else if pin.signal == "VOUT" {
                         // Impl OutputPin for the VOUT pin
-                        let peri = format_ident!("{}", p.name);
-                        let pin_name = format_ident!("{}", pin.pin);
                         g.extend(quote! {
                             impl_opamp_vout_pin!( #peri, #pin_name );
                         })
@@ -1482,10 +1482,10 @@ fn main() {
         (("hash", "IN"), quote!(crate::hash::Dma)),
         (("cryp", "IN"), quote!(crate::cryp::DmaIn)),
         (("cryp", "OUT"), quote!(crate::cryp::DmaOut)),
-        (("timer", "CH1"), quote!(crate::timer::Ch1Dma)),
-        (("timer", "CH2"), quote!(crate::timer::Ch2Dma)),
-        (("timer", "CH3"), quote!(crate::timer::Ch3Dma)),
-        (("timer", "CH4"), quote!(crate::timer::Ch4Dma)),
+        (("timer", "CH1"), quote!(crate::timer::Dma<Ch1>)),
+        (("timer", "CH2"), quote!(crate::timer::Dma<Ch2>)),
+        (("timer", "CH3"), quote!(crate::timer::Dma<Ch3>)),
+        (("timer", "CH4"), quote!(crate::timer::Dma<Ch4>)),
         (("cordic", "WRITE"), quote!(crate::cordic::WriteDma)), // FIXME: stm32u5a crash on Cordic driver
         (("cordic", "READ"), quote!(crate::cordic::ReadDma)),   // FIXME: stm32u5a crash on Cordic driver
     ]
@@ -1497,6 +1497,10 @@ fn main() {
         signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma));
     }
 
+    if chip_name.starts_with("stm32wba") {
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma4));
+    }
+
     if chip_name.starts_with("stm32g4") {
         let line_number = chip_name.chars().skip(8).next().unwrap();
         if line_number == '3' || line_number == '4' {
@@ -1554,9 +1558,35 @@ fn main() {
                             quote!(())
                         };
 
+                        let mut remap = quote!();
+                        for remap_info in ch.remap {
+                            let register = format_ident!("{}", remap_info.register.to_lowercase());
+                            let setter = format_ident!("set_{}", remap_info.field.to_lowercase());
+
+                            let field_metadata = METADATA
+                                .peripherals
+                                .iter()
+                                .filter(|p| p.name == "SYSCFG")
+                                .flat_map(|p| p.registers.as_ref().unwrap().ir.fieldsets.iter())
+                                .filter(|f| f.name.eq_ignore_ascii_case(remap_info.register))
+                                .flat_map(|f| f.fields.iter())
+                                .find(|f| f.name.eq_ignore_ascii_case(remap_info.field))
+                                .unwrap();
+
+                            let value = if field_metadata.bit_size == 1 {
+                                let bool_value = format_ident!("{}", remap_info.value > 0);
+                                quote!(#bool_value)
+                            } else {
+                                let value = remap_info.value;
+                                quote!(#value.into())
+                            };
+
+                            remap.extend(quote!(crate::pac::SYSCFG.#register().modify(|w| w.#setter(#value));));
+                        }
+
                         let channel = format_ident!("{}", channel);
                         g.extend(quote! {
-                            dma_trait_impl!(#tr, #peri, #channel, #request);
+                            dma_trait_impl!(#tr, #peri, #channel, #request, {#remap});
                         });
                     }
                 }
@@ -1888,9 +1918,9 @@ fn main() {
     }
 
     g.extend(quote!(
-        pub fn gpio_block(n: usize) -> crate::pac::gpio::Gpio {{
-            unsafe {{ crate::pac::gpio::Gpio::from_ptr((#gpio_base + #gpio_stride*n) as _) }}
-        }}
+        pub fn gpio_block(n: usize) -> crate::pac::gpio::Gpio {
+            unsafe { crate::pac::gpio::Gpio::from_ptr((#gpio_base + #gpio_stride*n) as _) }
+        }
     ));
 
     // ========
diff --git a/embassy-stm32/src/adc/u5_adc4.rs b/embassy-stm32/src/adc/adc4.rs
index 1dd664366..31cbdc0d7 100644
--- a/embassy-stm32/src/adc/u5_adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -1,10 +1,19 @@
+#[cfg(stm32u5)]
+use pac::adc::vals::{Adc4Dmacfg as Dmacfg, Adc4Exten as Exten, Adc4OversamplingRatio as OversamplingRatio};
 #[allow(unused)]
-use pac::adc::vals::{Adc4Dmacfg, Adc4Exten, Adc4OversamplingRatio};
+#[cfg(stm32wba)]
+use pac::adc::vals::{Chselrmod, Cont, Dmacfg, Exten, OversamplingRatio, Ovss, Smpsel};
 
 use super::{blocking_delay_us, AdcChannel, AnyAdcChannel, RxDma4, SealedAdcChannel};
 use crate::dma::Transfer;
-pub use crate::pac::adc::regs::Adc4Chselrmod0;
+#[cfg(stm32u5)]
+pub use crate::pac::adc::regs::Adc4Chselrmod0 as Chselr;
+#[cfg(stm32wba)]
+pub use crate::pac::adc::regs::Chselr;
+#[cfg(stm32u5)]
 pub use crate::pac::adc::vals::{Adc4Presc as Presc, Adc4Res as Resolution, Adc4SampleTime as SampleTime};
+#[cfg(stm32wba)]
+pub use crate::pac::adc::vals::{Presc, Res as Resolution, SampleTime};
 use crate::time::Hertz;
 use crate::{pac, rcc, Peri};
 
@@ -67,12 +76,14 @@ impl<T: Instance> SealedAdcChannel<T> for Vcore {
     }
 }
 
+#[derive(Copy, Clone)]
 pub enum DacChannel {
     OUT1,
     OUT2,
 }
 
 /// Number of samples used for averaging.
+#[derive(Copy, Clone)]
 pub enum Averaging {
     Disabled,
     Samples2,
@@ -178,7 +189,7 @@ pub struct Adc4<'d, T: Instance> {
     adc: crate::Peri<'d, T>,
 }
 
-#[derive(Debug)]
+#[derive(Copy, Clone, Debug)]
 pub enum Adc4Error {
     InvalidSequence,
     DMAError,
@@ -242,17 +253,28 @@ impl<'d, T: Instance> Adc4<'d, T> {
     fn configure(&mut self) {
         // single conversion mode, software trigger
         T::regs().cfgr1().modify(|w| {
+            #[cfg(stm32u5)]
             w.set_cont(false);
+            #[cfg(stm32wba)]
+            w.set_cont(Cont::SINGLE);
             w.set_discen(false);
-            w.set_exten(Adc4Exten::DISABLED);
+            w.set_exten(Exten::DISABLED);
+            #[cfg(stm32u5)]
             w.set_chselrmod(false);
+            #[cfg(stm32wba)]
+            w.set_chselrmod(Chselrmod::ENABLE_INPUT);
         });
 
         // only use one channel at the moment
         T::regs().smpr().modify(|w| {
+            #[cfg(stm32u5)]
             for i in 0..24 {
                 w.set_smpsel(i, false);
             }
+            #[cfg(stm32wba)]
+            for i in 0..14 {
+                w.set_smpsel(i, Smpsel::SMP1);
+            }
         });
     }
 
@@ -275,6 +297,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
     }
 
     /// Enable reading the vbat internal channel.
+    #[cfg(stm32u5)]
     pub fn enable_vbat(&self) -> Vbat {
         T::regs().ccr().modify(|w| {
             w.set_vbaten(true);
@@ -289,6 +312,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
     }
 
     /// Enable reading the vbat internal channel.
+    #[cfg(stm32u5)]
     pub fn enable_dac_channel(&self, dac: DacChannel) -> Dac {
         let mux;
         match dac {
@@ -317,17 +341,38 @@ impl<'d, T: Instance> Adc4<'d, T> {
     }
 
     /// Set hardware averaging.
+    #[cfg(stm32u5)]
+    pub fn set_averaging(&mut self, averaging: Averaging) {
+        let (enable, samples, right_shift) = match averaging {
+            Averaging::Disabled => (false, OversamplingRatio::OVERSAMPLE2X, 0),
+            Averaging::Samples2 => (true, OversamplingRatio::OVERSAMPLE2X, 1),
+            Averaging::Samples4 => (true, OversamplingRatio::OVERSAMPLE4X, 2),
+            Averaging::Samples8 => (true, OversamplingRatio::OVERSAMPLE8X, 3),
+            Averaging::Samples16 => (true, OversamplingRatio::OVERSAMPLE16X, 4),
+            Averaging::Samples32 => (true, OversamplingRatio::OVERSAMPLE32X, 5),
+            Averaging::Samples64 => (true, OversamplingRatio::OVERSAMPLE64X, 6),
+            Averaging::Samples128 => (true, OversamplingRatio::OVERSAMPLE128X, 7),
+            Averaging::Samples256 => (true, OversamplingRatio::OVERSAMPLE256X, 8),
+        };
+
+        T::regs().cfgr2().modify(|w| {
+            w.set_ovsr(samples);
+            w.set_ovss(right_shift);
+            w.set_ovse(enable)
+        })
+    }
+    #[cfg(stm32wba)]
     pub fn set_averaging(&mut self, averaging: Averaging) {
         let (enable, samples, right_shift) = match averaging {
-            Averaging::Disabled => (false, Adc4OversamplingRatio::OVERSAMPLE2X, 0),
-            Averaging::Samples2 => (true, Adc4OversamplingRatio::OVERSAMPLE2X, 1),
-            Averaging::Samples4 => (true, Adc4OversamplingRatio::OVERSAMPLE4X, 2),
-            Averaging::Samples8 => (true, Adc4OversamplingRatio::OVERSAMPLE8X, 3),
-            Averaging::Samples16 => (true, Adc4OversamplingRatio::OVERSAMPLE16X, 4),
-            Averaging::Samples32 => (true, Adc4OversamplingRatio::OVERSAMPLE32X, 5),
-            Averaging::Samples64 => (true, Adc4OversamplingRatio::OVERSAMPLE64X, 6),
-            Averaging::Samples128 => (true, Adc4OversamplingRatio::OVERSAMPLE128X, 7),
-            Averaging::Samples256 => (true, Adc4OversamplingRatio::OVERSAMPLE256X, 8),
+            Averaging::Disabled => (false, OversamplingRatio::OVERSAMPLE2X, Ovss::SHIFT0),
+            Averaging::Samples2 => (true, OversamplingRatio::OVERSAMPLE2X, Ovss::SHIFT1),
+            Averaging::Samples4 => (true, OversamplingRatio::OVERSAMPLE4X, Ovss::SHIFT2),
+            Averaging::Samples8 => (true, OversamplingRatio::OVERSAMPLE8X, Ovss::SHIFT3),
+            Averaging::Samples16 => (true, OversamplingRatio::OVERSAMPLE16X, Ovss::SHIFT4),
+            Averaging::Samples32 => (true, OversamplingRatio::OVERSAMPLE32X, Ovss::SHIFT5),
+            Averaging::Samples64 => (true, OversamplingRatio::OVERSAMPLE64X, Ovss::SHIFT6),
+            Averaging::Samples128 => (true, OversamplingRatio::OVERSAMPLE128X, Ovss::SHIFT7),
+            Averaging::Samples256 => (true, OversamplingRatio::OVERSAMPLE256X, Ovss::SHIFT8),
         };
 
         T::regs().cfgr2().modify(|w| {
@@ -342,10 +387,20 @@ impl<'d, T: Instance> Adc4<'d, T> {
         channel.setup();
 
         // Select channel
-        T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
-        T::regs().chselrmod0().modify(|w| {
-            w.set_chsel(channel.channel() as usize, true);
-        });
+        #[cfg(stm32wba)]
+        {
+            T::regs().chselr().write_value(Chselr(0_u32));
+            T::regs().chselr().modify(|w| {
+                w.set_chsel0(channel.channel() as usize, true);
+            });
+        }
+        #[cfg(stm32u5)]
+        {
+            T::regs().chselrmod0().write_value(Chselr(0_u32));
+            T::regs().chselrmod0().modify(|w| {
+                w.set_chsel(channel.channel() as usize, true);
+            });
+        }
 
         // Reset interrupts
         T::regs().isr().modify(|reg| {
@@ -415,13 +470,19 @@ impl<'d, T: Instance> Adc4<'d, T> {
 
         T::regs().cfgr1().modify(|reg| {
             reg.set_dmaen(true);
-            reg.set_dmacfg(Adc4Dmacfg::ONE_SHOT);
+            reg.set_dmacfg(Dmacfg::ONE_SHOT);
+            #[cfg(stm32u5)]
             reg.set_chselrmod(false);
+            #[cfg(stm32wba)]
+            reg.set_chselrmod(Chselrmod::ENABLE_INPUT)
         });
 
         // Verify and activate sequence
         let mut prev_channel: i16 = -1;
-        T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
+        #[cfg(stm32wba)]
+        T::regs().chselr().write_value(Chselr(0_u32));
+        #[cfg(stm32u5)]
+        T::regs().chselrmod0().write_value(Chselr(0_u32));
         for channel in sequence {
             let channel_num = channel.channel;
             if channel_num as i16 <= prev_channel {
@@ -429,6 +490,11 @@ impl<'d, T: Instance> Adc4<'d, T> {
             };
             prev_channel = channel_num as i16;
 
+            #[cfg(stm32wba)]
+            T::regs().chselr().modify(|w| {
+                w.set_chsel0(channel.channel as usize, true);
+            });
+            #[cfg(stm32u5)]
             T::regs().chselrmod0().modify(|w| {
                 w.set_chsel(channel.channel as usize, true);
             });
diff --git a/embassy-stm32/src/adc/c0.rs b/embassy-stm32/src/adc/c0.rs
index 936ad7413..f5870801e 100644
--- a/embassy-stm32/src/adc/c0.rs
+++ b/embassy-stm32/src/adc/c0.rs
@@ -48,7 +48,7 @@ impl<T: Instance> SealedAdcChannel<T> for Temperature {
     }
 }
 
-#[derive(Debug)]
+#[derive(Copy, Clone, Debug)]
 pub enum Prescaler {
     NotDivided,
     DividedBy2,
@@ -138,6 +138,7 @@ impl<'a> defmt::Format for Prescaler {
 /// Number of samples used for averaging.
 /// TODO: Implement hardware averaging setting.
 #[allow(unused)]
+#[derive(Copy, Clone)]
 pub enum Averaging {
     Disabled,
     Samples2,
diff --git a/embassy-stm32/src/adc/f3_v1_1.rs b/embassy-stm32/src/adc/f3_v1_1.rs
index 944e971bb..84613078c 100644
--- a/embassy-stm32/src/adc/f3_v1_1.rs
+++ b/embassy-stm32/src/adc/f3_v1_1.rs
@@ -17,6 +17,7 @@ pub const VDDA_CALIB_MV: u32 = 3300;
 pub const ADC_MAX: u32 = (1 << 12) - 1;
 pub const VREF_INT: u32 = 1230;
 
+#[derive(Copy, Clone)]
 pub enum AdcPowerMode {
     AlwaysOn,
     DelayOff,
@@ -24,6 +25,7 @@ pub enum AdcPowerMode {
     DelayIdleOff,
 }
 
+#[derive(Copy, Clone)]
 pub enum Prescaler {
     Div1,
     Div2,
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 1fce3085a..43498966f 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -24,44 +24,31 @@ const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(60);
 #[cfg(stm32h7)]
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(50);
 
-#[cfg(stm32g4)]
-const VREF_CHANNEL: u8 = 18;
-#[cfg(stm32g4)]
-const TEMP_CHANNEL: u8 = 16;
-
-#[cfg(stm32h7)]
-const VREF_CHANNEL: u8 = 19;
-#[cfg(stm32h7)]
-const TEMP_CHANNEL: u8 = 18;
-
-// TODO this should be 14 for H7a/b/35
-const VBAT_CHANNEL: u8 = 17;
-
 // NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
 /// Internal voltage reference channel.
 pub struct VrefInt;
-impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> super::SealedAdcChannel<T> for VrefInt {
+impl<T: Instance + VrefChannel> AdcChannel<T> for VrefInt {}
+impl<T: Instance + VrefChannel> super::SealedAdcChannel<T> for VrefInt {
     fn channel(&self) -> u8 {
-        VREF_CHANNEL
+        T::CHANNEL
     }
 }
 
 /// Internal temperature channel.
 pub struct Temperature;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
+impl<T: Instance + TemperatureChannel> AdcChannel<T> for Temperature {}
+impl<T: Instance + TemperatureChannel> super::SealedAdcChannel<T> for Temperature {
     fn channel(&self) -> u8 {
-        TEMP_CHANNEL
+        T::CHANNEL
     }
 }
 
 /// Internal battery voltage channel.
 pub struct Vbat;
-impl<T: Instance> AdcChannel<T> for Vbat {}
-impl<T: Instance> super::SealedAdcChannel<T> for Vbat {
+impl<T: Instance + VBatChannel> AdcChannel<T> for Vbat {}
+impl<T: Instance + VBatChannel> super::SealedAdcChannel<T> for Vbat {
     fn channel(&self) -> u8 {
-        VBAT_CHANNEL
+        T::CHANNEL
     }
 }
 
@@ -234,7 +221,10 @@ impl<'d, T: Instance> Adc<'d, T> {
     }
 
     /// Enable reading the voltage reference internal channel.
-    pub fn enable_vrefint(&self) -> VrefInt {
+    pub fn enable_vrefint(&self) -> VrefInt
+    where
+        T: VrefChannel,
+    {
         T::common_regs().ccr().modify(|reg| {
             reg.set_vrefen(true);
         });
@@ -243,7 +233,10 @@ impl<'d, T: Instance> Adc<'d, T> {
     }
 
     /// Enable reading the temperature internal channel.
-    pub fn enable_temperature(&self) -> Temperature {
+    pub fn enable_temperature(&self) -> Temperature
+    where
+        T: TemperatureChannel,
+    {
         T::common_regs().ccr().modify(|reg| {
             reg.set_vsenseen(true);
         });
@@ -252,7 +245,10 @@ impl<'d, T: Instance> Adc<'d, T> {
     }
 
     /// Enable reading the vbat internal channel.
-    pub fn enable_vbat(&self) -> Vbat {
+    pub fn enable_vbat(&self) -> Vbat
+    where
+        T: VBatChannel,
+    {
         T::common_regs().ccr().modify(|reg| {
             reg.set_vbaten(true);
         });
@@ -519,3 +515,78 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
     }
 }
+
+/// Implemented for ADCs that have a Temperature channel
+pub trait TemperatureChannel {
+    const CHANNEL: u8;
+}
+/// Implemented for ADCs that have a Vref channel
+pub trait VrefChannel {
+    const CHANNEL: u8;
+}
+/// Implemented for ADCs that have a VBat channel
+pub trait VBatChannel {
+    const CHANNEL: u8;
+}
+
+#[cfg(stm32g4)]
+mod g4 {
+    pub use super::*;
+
+    impl TemperatureChannel for crate::peripherals::ADC1 {
+        const CHANNEL: u8 = 16;
+    }
+
+    impl VrefChannel for crate::peripherals::ADC1 {
+        const CHANNEL: u8 = 18;
+    }
+
+    impl VBatChannel for crate::peripherals::ADC1 {
+        const CHANNEL: u8 = 17;
+    }
+
+    #[cfg(peri_adc3_common)]
+    impl VrefChannel for crate::peripherals::ADC3 {
+        const CHANNEL: u8 = 18;
+    }
+
+    #[cfg(peri_adc3_common)]
+    impl VBatChannel for crate::peripherals::ADC3 {
+        const CHANNEL: u8 = 17;
+    }
+
+    #[cfg(not(stm32g4x1))]
+    impl VrefChannel for crate::peripherals::ADC4 {
+        const CHANNEL: u8 = 18;
+    }
+
+    #[cfg(not(stm32g4x1))]
+    impl TemperatureChannel for crate::peripherals::ADC5 {
+        const CHANNEL: u8 = 4;
+    }
+
+    #[cfg(not(stm32g4x1))]
+    impl VrefChannel for crate::peripherals::ADC5 {
+        const CHANNEL: u8 = 18;
+    }
+
+    #[cfg(not(stm32g4x1))]
+    impl VBatChannel for crate::peripherals::ADC5 {
+        const CHANNEL: u8 = 17;
+    }
+}
+
+// TODO this should look at each ADC individually and impl the correct channels
+#[cfg(stm32h7)]
+mod h7 {
+    impl<T: Instance> TemperatureChannel for T {
+        const CHANNEL: u8 = 18;
+    }
+    impl<T: Instance> VrefChannel for T {
+        const CHANNEL: u8 = 19;
+    }
+    impl<T: Instance> VBatChannel for T {
+        // TODO this should be 14 for H7a/b/35
+        const CHANNEL: u8 = 17;
+    }
+}
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index f46e87f38..778edc6f6 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -4,7 +4,7 @@
 #![allow(missing_docs)] // TODO
 #![cfg_attr(adc_f3_v2, allow(unused))]
 
-#[cfg(not(any(adc_f3_v2)))]
+#[cfg(not(any(adc_f3_v2, adc_wba)))]
 #[cfg_attr(adc_f1, path = "f1.rs")]
 #[cfg_attr(adc_f3, path = "f3.rs")]
 #[cfg_attr(adc_f3_v1_1, path = "f3_v1_1.rs")]
@@ -20,14 +20,14 @@ mod _version;
 use core::marker::PhantomData;
 
 #[allow(unused)]
-#[cfg(not(any(adc_f3_v2)))]
+#[cfg(not(any(adc_f3_v2, adc_wba)))]
 pub use _version::*;
 use embassy_hal_internal::{impl_peripheral, PeripheralType};
 #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
 use embassy_sync::waitqueue::AtomicWaker;
 
-#[cfg(adc_u5)]
-#[path = "u5_adc4.rs"]
+#[cfg(any(adc_u5, adc_wba))]
+#[path = "adc4.rs"]
 pub mod adc4;
 
 pub use crate::pac::adc::vals;
@@ -36,15 +36,18 @@ pub use crate::pac::adc::vals::Res as Resolution;
 pub use crate::pac::adc::vals::SampleTime;
 use crate::peripherals;
 
+#[cfg(not(adc_wba))]
 dma_trait!(RxDma, Instance);
 #[cfg(adc_u5)]
 dma_trait!(RxDma4, adc4::Instance);
+#[cfg(adc_wba)]
+dma_trait!(RxDma4, adc4::Instance);
 
 /// Analog to Digital driver.
 pub struct Adc<'d, T: Instance> {
     #[allow(unused)]
     adc: crate::Peri<'d, T>,
-    #[cfg(not(any(adc_f3_v2, adc_f3_v1_1)))]
+    #[cfg(not(any(adc_f3_v2, adc_f3_v1_1, adc_wba)))]
     sample_time: SampleTime,
 }
 
@@ -63,6 +66,7 @@ impl State {
 }
 
 trait SealedInstance {
+    #[cfg(not(adc_wba))]
     #[allow(unused)]
     fn regs() -> crate::pac::adc::Adc;
     #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
@@ -73,7 +77,7 @@ trait SealedInstance {
 }
 
 pub(crate) trait SealedAdcChannel<T> {
-    #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
+    #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
     fn setup(&mut self) {}
 
     #[allow(unused)]
@@ -110,7 +114,8 @@ pub(crate) fn blocking_delay_us(us: u32) {
     adc_h5,
     adc_h7rs,
     adc_u5,
-    adc_c0
+    adc_c0,
+    adc_wba,
 )))]
 #[allow(private_bounds)]
 pub trait Instance: SealedInstance + crate::PeripheralType {
@@ -132,7 +137,8 @@ pub trait Instance: SealedInstance + crate::PeripheralType {
     adc_h5,
     adc_h7rs,
     adc_u5,
-    adc_c0
+    adc_c0,
+    adc_wba,
 ))]
 #[allow(private_bounds)]
 pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeripheral {
@@ -144,7 +150,7 @@ pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeri
 pub trait AdcChannel<T>: SealedAdcChannel<T> + Sized {
     #[allow(unused_mut)]
     fn degrade_adc(mut self) -> AnyAdcChannel<T> {
-        #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
+        #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
         self.setup();
 
         AnyAdcChannel {
@@ -176,6 +182,36 @@ impl<T> AnyAdcChannel<T> {
         self.channel
     }
 }
+#[cfg(adc_wba)]
+foreach_adc!(
+    (ADC4, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::adc4::SealedInstance for peripherals::ADC4 {
+            fn regs() -> crate::pac::adc::Adc4 {
+                crate::pac::ADC4
+            }
+        }
+
+        impl crate::adc::adc4::Instance for peripherals::ADC4 {
+            type Interrupt = crate::_generated::peripheral_interrupts::ADC4::GLOBAL;
+        }
+    };
+
+    ($inst:ident, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::SealedInstance for peripherals::$inst {
+            fn regs() -> crate::pac::adc::Adc {
+                crate::pac::$inst
+            }
+
+            fn common_regs() -> crate::pac::adccommon::AdcCommon {
+                return crate::pac::$common_inst
+            }
+        }
+
+        impl crate::adc::Instance for peripherals::$inst {
+            type Interrupt = crate::_generated::peripheral_interrupts::$inst::GLOBAL;
+        }
+    };
+);
 
 #[cfg(adc_u5)]
 foreach_adc!(
@@ -208,15 +244,21 @@ foreach_adc!(
     };
 );
 
-#[cfg(not(adc_u5))]
+#[cfg(not(any(adc_u5, adc_wba)))]
 foreach_adc!(
     ($inst:ident, $common_inst:ident, $clock:ident) => {
         impl crate::adc::SealedInstance for peripherals::$inst {
+            #[cfg(not(adc_wba))]
             fn regs() -> crate::pac::adc::Adc {
                 crate::pac::$inst
             }
 
-            #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
+            #[cfg(adc_wba)]
+            fn regs() -> crate::pac::adc::Adc4 {
+                crate::pac::$inst
+            }
+
+            #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0, adc_u5, adc_wba)))]
             fn common_regs() -> crate::pac::adccommon::AdcCommon {
                 return crate::pac::$common_inst
             }
@@ -238,7 +280,7 @@ macro_rules! impl_adc_pin {
     ($inst:ident, $pin:ident, $ch:expr) => {
         impl crate::adc::AdcChannel<peripherals::$inst> for crate::Peri<'_, crate::peripherals::$pin> {}
         impl crate::adc::SealedAdcChannel<peripherals::$inst> for crate::Peri<'_, crate::peripherals::$pin> {
-            #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
+            #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
             fn setup(&mut self) {
                 <crate::peripherals::$pin as crate::gpio::SealedPin>::set_as_analog(self);
             }
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index fb6f5b7d0..7fe502da0 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -11,6 +11,9 @@ use crate::interrupt::typelevel::Interrupt;
 use crate::peripherals::ADC1;
 use crate::{interrupt, rcc, Peri};
 
+mod watchdog_v1;
+pub use watchdog_v1::WatchdogChannels;
+
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const VREF_INT: u32 = 1230;
 
@@ -21,8 +24,15 @@ pub struct InterruptHandler<T: Instance> {
 
 impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
     unsafe fn on_interrupt() {
-        if T::regs().isr().read().eoc() {
+        let isr = T::regs().isr().read();
+        let ier = T::regs().ier().read();
+        if ier.eocie() && isr.eoc() {
+            // eocie is set during adc.read()
             T::regs().ier().modify(|w| w.set_eocie(false));
+        } else if ier.awdie() && isr.awd() {
+            // awdie is set during adc.monitor_watchdog()
+            T::regs().cr().read().set_adstp(true);
+            T::regs().ier().modify(|w| w.set_awdie(false));
         } else {
             return;
         }
@@ -186,16 +196,21 @@ impl<'d, T: Instance> Adc<'d, T> {
 
         T::regs().dr().read().data()
     }
-}
 
-impl<'d, T: Instance> Drop for Adc<'d, T> {
-    fn drop(&mut self) {
+    fn teardown_adc() {
         // A.7.3 ADC disable code example
         T::regs().cr().modify(|reg| reg.set_adstp(true));
         while T::regs().cr().read().adstp() {}
 
         T::regs().cr().modify(|reg| reg.set_addis(true));
         while T::regs().cr().read().aden() {}
+    }
+}
+
+impl<'d, T: Instance> Drop for Adc<'d, T> {
+    fn drop(&mut self) {
+        Self::teardown_adc();
+        Self::teardown_awd();
 
         rcc::disable::<T>();
     }
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 7b5df80b8..805dae564 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -1,5 +1,7 @@
 use cfg_if::cfg_if;
 use pac::adc::vals::Dmacfg;
+#[cfg(adc_v3)]
+use pac::adc::vals::{OversamplingRatio, OversamplingShift, Rovsm, Trovs};
 
 use super::{
     blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
@@ -506,6 +508,23 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().cfgr2().modify(|reg| reg.set_ovse(enable));
     }
 
+    #[cfg(adc_v3)]
+    pub fn enable_regular_oversampling_mode(&mut self, mode: Rovsm, trig_mode: Trovs, enable: bool) {
+        T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
+        T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
+        T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+    }
+
+    #[cfg(adc_v3)]
+    pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
+        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+    }
+
+    #[cfg(adc_v3)]
+    pub fn set_oversampling_shift(&mut self, shift: OversamplingShift) {
+        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+    }
+
     fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
         cfg_if! {
             if #[cfg(any(adc_g0, adc_u0))] {
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index 39e0d51b9..b0871019a 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -142,6 +142,7 @@ impl Prescaler {
 }
 
 /// Number of samples used for averaging.
+#[derive(Copy, Clone)]
 pub enum Averaging {
     Disabled,
     Samples2,
diff --git a/embassy-stm32/src/adc/watchdog_v1.rs b/embassy-stm32/src/adc/watchdog_v1.rs
new file mode 100644
index 000000000..bbe8e1971
--- /dev/null
+++ b/embassy-stm32/src/adc/watchdog_v1.rs
@@ -0,0 +1,188 @@
+use core::future::poll_fn;
+use core::task::Poll;
+
+use stm32_metapac::adc::vals::{Align, Awdsgl, Res};
+
+use crate::adc::{Adc, AdcChannel, Instance};
+
+/// This enum is passed into `Adc::init_watchdog` to specify the channels for the watchdog to monitor
+pub enum WatchdogChannels {
+    // Single channel identified by index
+    Single(u8),
+    // Multiple channels identified by mask
+    Multiple(u16),
+}
+
+impl WatchdogChannels {
+    pub fn from_channel<T>(channel: &impl AdcChannel<T>) -> Self {
+        Self::Single(channel.channel())
+    }
+
+    pub fn add_channel<T>(self, channel: &impl AdcChannel<T>) -> Self {
+        WatchdogChannels::Multiple(
+            (match self {
+                WatchdogChannels::Single(ch) => 1 << ch,
+                WatchdogChannels::Multiple(ch) => ch,
+            }) | 1 << channel.channel(),
+        )
+    }
+}
+
+impl<'d, T: Instance> Adc<'d, T> {
+    /// Configure the analog window watchdog to monitor one or more ADC channels
+    ///
+    /// `high_threshold` and `low_threshold` are expressed in the same way as ADC results. The format
+    /// depends on the values of CFGR1.ALIGN and CFGR1.RES.
+    pub fn init_watchdog(&mut self, channels: WatchdogChannels, low_threshold: u16, high_threshold: u16) {
+        Self::stop_awd();
+
+        match channels {
+            WatchdogChannels::Single(ch) => {
+                T::regs().chselr().modify(|w| {
+                    w.set_chsel_x(ch.into(), true);
+                });
+                T::regs().cfgr1().modify(|w| {
+                    w.set_awdch(ch);
+                    w.set_awdsgl(Awdsgl::SINGLE_CHANNEL)
+                });
+            }
+            WatchdogChannels::Multiple(ch) => {
+                T::regs().chselr().modify(|w| w.0 = ch.into());
+                T::regs().cfgr1().modify(|w| {
+                    w.set_awdch(0);
+                    w.set_awdsgl(Awdsgl::ALL_CHANNELS)
+                });
+            }
+        }
+
+        Self::set_watchdog_thresholds(low_threshold, high_threshold);
+        Self::setup_awd();
+    }
+
+    /// Monitor the voltage on the selected channels; return when it crosses the thresholds.
+    ///
+    /// ```rust,ignore
+    /// // Wait for pin to go high
+    /// adc.init_watchdog(WatchdogChannels::from_channel(&pin), 0, 0x07F);
+    /// let v_high = adc.monitor_watchdog().await;
+    /// info!("ADC sample is high {}", v_high);
+    /// ```
+    pub async fn monitor_watchdog(&mut self) -> u16 {
+        assert!(
+            match T::regs().cfgr1().read().awdsgl() {
+                Awdsgl::SINGLE_CHANNEL => T::regs().cfgr1().read().awdch() != 0,
+                Awdsgl::ALL_CHANNELS => T::regs().cfgr1().read().awdch() == 0,
+            },
+            "`set_channel` should be called before `monitor`",
+        );
+        assert!(T::regs().chselr().read().0 != 0);
+        T::regs().smpr().modify(|reg| reg.set_smp(self.sample_time.into()));
+        Self::start_awd();
+
+        let sample = poll_fn(|cx| {
+            T::state().waker.register(cx.waker());
+
+            if T::regs().isr().read().awd() {
+                Poll::Ready(T::regs().dr().read().data())
+            } else {
+                Poll::Pending
+            }
+        })
+        .await;
+
+        self.stop_watchdog();
+        sample
+    }
+
+    /// Stop monitoring the selected channels
+    pub fn stop_watchdog(&mut self) {
+        Self::stop_awd();
+    }
+
+    fn set_watchdog_thresholds(low_threshold: u16, high_threshold: u16) {
+        // This function takes `high_threshold` and `low_threshold` in the same alignment and resolution
+        // as ADC results, and programs them into ADC_DR. Because ADC_DR is always right-aligned on 12 bits,
+        // some bit-shifting may be necessary. See more in table 47 §13.7.1 Analog Watchdog Comparison
+
+        // Verify that the thresholds are in the correct bit positions according to alignment and resolution
+        let threshold_mask = match (T::regs().cfgr1().read().align(), T::regs().cfgr1().read().res()) {
+            (Align::LEFT, Res::BITS6) => 0x00FC,
+            (Align::LEFT, Res::BITS8) => 0xFF00,
+            (Align::LEFT, Res::BITS10) => 0xFFC0,
+            (Align::LEFT, Res::BITS12) => 0xFFF0,
+            (Align::RIGHT, Res::BITS6) => 0x003F,
+            (Align::RIGHT, Res::BITS8) => 0x00FF,
+            (Align::RIGHT, Res::BITS10) => 0x03FF,
+            (Align::RIGHT, Res::BITS12) => 0x0FFF,
+        };
+        assert!(
+            high_threshold & !threshold_mask == 0,
+            "High threshold {:x} is invalid — only bits {:x} are allowed",
+            high_threshold,
+            threshold_mask
+        );
+        assert!(
+            low_threshold & !threshold_mask == 0,
+            "Low threshold {:x} is invalid — only bits {:x} are allowed",
+            low_threshold,
+            threshold_mask
+        );
+
+        T::regs().tr().modify(|w| {
+            w.set_lt(low_threshold << threshold_mask.leading_zeros() >> 4);
+            w.set_ht(high_threshold << threshold_mask.leading_zeros() >> 4);
+        })
+    }
+
+    fn setup_awd() {
+        // Configure AWD
+        assert!(!T::regs().cr().read().adstart());
+        T::regs().cfgr1().modify(|w| w.set_awden(true));
+    }
+
+    fn start_awd() {
+        // Clear AWD interrupt flag
+        while T::regs().isr().read().awd() {
+            T::regs().isr().modify(|regs| {
+                regs.set_awd(true);
+            })
+        }
+
+        // Enable AWD interrupt
+        assert!(!T::regs().cr().read().adstart());
+        T::regs().ier().modify(|w| {
+            w.set_eocie(false);
+            w.set_awdie(true)
+        });
+
+        // Start conversion
+        T::regs().cfgr1().modify(|w| w.set_cont(true));
+        T::regs().cr().modify(|w| w.set_adstart(true));
+    }
+
+    fn stop_awd() {
+        // Stop conversion
+        while T::regs().cr().read().addis() {}
+        if T::regs().cr().read().adstart() {
+            T::regs().cr().write(|x| x.set_adstp(true));
+            while T::regs().cr().read().adstp() {}
+        }
+        T::regs().cfgr1().modify(|w| w.set_cont(false));
+
+        // Disable AWD interrupt
+        assert!(!T::regs().cr().read().adstart());
+        T::regs().ier().modify(|w| w.set_awdie(false));
+
+        // Clear AWD interrupt flag
+        while T::regs().isr().read().awd() {
+            T::regs().isr().modify(|regs| {
+                regs.set_awd(true);
+            })
+        }
+    }
+
+    pub(crate) fn teardown_awd() {
+        Self::stop_awd();
+        T::regs().cfgr1().modify(|w| w.set_awden(false));
+    }
+}
diff --git a/embassy-stm32/src/can/bxcan/mod.rs b/embassy-stm32/src/can/bxcan/mod.rs
index 305666d5b..4c0795a2a 100644
--- a/embassy-stm32/src/can/bxcan/mod.rs
+++ b/embassy-stm32/src/can/bxcan/mod.rs
@@ -15,9 +15,10 @@ pub use embedded_can::{ExtendedId, Id, StandardId};
 use self::filter::MasterFilters;
 use self::registers::{Registers, RxFifo};
 pub use super::common::{BufferedCanReceiver, BufferedCanSender};
+use super::common::{InfoRef, RxInfoRef, TxInfoRef};
 use super::frame::{Envelope, Frame};
 use super::util;
-use crate::can::enums::{BusError, InternalOperation, TryReadError};
+use crate::can::enums::{BusError, RefCountOp, TryReadError};
 use crate::gpio::{AfType, OutputType, Pull, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
@@ -35,7 +36,9 @@ impl<T: Instance> interrupt::typelevel::Handler<T::TXInterrupt> for TxInterruptH
             v.set_rqcp(1, true);
             v.set_rqcp(2, true);
         });
-        T::state().tx_mode.on_interrupt::<T>();
+        T::info().state.lock(|state| {
+            state.borrow().tx_mode.on_interrupt::<T>();
+        });
     }
 }
 
@@ -46,7 +49,9 @@ pub struct Rx0InterruptHandler<T: Instance> {
 
 impl<T: Instance> interrupt::typelevel::Handler<T::RX0Interrupt> for Rx0InterruptHandler<T> {
     unsafe fn on_interrupt() {
-        T::state().rx_mode.on_interrupt::<T>(RxFifo::Fifo0);
+        T::info().state.lock(|state| {
+            state.borrow().rx_mode.on_interrupt::<T>(RxFifo::Fifo0);
+        });
     }
 }
 
@@ -57,7 +62,9 @@ pub struct Rx1InterruptHandler<T: Instance> {
 
 impl<T: Instance> interrupt::typelevel::Handler<T::RX1Interrupt> for Rx1InterruptHandler<T> {
     unsafe fn on_interrupt() {
-        T::state().rx_mode.on_interrupt::<T>(RxFifo::Fifo1);
+        T::info().state.lock(|state| {
+            state.borrow().rx_mode.on_interrupt::<T>(RxFifo::Fifo1);
+        });
     }
 }
 
@@ -73,7 +80,9 @@ impl<T: Instance> interrupt::typelevel::Handler<T::SCEInterrupt> for SceInterrup
 
         if msr_val.slaki() {
             msr.modify(|m| m.set_slaki(true));
-            T::state().err_waker.wake();
+            T::info().state.lock(|state| {
+                state.borrow().err_waker.wake();
+            });
         } else if msr_val.erri() {
             // Disable the interrupt, but don't acknowledge the error, so that it can be
             // forwarded off the bus message consumer. If we don't provide some way for
@@ -82,8 +91,9 @@ impl<T: Instance> interrupt::typelevel::Handler<T::SCEInterrupt> for SceInterrup
             // an indefinite amount of time.
             let ier = T::regs().ier();
             ier.modify(|i| i.set_errie(false));
-
-            T::state().err_waker.wake();
+            T::info().state.lock(|state| {
+                state.borrow().err_waker.wake();
+            });
         }
     }
 }
@@ -91,7 +101,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::SCEInterrupt> for SceInterrup
 /// Configuration proxy returned by [`Can::modify_config`].
 pub struct CanConfig<'a> {
     phantom: PhantomData<&'a ()>,
-    info: &'static Info,
+    info: InfoRef,
     periph_clock: crate::time::Hertz,
 }
 
@@ -156,8 +166,7 @@ impl Drop for CanConfig<'_> {
 /// CAN driver
 pub struct Can<'d> {
     phantom: PhantomData<&'d ()>,
-    info: &'static Info,
-    state: &'static State,
+    info: InfoRef,
     periph_clock: crate::time::Hertz,
 }
 
@@ -227,8 +236,7 @@ impl<'d> Can<'d> {
 
         Self {
             phantom: PhantomData,
-            info: T::info(),
-            state: T::state(),
+            info: InfoRef::new(T::info()),
             periph_clock: T::frequency(),
         }
     }
@@ -248,7 +256,7 @@ impl<'d> Can<'d> {
 
         CanConfig {
             phantom: self.phantom,
-            info: self.info,
+            info: InfoRef::new(&self.info),
             periph_clock: self.periph_clock,
         }
     }
@@ -297,7 +305,9 @@ impl<'d> Can<'d> {
         self.info.regs.0.mcr().modify(|m| m.set_sleep(true));
 
         poll_fn(|cx| {
-            self.state.err_waker.register(cx.waker());
+            self.info.state.lock(|s| {
+                s.borrow().err_waker.register(cx.waker());
+            });
             if self.is_sleeping() {
                 Poll::Ready(())
             } else {
@@ -350,8 +360,7 @@ impl<'d> Can<'d> {
     pub async fn flush(&self, mb: Mailbox) {
         CanTx {
             _phantom: PhantomData,
-            info: self.info,
-            state: self.state,
+            info: TxInfoRef::new(&self.info),
         }
         .flush_inner(mb)
         .await;
@@ -366,8 +375,7 @@ impl<'d> Can<'d> {
     pub async fn flush_any(&self) {
         CanTx {
             _phantom: PhantomData,
-            info: self.info,
-            state: self.state,
+            info: TxInfoRef::new(&self.info),
         }
         .flush_any_inner()
         .await
@@ -377,8 +385,7 @@ impl<'d> Can<'d> {
     pub async fn flush_all(&self) {
         CanTx {
             _phantom: PhantomData,
-            info: self.info,
-            state: self.state,
+            info: TxInfoRef::new(&self.info),
         }
         .flush_all_inner()
         .await
@@ -406,19 +413,19 @@ impl<'d> Can<'d> {
     ///
     /// Returns a tuple of the time the message was received and the message frame
     pub async fn read(&mut self) -> Result<Envelope, BusError> {
-        self.state.rx_mode.read(self.info, self.state).await
+        RxMode::read(&self.info).await
     }
 
     /// Attempts to read a CAN frame without blocking.
     ///
     /// Returns [Err(TryReadError::Empty)] if there are no frames in the rx queue.
     pub fn try_read(&mut self) -> Result<Envelope, TryReadError> {
-        self.state.rx_mode.try_read(self.info)
+        RxMode::try_read(&self.info)
     }
 
     /// Waits while receive queue is empty.
     pub async fn wait_not_empty(&mut self) {
-        self.state.rx_mode.wait_not_empty(self.info, self.state).await
+        RxMode::wait_not_empty(&self.info).await
     }
 
     /// Split the CAN driver into transmit and receive halves.
@@ -428,13 +435,11 @@ impl<'d> Can<'d> {
         (
             CanTx {
                 _phantom: PhantomData,
-                info: self.info,
-                state: self.state,
+                info: TxInfoRef::new(&self.info),
             },
             CanRx {
                 _phantom: PhantomData,
-                info: self.info,
-                state: self.state,
+                info: RxInfoRef::new(&self.info),
             },
         )
     }
@@ -459,7 +464,7 @@ impl<'d> Can<'d> {
     /// To modify filters of a slave peripheral, `modify_filters` has to be called on the master
     /// peripheral instead.
     pub fn modify_filters(&mut self) -> MasterFilters<'_> {
-        unsafe { MasterFilters::new(self.info) }
+        unsafe { MasterFilters::new(&self.info) }
     }
 }
 
@@ -514,8 +519,7 @@ impl<'d, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d, TX_
 /// CAN driver, transmit half.
 pub struct CanTx<'d> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
-    state: &'static State,
+    info: TxInfoRef,
 }
 
 impl<'d> CanTx<'d> {
@@ -524,7 +528,9 @@ impl<'d> CanTx<'d> {
     /// If the TX queue is full, this will wait until there is space, therefore exerting backpressure.
     pub async fn write(&mut self, frame: &Frame) -> TransmitStatus {
         poll_fn(|cx| {
-            self.state.tx_mode.register(cx.waker());
+            self.info.state.lock(|s| {
+                s.borrow().tx_mode.register(cx.waker());
+            });
             if let Ok(status) = self.info.regs.transmit(frame) {
                 return Poll::Ready(status);
             }
@@ -549,7 +555,9 @@ impl<'d> CanTx<'d> {
 
     async fn flush_inner(&self, mb: Mailbox) {
         poll_fn(|cx| {
-            self.state.tx_mode.register(cx.waker());
+            self.info.state.lock(|s| {
+                s.borrow().tx_mode.register(cx.waker());
+            });
             if self.info.regs.0.tsr().read().tme(mb.index()) {
                 return Poll::Ready(());
             }
@@ -566,7 +574,9 @@ impl<'d> CanTx<'d> {
 
     async fn flush_any_inner(&self) {
         poll_fn(|cx| {
-            self.state.tx_mode.register(cx.waker());
+            self.info.state.lock(|s| {
+                s.borrow().tx_mode.register(cx.waker());
+            });
 
             let tsr = self.info.regs.0.tsr().read();
             if tsr.tme(Mailbox::Mailbox0.index())
@@ -593,7 +603,9 @@ impl<'d> CanTx<'d> {
 
     async fn flush_all_inner(&self) {
         poll_fn(|cx| {
-            self.state.tx_mode.register(cx.waker());
+            self.info.state.lock(|s| {
+                s.borrow().tx_mode.register(cx.waker());
+            });
 
             let tsr = self.info.regs.0.tsr().read();
             if tsr.tme(Mailbox::Mailbox0.index())
@@ -634,7 +646,7 @@ impl<'d> CanTx<'d> {
         self,
         txb: &'static mut TxBuf<TX_BUF_SIZE>,
     ) -> BufferedCanTx<'d, TX_BUF_SIZE> {
-        BufferedCanTx::new(self.info, self.state, self, txb)
+        BufferedCanTx::new(&self.info, self, txb)
     }
 }
 
@@ -643,17 +655,15 @@ pub type TxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, Frame,
 
 /// Buffered CAN driver, transmit half.
 pub struct BufferedCanTx<'d, const TX_BUF_SIZE: usize> {
-    info: &'static Info,
-    state: &'static State,
+    info: TxInfoRef,
     _tx: CanTx<'d>,
     tx_buf: &'static TxBuf<TX_BUF_SIZE>,
 }
 
 impl<'d, const TX_BUF_SIZE: usize> BufferedCanTx<'d, TX_BUF_SIZE> {
-    fn new(info: &'static Info, state: &'static State, _tx: CanTx<'d>, tx_buf: &'static TxBuf<TX_BUF_SIZE>) -> Self {
+    fn new(info: &'static Info, _tx: CanTx<'d>, tx_buf: &'static TxBuf<TX_BUF_SIZE>) -> Self {
         Self {
-            info,
-            state,
+            info: TxInfoRef::new(info),
             _tx,
             tx_buf,
         }
@@ -666,11 +676,9 @@ impl<'d, const TX_BUF_SIZE: usize> BufferedCanTx<'d, TX_BUF_SIZE> {
             let tx_inner = super::common::ClassicBufferedTxInner {
                 tx_receiver: self.tx_buf.receiver().into(),
             };
-            let state = self.state as *const State;
-            unsafe {
-                let mut_state = state as *mut State;
-                (*mut_state).tx_mode = TxMode::Buffered(tx_inner);
-            }
+            self.info.state.lock(|s| {
+                s.borrow_mut().tx_mode = TxMode::Buffered(tx_inner);
+            });
         });
         self
     }
@@ -684,27 +692,18 @@ impl<'d, const TX_BUF_SIZE: usize> BufferedCanTx<'d, TX_BUF_SIZE> {
 
     /// Returns a sender that can be used for sending CAN frames.
     pub fn writer(&self) -> BufferedCanSender {
-        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
         BufferedCanSender {
             tx_buf: self.tx_buf.sender().into(),
-            waker: self.info.tx_waker,
-            internal_operation: self.info.internal_operation,
+            info: TxInfoRef::new(&self.info),
         }
     }
 }
 
-impl<'d, const TX_BUF_SIZE: usize> Drop for BufferedCanTx<'d, TX_BUF_SIZE> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-    }
-}
-
 /// CAN driver, receive half.
 #[allow(dead_code)]
 pub struct CanRx<'d> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
-    state: &'static State,
+    info: RxInfoRef,
 }
 
 impl<'d> CanRx<'d> {
@@ -714,19 +713,19 @@ impl<'d> CanRx<'d> {
     ///
     /// Returns a tuple of the time the message was received and the message frame
     pub async fn read(&mut self) -> Result<Envelope, BusError> {
-        self.state.rx_mode.read(self.info, self.state).await
+        RxMode::read(&self.info).await
     }
 
     /// Attempts to read a CAN frame without blocking.
     ///
     /// Returns [Err(TryReadError::Empty)] if there are no frames in the rx queue.
     pub fn try_read(&mut self) -> Result<Envelope, TryReadError> {
-        self.state.rx_mode.try_read(self.info)
+        RxMode::try_read(&self.info)
     }
 
     /// Waits while receive queue is empty.
     pub async fn wait_not_empty(&mut self) {
-        self.state.rx_mode.wait_not_empty(self.info, self.state).await
+        RxMode::wait_not_empty(&self.info).await
     }
 
     /// Return a buffered instance of driver. User must supply Buffers
@@ -734,7 +733,7 @@ impl<'d> CanRx<'d> {
         self,
         rxb: &'static mut RxBuf<RX_BUF_SIZE>,
     ) -> BufferedCanRx<'d, RX_BUF_SIZE> {
-        BufferedCanRx::new(self.info, self.state, self, rxb)
+        BufferedCanRx::new(&self.info, self, rxb)
     }
 
     /// Accesses the filter banks owned by this CAN peripheral.
@@ -742,7 +741,7 @@ impl<'d> CanRx<'d> {
     /// To modify filters of a slave peripheral, `modify_filters` has to be called on the master
     /// peripheral instead.
     pub fn modify_filters(&mut self) -> MasterFilters<'_> {
-        unsafe { MasterFilters::new(self.info) }
+        unsafe { MasterFilters::new(&self.info) }
     }
 }
 
@@ -751,17 +750,15 @@ pub type RxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, Result<
 
 /// CAN driver, receive half in Buffered mode.
 pub struct BufferedCanRx<'d, const RX_BUF_SIZE: usize> {
-    info: &'static Info,
-    state: &'static State,
+    info: RxInfoRef,
     rx: CanRx<'d>,
     rx_buf: &'static RxBuf<RX_BUF_SIZE>,
 }
 
 impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
-    fn new(info: &'static Info, state: &'static State, rx: CanRx<'d>, rx_buf: &'static RxBuf<RX_BUF_SIZE>) -> Self {
+    fn new(info: &'static Info, rx: CanRx<'d>, rx_buf: &'static RxBuf<RX_BUF_SIZE>) -> Self {
         BufferedCanRx {
-            info,
-            state,
+            info: RxInfoRef::new(info),
             rx,
             rx_buf,
         }
@@ -774,11 +771,9 @@ impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
             let rx_inner = super::common::ClassicBufferedRxInner {
                 rx_sender: self.rx_buf.sender().into(),
             };
-            let state = self.state as *const State;
-            unsafe {
-                let mut_state = state as *mut State;
-                (*mut_state).rx_mode = RxMode::Buffered(rx_inner);
-            }
+            self.info.state.lock(|s| {
+                s.borrow_mut().rx_mode = RxMode::Buffered(rx_inner);
+            });
         });
         self
     }
@@ -792,7 +787,7 @@ impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
     ///
     /// Returns [Err(TryReadError::Empty)] if there are no frames in the rx queue.
     pub fn try_read(&mut self) -> Result<Envelope, TryReadError> {
-        match &self.state.rx_mode {
+        self.info.state.lock(|s| match &s.borrow().rx_mode {
             RxMode::Buffered(_) => {
                 if let Ok(result) = self.rx_buf.try_receive() {
                     match result {
@@ -810,7 +805,7 @@ impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
             _ => {
                 panic!("Bad Mode")
             }
-        }
+        })
     }
 
     /// Waits while receive queue is empty.
@@ -820,10 +815,9 @@ impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
 
     /// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
     pub fn reader(&self) -> BufferedCanReceiver {
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         BufferedCanReceiver {
             rx_buf: self.rx_buf.receiver().into(),
-            internal_operation: self.info.internal_operation,
+            info: RxInfoRef::new(&self.info),
         }
     }
 
@@ -836,12 +830,6 @@ impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
     }
 }
 
-impl<'d, const RX_BUF_SIZE: usize> Drop for BufferedCanRx<'d, RX_BUF_SIZE> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-    }
-}
-
 impl Drop for Can<'_> {
     fn drop(&mut self) {
         // Cannot call `free()` because it moves the instance.
@@ -929,27 +917,30 @@ impl RxMode {
         }
     }
 
-    pub(crate) async fn read(&self, info: &Info, state: &State) -> Result<Envelope, BusError> {
-        match self {
-            Self::NonBuffered(waker) => {
-                poll_fn(|cx| {
-                    state.err_waker.register(cx.waker());
-                    waker.register(cx.waker());
-                    match self.try_read(info) {
-                        Ok(result) => Poll::Ready(Ok(result)),
-                        Err(TryReadError::Empty) => Poll::Pending,
-                        Err(TryReadError::BusError(be)) => Poll::Ready(Err(be)),
+    pub(crate) async fn read(info: &Info) -> Result<Envelope, BusError> {
+        poll_fn(|cx| {
+            info.state.lock(|state| {
+                let state = state.borrow();
+                state.err_waker.register(cx.waker());
+                match &state.rx_mode {
+                    Self::NonBuffered(waker) => {
+                        waker.register(cx.waker());
                     }
-                })
-                .await
-            }
-            _ => {
-                panic!("Bad Mode")
+                    _ => {
+                        panic!("Bad Mode")
+                    }
+                }
+            });
+            match RxMode::try_read(info) {
+                Ok(result) => Poll::Ready(Ok(result)),
+                Err(TryReadError::Empty) => Poll::Pending,
+                Err(TryReadError::BusError(be)) => Poll::Ready(Err(be)),
             }
-        }
+        })
+        .await
     }
-    pub(crate) fn try_read(&self, info: &Info) -> Result<Envelope, TryReadError> {
-        match self {
+    pub(crate) fn try_read(info: &Info) -> Result<Envelope, TryReadError> {
+        info.state.lock(|state| match state.borrow().rx_mode {
             Self::NonBuffered(_) => {
                 let registers = &info.regs;
                 if let Some(msg) = registers.receive_fifo(RxFifo::Fifo0) {
@@ -975,25 +966,28 @@ impl RxMode {
             _ => {
                 panic!("Bad Mode")
             }
-        }
+        })
     }
-    pub(crate) async fn wait_not_empty(&self, info: &Info, state: &State) {
-        match &state.rx_mode {
-            Self::NonBuffered(waker) => {
-                poll_fn(|cx| {
-                    waker.register(cx.waker());
-                    if info.regs.receive_frame_available() {
-                        Poll::Ready(())
-                    } else {
-                        Poll::Pending
+    pub(crate) async fn wait_not_empty(info: &Info) {
+        poll_fn(|cx| {
+            info.state.lock(|s| {
+                let state = s.borrow();
+                match &state.rx_mode {
+                    Self::NonBuffered(waker) => {
+                        waker.register(cx.waker());
                     }
-                })
-                .await
-            }
-            _ => {
-                panic!("Bad Mode")
+                    _ => {
+                        panic!("Bad Mode")
+                    }
+                }
+            });
+            if info.regs.receive_frame_available() {
+                Poll::Ready(())
+            } else {
+                Poll::Pending
             }
-        }
+        })
+        .await
     }
 }
 
@@ -1008,21 +1002,25 @@ impl TxMode {
         tsr.tme(Mailbox::Mailbox0.index()) || tsr.tme(Mailbox::Mailbox1.index()) || tsr.tme(Mailbox::Mailbox2.index())
     }
     pub fn on_interrupt<T: Instance>(&self) {
-        match &T::state().tx_mode {
-            TxMode::NonBuffered(waker) => waker.wake(),
-            TxMode::Buffered(buf) => {
-                while self.buffer_free::<T>() {
-                    match buf.tx_receiver.try_receive() {
-                        Ok(frame) => {
-                            _ = Registers(T::regs()).transmit(&frame);
-                        }
-                        Err(_) => {
-                            break;
+        T::info().state.lock(|state| {
+            let tx_mode = &state.borrow().tx_mode;
+
+            match tx_mode {
+                TxMode::NonBuffered(waker) => waker.wake(),
+                TxMode::Buffered(buf) => {
+                    while self.buffer_free::<T>() {
+                        match buf.tx_receiver.try_receive() {
+                            Ok(frame) => {
+                                _ = Registers(T::regs()).transmit(&frame);
+                            }
+                            Err(_) => {
+                                break;
+                            }
                         }
                     }
                 }
             }
-        }
+        });
     }
 
     fn register(&self, arg: &core::task::Waker) {
@@ -1057,14 +1055,15 @@ impl State {
     }
 }
 
+type SharedState = embassy_sync::blocking_mutex::Mutex<CriticalSectionRawMutex, core::cell::RefCell<State>>;
 pub(crate) struct Info {
     regs: Registers,
     tx_interrupt: crate::interrupt::Interrupt,
     rx0_interrupt: crate::interrupt::Interrupt,
     rx1_interrupt: crate::interrupt::Interrupt,
     sce_interrupt: crate::interrupt::Interrupt,
-    tx_waker: fn(),
-    internal_operation: fn(InternalOperation),
+    pub(crate) tx_waker: fn(),
+    state: SharedState,
 
     /// The total number of filter banks available to the instance.
     ///
@@ -1072,12 +1071,37 @@ pub(crate) struct Info {
     num_filter_banks: u8,
 }
 
+impl Info {
+    pub(crate) fn adjust_reference_counter(&self, val: RefCountOp) {
+        self.state.lock(|s| {
+            let mut mut_state = s.borrow_mut();
+            match val {
+                RefCountOp::NotifySenderCreated => {
+                    mut_state.sender_instance_count += 1;
+                }
+                RefCountOp::NotifySenderDestroyed => {
+                    mut_state.sender_instance_count -= 1;
+                    if 0 == mut_state.sender_instance_count {
+                        (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                    }
+                }
+                RefCountOp::NotifyReceiverCreated => {
+                    mut_state.receiver_instance_count += 1;
+                }
+                RefCountOp::NotifyReceiverDestroyed => {
+                    mut_state.receiver_instance_count -= 1;
+                    if 0 == mut_state.receiver_instance_count {
+                        (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                    }
+                }
+            }
+        });
+    }
+}
+
 trait SealedInstance {
     fn info() -> &'static Info;
     fn regs() -> crate::pac::can::Can;
-    fn state() -> &'static State;
-    unsafe fn mut_state() -> &'static mut State;
-    fn internal_operation(val: InternalOperation);
 }
 
 /// CAN instance trait.
@@ -1135,53 +1159,14 @@ foreach_peripheral!(
                     rx1_interrupt: crate::_generated::peripheral_interrupts::$inst::RX1::IRQ,
                     sce_interrupt: crate::_generated::peripheral_interrupts::$inst::SCE::IRQ,
                     tx_waker: crate::_generated::peripheral_interrupts::$inst::TX::pend,
-                    internal_operation: peripherals::$inst::internal_operation,
                     num_filter_banks: peripherals::$inst::NUM_FILTER_BANKS,
+                    state: embassy_sync::blocking_mutex::Mutex::new(core::cell::RefCell::new(State::new())),
                 };
                 &INFO
             }
             fn regs() -> crate::pac::can::Can {
                 crate::pac::$inst
             }
-
-            unsafe fn mut_state() -> & 'static mut State {
-                static mut STATE: State = State::new();
-                &mut *core::ptr::addr_of_mut!(STATE)
-            }
-            fn state() -> &'static State {
-                unsafe { peripherals::$inst::mut_state() }
-            }
-
-
-            fn internal_operation(val: InternalOperation) {
-                critical_section::with(|_| {
-                    //let state = self.state as *const State;
-                    unsafe {
-                        //let mut_state = state as *mut State;
-                        let mut_state = peripherals::$inst::mut_state();
-                        match val {
-                            InternalOperation::NotifySenderCreated => {
-                                mut_state.sender_instance_count += 1;
-                            }
-                            InternalOperation::NotifySenderDestroyed => {
-                                mut_state.sender_instance_count -= 1;
-                                if ( 0 == mut_state.sender_instance_count) {
-                                    (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-                                }
-                            }
-                            InternalOperation::NotifyReceiverCreated => {
-                                mut_state.receiver_instance_count += 1;
-                            }
-                            InternalOperation::NotifyReceiverDestroyed => {
-                                mut_state.receiver_instance_count -= 1;
-                                if ( 0 == mut_state.receiver_instance_count) {
-                                    (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-                                }
-                            }
-                        }
-                    }
-                });
-            }
         }
 
         impl Instance for peripherals::$inst {
diff --git a/embassy-stm32/src/can/common.rs b/embassy-stm32/src/can/common.rs
index 386d4467c..980f33a04 100644
--- a/embassy-stm32/src/can/common.rs
+++ b/embassy-stm32/src/can/common.rs
@@ -24,22 +24,21 @@ pub(crate) struct FdBufferedTxInner {
 /// Sender that can be used for sending CAN frames.
 pub struct BufferedSender<'ch, FRAME> {
     pub(crate) tx_buf: embassy_sync::channel::SendDynamicSender<'ch, FRAME>,
-    pub(crate) waker: fn(),
-    pub(crate) internal_operation: fn(InternalOperation),
+    pub(crate) info: TxInfoRef,
 }
 
 impl<'ch, FRAME> BufferedSender<'ch, FRAME> {
     /// Async write frame to TX buffer.
     pub fn try_write(&mut self, frame: FRAME) -> Result<(), embassy_sync::channel::TrySendError<FRAME>> {
         self.tx_buf.try_send(frame)?;
-        (self.waker)();
+        (self.info.tx_waker)();
         Ok(())
     }
 
     /// Async write frame to TX buffer.
     pub async fn write(&mut self, frame: FRAME) {
         self.tx_buf.send(frame).await;
-        (self.waker)();
+        (self.info.tx_waker)();
     }
 
     /// Allows a poll_fn to poll until the channel is ready to write
@@ -50,28 +49,20 @@ impl<'ch, FRAME> BufferedSender<'ch, FRAME> {
 
 impl<'ch, FRAME> Clone for BufferedSender<'ch, FRAME> {
     fn clone(&self) -> Self {
-        (self.internal_operation)(InternalOperation::NotifySenderCreated);
         Self {
             tx_buf: self.tx_buf,
-            waker: self.waker,
-            internal_operation: self.internal_operation,
+            info: TxInfoRef::new(&self.info),
         }
     }
 }
 
-impl<'ch, FRAME> Drop for BufferedSender<'ch, FRAME> {
-    fn drop(&mut self) {
-        (self.internal_operation)(InternalOperation::NotifySenderDestroyed);
-    }
-}
-
 /// Sender that can be used for sending Classic CAN frames.
 pub type BufferedCanSender = BufferedSender<'static, Frame>;
 
 /// Receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
 pub struct BufferedReceiver<'ch, ENVELOPE> {
     pub(crate) rx_buf: embassy_sync::channel::SendDynamicReceiver<'ch, Result<ENVELOPE, BusError>>,
-    pub(crate) internal_operation: fn(InternalOperation),
+    pub(crate) info: RxInfoRef,
 }
 
 impl<'ch, ENVELOPE> BufferedReceiver<'ch, ENVELOPE> {
@@ -106,19 +97,99 @@ impl<'ch, ENVELOPE> BufferedReceiver<'ch, ENVELOPE> {
 
 impl<'ch, ENVELOPE> Clone for BufferedReceiver<'ch, ENVELOPE> {
     fn clone(&self) -> Self {
-        (self.internal_operation)(InternalOperation::NotifyReceiverCreated);
         Self {
             rx_buf: self.rx_buf,
-            internal_operation: self.internal_operation,
+            info: RxInfoRef::new(&self.info),
         }
     }
 }
 
-impl<'ch, ENVELOPE> Drop for BufferedReceiver<'ch, ENVELOPE> {
+/// A BufferedCanReceiver for Classic CAN frames.
+pub type BufferedCanReceiver = BufferedReceiver<'static, Envelope>;
+
+/// Provides a reference to the driver internals and implements RAII for the internal reference
+/// counting. Each type that can operate on the driver should contain either InfoRef
+/// or the similar TxInfoRef or RxInfoRef. The new method and the Drop impl will automatically
+/// call the reference counting function. Like this, the reference counting function does not
+/// need to be called manually for each type.
+pub(crate) struct InfoRef {
+    info: &'static super::Info,
+}
+impl InfoRef {
+    pub(crate) fn new(info: &'static super::Info) -> Self {
+        info.adjust_reference_counter(RefCountOp::NotifyReceiverCreated);
+        info.adjust_reference_counter(RefCountOp::NotifySenderCreated);
+        Self { info }
+    }
+}
+
+impl Drop for InfoRef {
     fn drop(&mut self) {
-        (self.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
+        self.info.adjust_reference_counter(RefCountOp::NotifyReceiverDestroyed);
+        self.info.adjust_reference_counter(RefCountOp::NotifySenderDestroyed);
     }
 }
 
-/// A BufferedCanReceiver for Classic CAN frames.
-pub type BufferedCanReceiver = BufferedReceiver<'static, Envelope>;
+impl core::ops::Deref for InfoRef {
+    type Target = &'static super::Info;
+
+    fn deref(&self) -> &Self::Target {
+        &self.info
+    }
+}
+
+/// Provides a reference to the driver internals and implements RAII for the internal reference
+/// counting for Tx only types.
+/// See InfoRef for further doc.
+pub(crate) struct TxInfoRef {
+    info: &'static super::Info,
+}
+
+impl TxInfoRef {
+    pub(crate) fn new(info: &'static super::Info) -> Self {
+        info.adjust_reference_counter(RefCountOp::NotifySenderCreated);
+        Self { info }
+    }
+}
+
+impl Drop for TxInfoRef {
+    fn drop(&mut self) {
+        self.info.adjust_reference_counter(RefCountOp::NotifySenderDestroyed);
+    }
+}
+
+impl core::ops::Deref for TxInfoRef {
+    type Target = &'static super::Info;
+
+    fn deref(&self) -> &Self::Target {
+        &self.info
+    }
+}
+
+/// Provides a reference to the driver internals and implements RAII for the internal reference
+/// counting for Rx only types.
+/// See InfoRef for further doc.
+pub(crate) struct RxInfoRef {
+    info: &'static super::Info,
+}
+
+impl RxInfoRef {
+    pub(crate) fn new(info: &'static super::Info) -> Self {
+        info.adjust_reference_counter(RefCountOp::NotifyReceiverCreated);
+        Self { info }
+    }
+}
+
+impl Drop for RxInfoRef {
+    fn drop(&mut self) {
+        self.info.adjust_reference_counter(RefCountOp::NotifyReceiverDestroyed);
+    }
+}
+
+impl core::ops::Deref for RxInfoRef {
+    type Target = &'static super::Info;
+
+    fn deref(&self) -> &Self::Target {
+        &self.info
+    }
+}
diff --git a/embassy-stm32/src/can/enums.rs b/embassy-stm32/src/can/enums.rs
index 97cb47640..6d91020fc 100644
--- a/embassy-stm32/src/can/enums.rs
+++ b/embassy-stm32/src/can/enums.rs
@@ -72,7 +72,7 @@ pub enum TryReadError {
 /// Internal Operation
 #[derive(Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum InternalOperation {
+pub enum RefCountOp {
     /// Notify receiver created
     NotifyReceiverCreated,
     /// Notify receiver destroyed
diff --git a/embassy-stm32/src/can/fd/message_ram/extended_filter.rs b/embassy-stm32/src/can/fd/message_ram/extended_filter.rs
index 453e9056e..ac47901a8 100644
--- a/embassy-stm32/src/can/fd/message_ram/extended_filter.rs
+++ b/embassy-stm32/src/can/fd/message_ram/extended_filter.rs
@@ -115,22 +115,22 @@ impl R {
 impl W {
     #[doc = "Byte 0 - Bits 0:28 - EFID1"]
     #[inline(always)]
-    pub fn efid1(&mut self) -> EFID1_W {
+    pub fn efid1(&mut self) -> EFID1_W<'_> {
         EFID1_W { w: self }
     }
     #[doc = "Byte 0 - Bits 29:31 - EFEC"]
     #[inline(always)]
-    pub fn efec(&mut self) -> EFEC_W {
+    pub fn efec(&mut self) -> EFEC_W<'_> {
         EFEC_W { w: self }
     }
     #[doc = "Byte 1 - Bits 0:28 - EFID2"]
     #[inline(always)]
-    pub fn efid2(&mut self) -> EFID2_W {
+    pub fn efid2(&mut self) -> EFID2_W<'_> {
         EFID2_W { w: self }
     }
     #[doc = "Byte 1 - Bits 30:31 - EFT"]
     #[inline(always)]
-    pub fn eft(&mut self) -> EFT_W {
+    pub fn eft(&mut self) -> EFT_W<'_> {
         EFT_W { w: self }
     }
 }
diff --git a/embassy-stm32/src/can/fd/message_ram/standard_filter.rs b/embassy-stm32/src/can/fd/message_ram/standard_filter.rs
index 3a3bbcf12..f52646bfe 100644
--- a/embassy-stm32/src/can/fd/message_ram/standard_filter.rs
+++ b/embassy-stm32/src/can/fd/message_ram/standard_filter.rs
@@ -115,22 +115,22 @@ impl R {
 impl W {
     #[doc = "Bits 0:10 - SFID2"]
     #[inline(always)]
-    pub fn sfid2(&mut self) -> SFID2_W {
+    pub fn sfid2(&mut self) -> SFID2_W<'_> {
         SFID2_W { w: self }
     }
     #[doc = "Bits 16:26 - SFID1"]
     #[inline(always)]
-    pub fn sfid1(&mut self) -> SFID1_W {
+    pub fn sfid1(&mut self) -> SFID1_W<'_> {
         SFID1_W { w: self }
     }
     #[doc = "Bits 27:29 - SFEC"]
     #[inline(always)]
-    pub fn sfec(&mut self) -> SFEC_W {
+    pub fn sfec(&mut self) -> SFEC_W<'_> {
         SFEC_W { w: self }
     }
     #[doc = "Bits 30:31 - SFT"]
     #[inline(always)]
-    pub fn sft(&mut self) -> SFT_W {
+    pub fn sft(&mut self) -> SFT_W<'_> {
         SFT_W { w: self }
     }
 }
diff --git a/embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs b/embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs
index 455406a1c..6d65a86cb 100644
--- a/embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs
+++ b/embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs
@@ -376,47 +376,47 @@ impl R {
 impl W {
     #[doc = "Byte 0 - Bits 0:28 - ID"]
     #[inline(always)]
-    pub fn id(&mut self) -> ID_W {
+    pub fn id(&mut self) -> ID_W<'_> {
         ID_W { w: self }
     }
     #[doc = "Byte 0 - Bit 29 - RTR"]
     #[inline(always)]
-    pub fn rtr(&mut self) -> RTR_W {
+    pub fn rtr(&mut self) -> RTR_W<'_> {
         RTR_W { w: self }
     }
     #[doc = "Byte 0 - Bit 30 - XTD"]
     #[inline(always)]
-    pub fn xtd(&mut self) -> XTD_W {
+    pub fn xtd(&mut self) -> XTD_W<'_> {
         XTD_W { w: self }
     }
     #[doc = "Byte 0 - Bit 31 - ESI"]
     #[inline(always)]
-    pub fn esi(&mut self) -> ESI_W {
+    pub fn esi(&mut self) -> ESI_W<'_> {
         ESI_W { w: self }
     }
     #[doc = "Byte 1 - Bit 16:19 - DLC"]
     #[inline(always)]
-    pub fn dlc(&mut self) -> DLC_W {
+    pub fn dlc(&mut self) -> DLC_W<'_> {
         DLC_W { w: self }
     }
     #[doc = "Byte 1 - Bit 20 - BRS"]
     #[inline(always)]
-    pub fn brs(&mut self) -> BRS_W {
+    pub fn brs(&mut self) -> BRS_W<'_> {
         BRS_W { w: self }
     }
     #[doc = "Byte 1 - Bit 21 - FDF"]
     #[inline(always)]
-    pub fn fdf(&mut self) -> FDF_W {
+    pub fn fdf(&mut self) -> FDF_W<'_> {
         FDF_W { w: self }
     }
     #[doc = "Byte 1 - Bit 23 - EFC"]
     #[inline(always)]
-    pub fn efc(&mut self) -> EFC_W {
+    pub fn efc(&mut self) -> EFC_W<'_> {
         EFC_W { w: self }
     }
     #[doc = "Byte 1 - Bit 24:31 - MM"]
     #[inline(always)]
-    pub fn mm(&mut self) -> MM_W {
+    pub fn mm(&mut self) -> MM_W<'_> {
         MM_W { w: self }
     }
     #[doc = "Convenience function for setting the data length and frame format"]
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 97d22315a..99e40ba62 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -21,6 +21,7 @@ use self::fd::config::*;
 use self::fd::filter::*;
 pub use self::fd::{config, filter};
 pub use super::common::{BufferedCanReceiver, BufferedCanSender};
+use super::common::{InfoRef, RxInfoRef, TxInfoRef};
 use super::enums::*;
 use super::frame::*;
 use super::util;
@@ -167,10 +168,10 @@ fn calc_ns_per_timer_tick(
 pub struct CanConfigurator<'d> {
     _phantom: PhantomData<&'d ()>,
     config: crate::can::fd::config::FdCanConfig,
-    info: &'static Info,
     /// Reference to internals.
     properties: Properties,
     periph_clock: crate::time::Hertz,
+    info: InfoRef,
 }
 
 impl<'d> CanConfigurator<'d> {
@@ -194,8 +195,6 @@ impl<'d> CanConfigurator<'d> {
             s.borrow_mut().tx_pin_port = Some(tx.pin_port());
             s.borrow_mut().rx_pin_port = Some(rx.pin_port());
         });
-        (info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (info.internal_operation)(InternalOperation::NotifyReceiverCreated);
 
         let mut config = crate::can::fd::config::FdCanConfig::default();
         config.timestamp_source = TimestampSource::Prescaler(TimestampPrescaler::_1);
@@ -211,9 +210,9 @@ impl<'d> CanConfigurator<'d> {
         Self {
             _phantom: PhantomData,
             config,
-            info,
             properties: Properties::new(T::info()),
             periph_clock: T::frequency(),
+            info: InfoRef::new(info),
         }
     }
 
@@ -262,19 +261,17 @@ impl<'d> CanConfigurator<'d> {
 
     /// Start in mode.
     pub fn start(self, mode: OperatingMode) -> Can<'d> {
-        let ns_per_timer_tick = calc_ns_per_timer_tick(self.info, self.periph_clock, self.config.frame_transmit);
+        let ns_per_timer_tick = calc_ns_per_timer_tick(&self.info, self.periph_clock, self.config.frame_transmit);
         self.info.state.lock(|s| {
             s.borrow_mut().ns_per_timer_tick = ns_per_timer_tick;
         });
         self.info.regs.into_mode(self.config, mode);
-        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         Can {
             _phantom: PhantomData,
             config: self.config,
-            info: self.info,
             _mode: mode,
-            properties: Properties::new(self.info),
+            properties: Properties::new(&self.info),
+            info: InfoRef::new(&self.info),
         }
     }
 
@@ -294,20 +291,13 @@ impl<'d> CanConfigurator<'d> {
     }
 }
 
-impl<'d> Drop for CanConfigurator<'d> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-    }
-}
-
 /// FDCAN Instance
 pub struct Can<'d> {
     _phantom: PhantomData<&'d ()>,
     config: crate::can::fd::config::FdCanConfig,
-    info: &'static Info,
     _mode: OperatingMode,
     properties: Properties,
+    info: InfoRef,
 }
 
 impl<'d> Can<'d> {
@@ -341,12 +331,12 @@ impl<'d> Can<'d> {
     /// can be replaced, this call asynchronously waits for a frame to be successfully
     /// transmitted, then tries again.
     pub async fn write(&mut self, frame: &Frame) -> Option<Frame> {
-        TxMode::write(self.info, frame).await
+        TxMode::write(&self.info, frame).await
     }
 
     /// Returns the next received message frame
     pub async fn read(&mut self) -> Result<Envelope, BusError> {
-        RxMode::read_classic(self.info).await
+        RxMode::read_classic(&self.info).await
     }
 
     /// Queues the message to be sent but exerts backpressure.  If a lower-priority
@@ -354,29 +344,27 @@ impl<'d> Can<'d> {
     /// can be replaced, this call asynchronously waits for a frame to be successfully
     /// transmitted, then tries again.
     pub async fn write_fd(&mut self, frame: &FdFrame) -> Option<FdFrame> {
-        TxMode::write_fd(self.info, frame).await
+        TxMode::write_fd(&self.info, frame).await
     }
 
     /// Returns the next received message frame
     pub async fn read_fd(&mut self) -> Result<FdEnvelope, BusError> {
-        RxMode::read_fd(self.info).await
+        RxMode::read_fd(&self.info).await
     }
 
     /// Split instance into separate portions: Tx(write), Rx(read), common properties
     pub fn split(self) -> (CanTx<'d>, CanRx<'d>, Properties) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         (
             CanTx {
                 _phantom: PhantomData,
-                info: self.info,
                 config: self.config,
                 _mode: self._mode,
+                info: TxInfoRef::new(&self.info),
             },
             CanRx {
                 _phantom: PhantomData,
-                info: self.info,
                 _mode: self._mode,
+                info: RxInfoRef::new(&self.info),
             },
             Properties {
                 info: self.properties.info,
@@ -385,14 +373,12 @@ impl<'d> Can<'d> {
     }
     /// Join split rx and tx portions back together
     pub fn join(tx: CanTx<'d>, rx: CanRx<'d>) -> Self {
-        (tx.info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (tx.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         Can {
             _phantom: PhantomData,
             config: tx.config,
-            info: tx.info,
             _mode: rx._mode,
-            properties: Properties::new(tx.info),
+            properties: Properties::new(&tx.info),
+            info: InfoRef::new(&tx.info),
         }
     }
 
@@ -402,7 +388,7 @@ impl<'d> Can<'d> {
         tx_buf: &'static mut TxBuf<TX_BUF_SIZE>,
         rxb: &'static mut RxBuf<RX_BUF_SIZE>,
     ) -> BufferedCan<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
-        BufferedCan::new(self.info, self._mode, tx_buf, rxb)
+        BufferedCan::new(&self.info, self._mode, tx_buf, rxb)
     }
 
     /// Return a buffered instance of driver with CAN FD support. User must supply Buffers
@@ -411,14 +397,7 @@ impl<'d> Can<'d> {
         tx_buf: &'static mut TxFdBuf<TX_BUF_SIZE>,
         rxb: &'static mut RxFdBuf<RX_BUF_SIZE>,
     ) -> BufferedCanFd<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
-        BufferedCanFd::new(self.info, self._mode, tx_buf, rxb)
-    }
-}
-
-impl<'d> Drop for Can<'d> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
+        BufferedCanFd::new(&self.info, self._mode, tx_buf, rxb)
     }
 }
 
@@ -431,11 +410,11 @@ pub type TxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, Frame,
 /// Buffered FDCAN Instance
 pub struct BufferedCan<'d, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
     _mode: OperatingMode,
     tx_buf: &'static TxBuf<TX_BUF_SIZE>,
     rx_buf: &'static RxBuf<RX_BUF_SIZE>,
     properties: Properties,
+    info: InfoRef,
 }
 
 impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
@@ -445,15 +424,13 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d,
         tx_buf: &'static TxBuf<TX_BUF_SIZE>,
         rx_buf: &'static RxBuf<RX_BUF_SIZE>,
     ) -> Self {
-        (info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         BufferedCan {
             _phantom: PhantomData,
-            info,
             _mode,
             tx_buf,
             rx_buf,
             properties: Properties::new(info),
+            info: InfoRef::new(info),
         }
         .setup()
     }
@@ -492,31 +469,21 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d,
 
     /// Returns a sender that can be used for sending CAN frames.
     pub fn writer(&self) -> BufferedCanSender {
-        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
         BufferedCanSender {
             tx_buf: self.tx_buf.sender().into(),
-            waker: self.info.tx_waker,
-            internal_operation: self.info.internal_operation,
+            info: TxInfoRef::new(&self.info),
         }
     }
 
     /// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
     pub fn reader(&self) -> BufferedCanReceiver {
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         BufferedCanReceiver {
             rx_buf: self.rx_buf.receiver().into(),
-            internal_operation: self.info.internal_operation,
+            info: RxInfoRef::new(&self.info),
         }
     }
 }
 
-impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop for BufferedCan<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-    }
-}
-
 /// User supplied buffer for RX Buffering
 pub type RxFdBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, Result<FdEnvelope, BusError>, BUF_SIZE>;
 
@@ -532,11 +499,11 @@ pub type BufferedFdCanReceiver = super::common::BufferedReceiver<'static, FdEnve
 /// Buffered FDCAN Instance
 pub struct BufferedCanFd<'d, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
     _mode: OperatingMode,
     tx_buf: &'static TxFdBuf<TX_BUF_SIZE>,
     rx_buf: &'static RxFdBuf<RX_BUF_SIZE>,
     properties: Properties,
+    info: InfoRef,
 }
 
 impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCanFd<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
@@ -546,15 +513,13 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCanFd<'
         tx_buf: &'static TxFdBuf<TX_BUF_SIZE>,
         rx_buf: &'static RxFdBuf<RX_BUF_SIZE>,
     ) -> Self {
-        (info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         BufferedCanFd {
             _phantom: PhantomData,
-            info,
             _mode,
             tx_buf,
             rx_buf,
             properties: Properties::new(info),
+            info: InfoRef::new(info),
         }
         .setup()
     }
@@ -593,36 +558,26 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCanFd<'
 
     /// Returns a sender that can be used for sending CAN frames.
     pub fn writer(&self) -> BufferedFdCanSender {
-        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
         BufferedFdCanSender {
             tx_buf: self.tx_buf.sender().into(),
-            waker: self.info.tx_waker,
-            internal_operation: self.info.internal_operation,
+            info: TxInfoRef::new(&self.info),
         }
     }
 
     /// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
     pub fn reader(&self) -> BufferedFdCanReceiver {
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         BufferedFdCanReceiver {
             rx_buf: self.rx_buf.receiver().into(),
-            internal_operation: self.info.internal_operation,
+            info: RxInfoRef::new(&self.info),
         }
     }
 }
 
-impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop for BufferedCanFd<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-    }
-}
-
 /// FDCAN Rx only Instance
 pub struct CanRx<'d> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
     _mode: OperatingMode,
+    info: RxInfoRef,
 }
 
 impl<'d> CanRx<'d> {
@@ -637,18 +592,12 @@ impl<'d> CanRx<'d> {
     }
 }
 
-impl<'d> Drop for CanRx<'d> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-    }
-}
-
 /// FDCAN Tx only Instance
 pub struct CanTx<'d> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
     config: crate::can::fd::config::FdCanConfig,
     _mode: OperatingMode,
+    info: TxInfoRef,
 }
 
 impl<'c, 'd> CanTx<'d> {
@@ -657,7 +606,7 @@ impl<'c, 'd> CanTx<'d> {
     /// can be replaced, this call asynchronously waits for a frame to be successfully
     /// transmitted, then tries again.
     pub async fn write(&mut self, frame: &Frame) -> Option<Frame> {
-        TxMode::write(self.info, frame).await
+        TxMode::write(&self.info, frame).await
     }
 
     /// Queues the message to be sent but exerts backpressure.  If a lower-priority
@@ -665,13 +614,7 @@ impl<'c, 'd> CanTx<'d> {
     /// can be replaced, this call asynchronously waits for a frame to be successfully
     /// transmitted, then tries again.
     pub async fn write_fd(&mut self, frame: &FdFrame) -> Option<FdFrame> {
-        TxMode::write_fd(self.info, frame).await
-    }
-}
-
-impl<'d> Drop for CanTx<'d> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
+        TxMode::write_fd(&self.info, frame).await
     }
 }
 
@@ -938,21 +881,56 @@ impl State {
 }
 
 type SharedState = embassy_sync::blocking_mutex::Mutex<CriticalSectionRawMutex, core::cell::RefCell<State>>;
-struct Info {
+pub(crate) struct Info {
     regs: Registers,
     interrupt0: crate::interrupt::Interrupt,
     _interrupt1: crate::interrupt::Interrupt,
-    tx_waker: fn(),
-    internal_operation: fn(InternalOperation),
+    pub(crate) tx_waker: fn(),
     state: SharedState,
 }
 
+impl Info {
+    pub(crate) fn adjust_reference_counter(&self, val: RefCountOp) {
+        self.state.lock(|s| {
+            let mut mut_state = s.borrow_mut();
+            match val {
+                RefCountOp::NotifySenderCreated => {
+                    mut_state.sender_instance_count += 1;
+                }
+                RefCountOp::NotifySenderDestroyed => {
+                    mut_state.sender_instance_count -= 1;
+                    if 0 == mut_state.sender_instance_count {
+                        (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                    }
+                }
+                RefCountOp::NotifyReceiverCreated => {
+                    mut_state.receiver_instance_count += 1;
+                }
+                RefCountOp::NotifyReceiverDestroyed => {
+                    mut_state.receiver_instance_count -= 1;
+                    if 0 == mut_state.receiver_instance_count {
+                        (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                    }
+                }
+            }
+            if mut_state.sender_instance_count == 0 && mut_state.receiver_instance_count == 0 {
+                unsafe {
+                    let tx_pin = crate::gpio::AnyPin::steal(mut_state.tx_pin_port.unwrap());
+                    tx_pin.set_as_disconnected();
+                    let rx_pin = crate::gpio::AnyPin::steal(mut_state.rx_pin_port.unwrap());
+                    rx_pin.set_as_disconnected();
+                    self.interrupt0.disable();
+                }
+            }
+        });
+    }
+}
+
 trait SealedInstance {
     const MSG_RAM_OFFSET: usize;
 
     fn info() -> &'static Info;
     fn registers() -> crate::can::fd::peripheral::Registers;
-    fn internal_operation(val: InternalOperation);
 }
 
 /// Instance trait
@@ -974,41 +952,6 @@ macro_rules! impl_fdcan {
         impl SealedInstance for peripherals::$inst {
             const MSG_RAM_OFFSET: usize = $msg_ram_offset;
 
-            fn internal_operation(val: InternalOperation) {
-                peripherals::$inst::info().state.lock(|s| {
-                    let mut mut_state = s.borrow_mut();
-                    match val {
-                        InternalOperation::NotifySenderCreated => {
-                            mut_state.sender_instance_count += 1;
-                        }
-                        InternalOperation::NotifySenderDestroyed => {
-                            mut_state.sender_instance_count -= 1;
-                            if ( 0 == mut_state.sender_instance_count) {
-                                (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-                            }
-                        }
-                        InternalOperation::NotifyReceiverCreated => {
-                            mut_state.receiver_instance_count += 1;
-                        }
-                        InternalOperation::NotifyReceiverDestroyed => {
-                            mut_state.receiver_instance_count -= 1;
-                            if ( 0 == mut_state.receiver_instance_count) {
-                                (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-                            }
-                        }
-                    }
-                    if mut_state.sender_instance_count == 0 && mut_state.receiver_instance_count == 0 {
-                        unsafe {
-                            let tx_pin = crate::gpio::AnyPin::steal(mut_state.tx_pin_port.unwrap());
-                            tx_pin.set_as_disconnected();
-                            let rx_pin = crate::gpio::AnyPin::steal(mut_state.rx_pin_port.unwrap());
-                            rx_pin.set_as_disconnected();
-                            rcc::disable::<peripherals::$inst>();
-                        }
-                    }
-                });
-            }
-
             fn info() -> &'static Info {
 
                 static INFO: Info = Info {
@@ -1016,7 +959,6 @@ macro_rules! impl_fdcan {
                     interrupt0: crate::_generated::peripheral_interrupts::$inst::IT0::IRQ,
                     _interrupt1: crate::_generated::peripheral_interrupts::$inst::IT1::IRQ,
                     tx_waker: crate::_generated::peripheral_interrupts::$inst::IT0::pend,
-                    internal_operation: peripherals::$inst::internal_operation,
                     state: embassy_sync::blocking_mutex::Mutex::new(core::cell::RefCell::new(State::new())),
                 };
                 &INFO
diff --git a/embassy-stm32/src/cordic/utils.rs b/embassy-stm32/src/cordic/utils.rs
index 008f50270..9afa8ef53 100644
--- a/embassy-stm32/src/cordic/utils.rs
+++ b/embassy-stm32/src/cordic/utils.rs
@@ -5,7 +5,7 @@ macro_rules! floating_fixed_convert {
     ($f_to_q:ident, $q_to_f:ident, $unsigned_bin_typ:ty, $signed_bin_typ:ty, $float_ty:ty, $offset:literal, $min_positive:literal) => {
         /// convert float point to fixed point format
         pub fn $f_to_q(value: $float_ty) -> Result<$unsigned_bin_typ, NumberOutOfRange> {
-            const MIN_POSITIVE: $float_ty = unsafe { core::mem::transmute($min_positive) };
+            const MIN_POSITIVE: $float_ty = <$float_ty>::from_bits($min_positive);
 
             if value < -1.0 {
                 return Err(NumberOutOfRange::BelowLowerBound)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index fba3c0fd7..35d9f8cce 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -2,7 +2,6 @@
 #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 use core::cmp::min;
 use core::marker::PhantomData;
-use core::ptr;
 
 use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
@@ -1814,14 +1813,12 @@ impl<'d, T: Instance> Cryp<'d, T, Async> {
         assert_eq!(blocks.len() % block_size, 0);
         // Configure DMA to transfer input to crypto core.
         let dst_ptr: *mut u32 = T::regs().din().as_ptr();
-        let num_words = blocks.len() / 4;
-        let src_ptr: *const [u8] = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words);
         let options = TransferOptions {
             #[cfg(not(gpdma))]
             priority: crate::dma::Priority::High,
             ..Default::default()
         };
-        let dma_transfer = unsafe { dma.write_raw(src_ptr, dst_ptr, options) };
+        let dma_transfer = unsafe { dma.write_raw(blocks, dst_ptr, options) };
         T::regs().dmacr().modify(|w| w.set_dien(true));
         // Wait for the transfer to complete.
         dma_transfer.await;
@@ -1836,14 +1833,12 @@ impl<'d, T: Instance> Cryp<'d, T, Async> {
         assert_eq!((blocks.len() * 4) % block_size, 0);
         // Configure DMA to transfer input to crypto core.
         let dst_ptr: *mut u32 = T::regs().din().as_ptr();
-        let num_words = blocks.len();
-        let src_ptr: *const [u32] = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words);
         let options = TransferOptions {
             #[cfg(not(gpdma))]
             priority: crate::dma::Priority::High,
             ..Default::default()
         };
-        let dma_transfer = unsafe { dma.write_raw(src_ptr, dst_ptr, options) };
+        let dma_transfer = unsafe { dma.write_raw(blocks, dst_ptr, options) };
         T::regs().dmacr().modify(|w| w.set_dien(true));
         // Wait for the transfer to complete.
         dma_transfer.await;
@@ -1857,14 +1852,12 @@ impl<'d, T: Instance> Cryp<'d, T, Async> {
         assert_eq!(blocks.len() % block_size, 0);
         // Configure DMA to get output from crypto core.
         let src_ptr = T::regs().dout().as_ptr();
-        let num_words = blocks.len() / 4;
-        let dst_ptr = ptr::slice_from_raw_parts_mut(blocks.as_mut_ptr().cast(), num_words);
         let options = TransferOptions {
             #[cfg(not(gpdma))]
             priority: crate::dma::Priority::VeryHigh,
             ..Default::default()
         };
-        let dma_transfer = unsafe { dma.read_raw(src_ptr, dst_ptr, options) };
+        let dma_transfer = unsafe { dma.read_raw(src_ptr, blocks, options) };
         T::regs().dmacr().modify(|w| w.set_doen(true));
         // Wait for the transfer to complete.
         dma_transfer.await;
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 30046849b..d8f1f96f2 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -403,6 +403,46 @@ impl<'d, T: Instance> Dac<'d, T, Async> {
             Mode::NormalExternalBuffered,
         )
     }
+    /// Create a new `Dac` instance with external output pins and unbuffered mode.
+    ///
+    /// This function consumes the underlying DAC peripheral and allows access to both channels.
+    /// The channels are configured for external output with the buffer disabled.
+    ///
+    /// The channels are enabled on creation and begin to drive their output pins.
+    /// Note that some methods, such as `set_trigger()` and `set_mode()`, will
+    /// disable the channel; you must re-enable them with `enable()`.
+    ///
+    /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
+    /// method on the underlying channels.
+    ///
+    /// # Arguments
+    ///
+    /// * `peri` - The DAC peripheral instance.
+    /// * `dma_ch1` - The DMA channel for DAC channel 1.
+    /// * `dma_ch2` - The DMA channel for DAC channel 2.
+    /// * `pin_ch1` - The GPIO pin for DAC channel 1 output.
+    /// * `pin_ch2` - The GPIO pin for DAC channel 2 output.
+    ///
+    /// # Returns
+    ///
+    /// A new `Dac` instance in unbuffered mode.
+    pub fn new_unbuffered(
+        peri: Peri<'d, T>,
+        dma_ch1: Peri<'d, impl Dma<T, Ch1>>,
+        dma_ch2: Peri<'d, impl Dma<T, Ch2>>,
+        pin_ch1: Peri<'d, impl DacPin<T, Ch1> + crate::gpio::Pin>,
+        pin_ch2: Peri<'d, impl DacPin<T, Ch2> + crate::gpio::Pin>,
+    ) -> Self {
+        pin_ch1.set_as_analog();
+        pin_ch2.set_as_analog();
+        Self::new_inner(
+            peri,
+            new_dma!(dma_ch1),
+            new_dma!(dma_ch2),
+            #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
+            Mode::NormalExternalUnbuffered,
+        )
+    }
 
     /// Create a new `Dac` instance where the external output pins are not used,
     /// so the DAC can only be used to generate internal signals but the GPIO
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
index 7dbbe7b72..464823bfc 100644
--- a/embassy-stm32/src/dma/dma_bdma.rs
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -341,9 +341,12 @@ impl AnyChannel {
         mem_len: usize,
         incr_mem: bool,
         mem_size: WordSize,
-        peripheral_size: WordSize,
+        peri_size: WordSize,
         options: TransferOptions,
     ) {
+        // "Preceding reads and writes cannot be moved past subsequent writes."
+        fence(Ordering::SeqCst);
+
         let info = self.info();
         #[cfg(feature = "_dual-core")]
         {
@@ -354,28 +357,48 @@ impl AnyChannel {
         #[cfg(dmamux)]
         super::dmamux::configure_dmamux(&info.dmamux, _request);
 
-        assert!(mem_len > 0 && mem_len <= 0xFFFF);
-
         match self.info().dma {
             #[cfg(dma)]
             DmaInfo::Dma(r) => {
                 let state: &ChannelState = &STATE[self.id as usize];
                 let ch = r.st(info.num);
 
-                // "Preceding reads and writes cannot be moved past subsequent writes."
-                fence(Ordering::SeqCst);
-
                 state.complete_count.store(0, Ordering::Release);
                 self.clear_irqs();
 
+                // NDTR is the number of transfers in the *peripheral* word size.
+                // ex: if mem_size=1, peri_size=4 and ndtr=3 it'll do 12 mem transfers, 3 peri transfers.
+                let ndtr = match (mem_size, peri_size) {
+                    (WordSize::FourBytes, WordSize::OneByte) => mem_len * 4,
+                    (WordSize::FourBytes, WordSize::TwoBytes) | (WordSize::TwoBytes, WordSize::OneByte) => mem_len * 2,
+                    (WordSize::FourBytes, WordSize::FourBytes)
+                    | (WordSize::TwoBytes, WordSize::TwoBytes)
+                    | (WordSize::OneByte, WordSize::OneByte) => mem_len,
+                    (WordSize::TwoBytes, WordSize::FourBytes) | (WordSize::OneByte, WordSize::TwoBytes) => {
+                        assert!(mem_len % 2 == 0);
+                        mem_len / 2
+                    }
+                    (WordSize::OneByte, WordSize::FourBytes) => {
+                        assert!(mem_len % 4 == 0);
+                        mem_len / 4
+                    }
+                };
+
+                assert!(ndtr > 0 && ndtr <= 0xFFFF);
+
                 ch.par().write_value(peri_addr as u32);
                 ch.m0ar().write_value(mem_addr as u32);
-                ch.ndtr().write_value(pac::dma::regs::Ndtr(mem_len as _));
+                ch.ndtr().write_value(pac::dma::regs::Ndtr(ndtr as _));
                 ch.fcr().write(|w| {
                     if let Some(fth) = options.fifo_threshold {
                         // FIFO mode
                         w.set_dmdis(pac::dma::vals::Dmdis::DISABLED);
                         w.set_fth(fth.into());
+                    } else if mem_size != peri_size {
+                        // force FIFO mode if msize != psize
+                        // packing/unpacking doesn't work in direct mode.
+                        w.set_dmdis(pac::dma::vals::Dmdis::DISABLED);
+                        w.set_fth(FifoThreshold::Half.into());
                     } else {
                         // Direct mode
                         w.set_dmdis(pac::dma::vals::Dmdis::ENABLED);
@@ -384,7 +407,7 @@ impl AnyChannel {
                 ch.cr().write(|w| {
                     w.set_dir(dir.into());
                     w.set_msize(mem_size.into());
-                    w.set_psize(peripheral_size.into());
+                    w.set_psize(peri_size.into());
                     w.set_pl(options.priority.into());
                     w.set_minc(incr_mem);
                     w.set_pinc(false);
@@ -404,6 +427,8 @@ impl AnyChannel {
             }
             #[cfg(bdma)]
             DmaInfo::Bdma(r) => {
+                assert!(mem_len > 0 && mem_len <= 0xFFFF);
+
                 #[cfg(bdma_v2)]
                 critical_section::with(|_| r.cselr().modify(|w| w.set_cs(info.num, _request)));
 
@@ -417,7 +442,7 @@ impl AnyChannel {
                 ch.mar().write_value(mem_addr as u32);
                 ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
                 ch.cr().write(|w| {
-                    w.set_psize(peripheral_size.into());
+                    w.set_psize(peri_size.into());
                     w.set_msize(mem_size.into());
                     w.set_minc(incr_mem);
                     w.set_dir(dir.into());
@@ -587,11 +612,11 @@ impl<'a> Transfer<'a> {
     }
 
     /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
-    pub unsafe fn new_read_raw<W: Word>(
+    pub unsafe fn new_read_raw<MW: Word, PW: Word>(
         channel: Peri<'a, impl Channel>,
         request: Request,
-        peri_addr: *mut W,
-        buf: *mut [W],
+        peri_addr: *mut PW,
+        buf: *mut [MW],
         options: TransferOptions,
     ) -> Self {
         Self::new_inner(
@@ -599,11 +624,11 @@ impl<'a> Transfer<'a> {
             request,
             Dir::PeripheralToMemory,
             peri_addr as *const u32,
-            buf as *mut W as *mut u32,
+            buf as *mut MW as *mut u32,
             buf.len(),
             true,
-            W::size(),
-            W::size(),
+            MW::size(),
+            PW::size(),
             options,
         )
     }
@@ -672,22 +697,14 @@ impl<'a> Transfer<'a> {
         mem_addr: *mut u32,
         mem_len: usize,
         incr_mem: bool,
-        data_size: WordSize,
-        peripheral_size: WordSize,
+        mem_size: WordSize,
+        peri_size: WordSize,
         options: TransferOptions,
     ) -> Self {
         assert!(mem_len > 0 && mem_len <= 0xFFFF);
 
         channel.configure(
-            _request,
-            dir,
-            peri_addr,
-            mem_addr,
-            mem_len,
-            incr_mem,
-            data_size,
-            peripheral_size,
-            options,
+            _request, dir, peri_addr, mem_addr, mem_len, incr_mem, mem_size, peri_size, options,
         );
         channel.start();
         Self { channel }
diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs
index ade70fb55..151e4ab9f 100644
--- a/embassy-stm32/src/dma/gpdma.rs
+++ b/embassy-stm32/src/dma/gpdma.rs
@@ -125,11 +125,11 @@ impl<'a> Transfer<'a> {
     }
 
     /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
-    pub unsafe fn new_read_raw<W: Word>(
+    pub unsafe fn new_read_raw<MW: Word, PW: Word>(
         channel: Peri<'a, impl Channel>,
         request: Request,
-        peri_addr: *mut W,
-        buf: *mut [W],
+        peri_addr: *mut PW,
+        buf: *mut [MW],
         options: TransferOptions,
     ) -> Self {
         Self::new_inner(
@@ -137,11 +137,11 @@ impl<'a> Transfer<'a> {
             request,
             Dir::PeripheralToMemory,
             peri_addr as *const u32,
-            buf as *mut W as *mut u32,
+            buf as *mut MW as *mut u32,
             buf.len(),
             true,
-            W::size(),
-            W::size(),
+            PW::size(),
+            MW::size(),
             options,
         )
     }
diff --git a/embassy-stm32/src/dma/util.rs b/embassy-stm32/src/dma/util.rs
index 8bf89e2fe..3245887c1 100644
--- a/embassy-stm32/src/dma/util.rs
+++ b/embassy-stm32/src/dma/util.rs
@@ -20,10 +20,10 @@ impl<'d> ChannelAndRequest<'d> {
         Transfer::new_read(self.channel.reborrow(), self.request, peri_addr, buf, options)
     }
 
-    pub unsafe fn read_raw<'a, W: Word>(
+    pub unsafe fn read_raw<'a, MW: Word, PW: Word>(
         &'a mut self,
-        peri_addr: *mut W,
-        buf: *mut [W],
+        peri_addr: *mut PW,
+        buf: *mut [MW],
         options: TransferOptions,
     ) -> Transfer<'a> {
         Transfer::new_read_raw(self.channel.reborrow(), self.request, peri_addr, buf, options)
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index 01e321bce..b9746231f 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -122,7 +122,10 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
 
             // Select RMII (Reduced Media Independent Interface)
             // Must be done prior to enabling peripheral clock
-            AFIO.mapr().modify(|w| w.set_mii_rmii_sel(true));
+            AFIO.mapr().modify(|w| {
+                w.set_mii_rmii_sel(true);
+                w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
+            });
 
             RCC.ahbenr().modify(|w| {
                 w.set_ethen(true);
@@ -316,7 +319,10 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
 
             // Select MII (Media Independent Interface)
             // Must be done prior to enabling peripheral clock
-            AFIO.mapr().modify(|w| w.set_mii_rmii_sel(false));
+            AFIO.mapr().modify(|w| {
+                w.set_mii_rmii_sel(false);
+                w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
+            });
 
             RCC.ahbenr().modify(|w| {
                 w.set_ethen(true);
diff --git a/embassy-stm32/src/flash/u5.rs b/embassy-stm32/src/flash/u5.rs
index 131caa195..6c3d4b422 100644
--- a/embassy-stm32/src/flash/u5.rs
+++ b/embassy-stm32/src/flash/u5.rs
@@ -30,19 +30,19 @@ pub(crate) unsafe fn enable_blocking_write() {
 
     #[cfg(feature = "trustzone-secure")]
     pac::FLASH.seccr().write(|w| {
-        w.set_pg(pac::flash::vals::SeccrPg::B_0X1);
+        w.set_pg(true);
     });
     #[cfg(not(feature = "trustzone-secure"))]
     pac::FLASH.nscr().write(|w| {
-        w.set_pg(pac::flash::vals::NscrPg::B_0X1);
+        w.set_pg(true);
     });
 }
 
 pub(crate) unsafe fn disable_blocking_write() {
     #[cfg(feature = "trustzone-secure")]
-    pac::FLASH.seccr().write(|w| w.set_pg(pac::flash::vals::SeccrPg::B_0X0));
+    pac::FLASH.seccr().write(|w| w.set_pg(false));
     #[cfg(not(feature = "trustzone-secure"))]
-    pac::FLASH.nscr().write(|w| w.set_pg(pac::flash::vals::NscrPg::B_0X0));
+    pac::FLASH.nscr().write(|w| w.set_pg(false));
 }
 
 pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
@@ -65,19 +65,19 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
         w.set_pnb(sector.index_in_bank);
         // TODO: add check for bank swap
         w.set_bker(match sector.bank {
-            FlashBank::Bank1 => pac::flash::vals::SeccrBker::B_0X0,
-            FlashBank::Bank2 => pac::flash::vals::SeccrBker::B_0X1,
+            FlashBank::Bank1 => false,
+            FlashBank::Bank2 => true,
             _ => unreachable!(),
         });
     });
     #[cfg(not(feature = "trustzone-secure"))]
     pac::FLASH.nscr().modify(|w| {
-        w.set_per(pac::flash::vals::NscrPer::B_0X1);
+        w.set_per(true);
         w.set_pnb(sector.index_in_bank);
         // TODO: add check for bank swap
         w.set_bker(match sector.bank {
-            FlashBank::Bank1 => pac::flash::vals::NscrBker::B_0X0,
-            FlashBank::Bank2 => pac::flash::vals::NscrBker::B_0X1,
+            FlashBank::Bank1 => false,
+            FlashBank::Bank2 => true,
             _ => unreachable!(),
         });
     });
@@ -93,13 +93,9 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
 
     let ret: Result<(), Error> = blocking_wait_ready();
     #[cfg(feature = "trustzone-secure")]
-    pac::FLASH
-        .seccr()
-        .modify(|w| w.set_per(pac::flash::vals::SeccrPer::B_0X0));
+    pac::FLASH.seccr().modify(|w| w.set_per(false));
     #[cfg(not(feature = "trustzone-secure"))]
-    pac::FLASH
-        .nscr()
-        .modify(|w| w.set_per(pac::flash::vals::NscrPer::B_0X0));
+    pac::FLASH.nscr().modify(|w| w.set_per(false));
     clear_all_err();
     ret
 }
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index 31527bcdb..573a1851d 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -3,7 +3,7 @@
 use embassy_hal_internal::PeripheralType;
 
 use crate::pac;
-use crate::rcc::RccPeripheral;
+use crate::rcc::{self, RccPeripheral};
 // TODO: This code works for all HSEM implemenations except for the STM32WBA52/4/5xx MCUs.
 // Those MCUs have a different HSEM implementation (Secure semaphore lock support,
 // Privileged / unprivileged semaphore lock support, Semaphore lock protection via semaphore attribute),
@@ -46,7 +46,7 @@ pub enum CoreId {
 #[inline(always)]
 pub fn get_current_coreid() -> CoreId {
     let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() };
-    match cpuid & 0x000000F0 {
+    match (cpuid & 0x000000F0) >> 4 {
         #[cfg(any(stm32wb, stm32wl))]
         0x0 => CoreId::Core1,
 
@@ -80,6 +80,8 @@ pub struct HardwareSemaphore<'d, T: Instance> {
 impl<'d, T: Instance> HardwareSemaphore<'d, T> {
     /// Creates a new HardwareSemaphore instance.
     pub fn new(peripheral: Peri<'d, T>) -> Self {
+        rcc::enable_and_reset::<T>();
+
         HardwareSemaphore { _peri: peripheral }
     }
 
diff --git a/embassy-stm32/src/i2c/config.rs b/embassy-stm32/src/i2c/config.rs
new file mode 100644
index 000000000..daae43bcd
--- /dev/null
+++ b/embassy-stm32/src/i2c/config.rs
@@ -0,0 +1,170 @@
+#[cfg(gpio_v2)]
+use crate::gpio::Pull;
+use crate::gpio::{AfType, OutputType, Speed};
+
+#[repr(u8)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Bits of the I2C OA2 register to mask out.
+pub enum AddrMask {
+    /// No mask
+    NOMASK,
+    /// OA2\[1\] is masked and don’t care. Only OA2\[7:2\] are compared.
+    MASK1,
+    /// OA2\[2:1\] are masked and don’t care. Only OA2\[7:3\] are compared.
+    MASK2,
+    /// OA2\[3:1\] are masked and don’t care. Only OA2\[7:4\] are compared.
+    MASK3,
+    /// OA2\[4:1\] are masked and don’t care. Only OA2\[7:5\] are compared.
+    MASK4,
+    /// OA2\[5:1\] are masked and don’t care. Only OA2\[7:6\] are compared.
+    MASK5,
+    /// OA2\[6:1\] are masked and don’t care. Only OA2\[7:6\] are compared.
+    MASK6,
+    /// OA2\[7:1\] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
+    MASK7,
+}
+
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// An I2C address. Either 7 or 10 bit.
+pub enum Address {
+    /// A 7 bit address
+    SevenBit(u8),
+    /// A 10 bit address.
+    ///
+    /// When using an address to configure the Own Address, only the OA1 register can be set to a 10-bit address.
+    TenBit(u16),
+}
+impl From<u8> for Address {
+    fn from(value: u8) -> Self {
+        Address::SevenBit(value)
+    }
+}
+impl From<u16> for Address {
+    fn from(value: u16) -> Self {
+        assert!(value < 0x400, "Ten bit address must be less than 0x400");
+        Address::TenBit(value)
+    }
+}
+impl Address {
+    /// Get the inner address as a u16.
+    ///
+    /// For 7 bit addresses, the u8 that was used to store the address is returned as a u16.
+    pub fn addr(&self) -> u16 {
+        match self {
+            Address::SevenBit(addr) => *addr as u16,
+            Address::TenBit(addr) => *addr,
+        }
+    }
+}
+
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// The second Own Address register.
+pub struct OA2 {
+    /// The address.
+    pub addr: u8,
+    /// The bit mask that will affect how the own address 2 register is compared.
+    pub mask: AddrMask,
+}
+
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// The Own Address(es) of the I2C peripheral.
+pub enum OwnAddresses {
+    /// Configuration for only the OA1 register.
+    OA1(Address),
+    /// Configuration for only the OA2 register.
+    OA2(OA2),
+    /// Configuration for both the OA1 and OA2 registers.
+    Both {
+        /// The [Address] for the OA1 register.
+        oa1: Address,
+        /// The [OA2] configuration.
+        oa2: OA2,
+    },
+}
+
+/// Slave Configuration
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct SlaveAddrConfig {
+    /// Target Address(es)
+    pub addr: OwnAddresses,
+    /// Control if the peripheral should respond to the general call address
+    pub general_call: bool,
+}
+impl SlaveAddrConfig {
+    /// Create a new slave address configuration with only the OA1 register set in 7 bit mode and the general call disabled.
+    pub fn basic(addr: u8) -> Self {
+        Self {
+            addr: OwnAddresses::OA1(Address::SevenBit(addr)),
+            general_call: false,
+        }
+    }
+}
+
+/// I2C config
+#[non_exhaustive]
+#[derive(Copy, Clone)]
+pub struct Config {
+    /// Enable internal pullup on SDA.
+    ///
+    /// Using external pullup resistors is recommended for I2C. If you do
+    /// have external pullups you should not enable this.
+    #[cfg(gpio_v2)]
+    pub sda_pullup: bool,
+    /// Enable internal pullup on SCL.
+    ///
+    /// Using external pullup resistors is recommended for I2C. If you do
+    /// have external pullups you should not enable this.
+    #[cfg(gpio_v2)]
+    pub scl_pullup: bool,
+    /// Timeout.
+    #[cfg(feature = "time")]
+    pub timeout: embassy_time::Duration,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            #[cfg(gpio_v2)]
+            sda_pullup: false,
+            #[cfg(gpio_v2)]
+            scl_pullup: false,
+            #[cfg(feature = "time")]
+            timeout: embassy_time::Duration::from_millis(1000),
+        }
+    }
+}
+
+impl Config {
+    pub(super) fn scl_af(&self) -> AfType {
+        #[cfg(gpio_v1)]
+        return AfType::output(OutputType::OpenDrain, Speed::Medium);
+        #[cfg(gpio_v2)]
+        return AfType::output_pull(
+            OutputType::OpenDrain,
+            Speed::Medium,
+            match self.scl_pullup {
+                true => Pull::Up,
+                false => Pull::Down,
+            },
+        );
+    }
+
+    pub(super) fn sda_af(&self) -> AfType {
+        #[cfg(gpio_v1)]
+        return AfType::output(OutputType::OpenDrain, Speed::Medium);
+        #[cfg(gpio_v2)]
+        return AfType::output_pull(
+            OutputType::OpenDrain,
+            Speed::Medium,
+            match self.sda_pullup {
+                true => Pull::Up,
+                false => Pull::Down,
+            },
+        );
+    }
+}
diff --git a/embassy-stm32/src/i2c/mod.rs b/embassy-stm32/src/i2c/mod.rs
index 1689fdb84..825dd240c 100644
--- a/embassy-stm32/src/i2c/mod.rs
+++ b/embassy-stm32/src/i2c/mod.rs
@@ -5,19 +5,22 @@
 #[cfg_attr(any(i2c_v2, i2c_v3), path = "v2.rs")]
 mod _version;
 
+mod config;
+
 use core::future::Future;
 use core::iter;
 use core::marker::PhantomData;
 
+pub use config::*;
 use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 #[cfg(feature = "time")]
 use embassy_time::{Duration, Instant};
+use mode::MasterMode;
+pub use mode::{Master, MultiMaster};
 
 use crate::dma::ChannelAndRequest;
-#[cfg(gpio_v2)]
-use crate::gpio::Pull;
-use crate::gpio::{AfType, AnyPin, OutputType, SealedPin as _, Speed};
+use crate::gpio::{AnyPin, SealedPin as _};
 use crate::interrupt::typelevel::Interrupt;
 use crate::mode::{Async, Blocking, Mode};
 use crate::rcc::{RccInfo, SealedRccPeripheral};
@@ -62,85 +65,89 @@ impl core::fmt::Display for Error {
 
 impl core::error::Error for Error {}
 
-/// I2C config
-#[non_exhaustive]
-#[derive(Copy, Clone)]
-pub struct Config {
-    /// Enable internal pullup on SDA.
-    ///
-    /// Using external pullup resistors is recommended for I2C. If you do
-    /// have external pullups you should not enable this.
-    #[cfg(gpio_v2)]
-    pub sda_pullup: bool,
-    /// Enable internal pullup on SCL.
-    ///
-    /// Using external pullup resistors is recommended for I2C. If you do
-    /// have external pullups you should not enable this.
-    #[cfg(gpio_v2)]
-    pub scl_pullup: bool,
-    /// Timeout.
-    #[cfg(feature = "time")]
-    pub timeout: embassy_time::Duration,
+/// I2C modes
+pub mod mode {
+    trait SealedMode {}
+
+    /// Trait for I2C master operations.
+    #[allow(private_bounds)]
+    pub trait MasterMode: SealedMode {}
+
+    /// Mode allowing for I2C master operations.
+    pub struct Master;
+    /// Mode allowing for I2C master and slave operations.
+    pub struct MultiMaster;
+
+    impl SealedMode for Master {}
+    impl MasterMode for Master {}
+
+    impl SealedMode for MultiMaster {}
+    impl MasterMode for MultiMaster {}
 }
 
-impl Default for Config {
-    fn default() -> Self {
-        Self {
-            #[cfg(gpio_v2)]
-            sda_pullup: false,
-            #[cfg(gpio_v2)]
-            scl_pullup: false,
-            #[cfg(feature = "time")]
-            timeout: embassy_time::Duration::from_millis(1000),
-        }
-    }
+#[derive(Debug, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// The command kind to the slave from the master
+pub enum SlaveCommandKind {
+    /// Write to the slave
+    Write,
+    /// Read from the slave
+    Read,
 }
 
-impl Config {
-    fn scl_af(&self) -> AfType {
-        #[cfg(gpio_v1)]
-        return AfType::output(OutputType::OpenDrain, Speed::Medium);
-        #[cfg(gpio_v2)]
-        return AfType::output_pull(
-            OutputType::OpenDrain,
-            Speed::Medium,
-            match self.scl_pullup {
-                true => Pull::Up,
-                false => Pull::None,
-            },
-        );
-    }
+#[derive(Debug, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// The command kind to the slave from the master and the address that the slave matched
+pub struct SlaveCommand {
+    /// The kind of command
+    pub kind: SlaveCommandKind,
+    /// The address that the slave matched
+    pub address: Address,
+}
 
-    fn sda_af(&self) -> AfType {
-        #[cfg(gpio_v1)]
-        return AfType::output(OutputType::OpenDrain, Speed::Medium);
-        #[cfg(gpio_v2)]
-        return AfType::output_pull(
-            OutputType::OpenDrain,
-            Speed::Medium,
-            match self.sda_pullup {
-                true => Pull::Up,
-                false => Pull::None,
-            },
-        );
+#[derive(Debug, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// The status of the slave send operation
+pub enum SendStatus {
+    /// The slave send operation is done, all bytes have been sent and the master is not requesting more
+    Done,
+    /// The slave send operation is done, but there are leftover bytes that the master did not read
+    LeftoverBytes(usize),
+}
+
+struct I2CDropGuard<'d> {
+    info: &'static Info,
+    scl: Option<Peri<'d, AnyPin>>,
+    sda: Option<Peri<'d, AnyPin>>,
+}
+impl<'d> Drop for I2CDropGuard<'d> {
+    fn drop(&mut self) {
+        if let Some(x) = self.scl.as_ref() {
+            x.set_as_disconnected()
+        }
+        if let Some(x) = self.sda.as_ref() {
+            x.set_as_disconnected()
+        }
+
+        self.info.rcc.disable();
     }
 }
 
 /// I2C driver.
-pub struct I2c<'d, M: Mode> {
+pub struct I2c<'d, M: Mode, IM: MasterMode> {
     info: &'static Info,
     state: &'static State,
     kernel_clock: Hertz,
-    scl: Option<Peri<'d, AnyPin>>,
-    sda: Option<Peri<'d, AnyPin>>,
     tx_dma: Option<ChannelAndRequest<'d>>,
     rx_dma: Option<ChannelAndRequest<'d>>,
     #[cfg(feature = "time")]
     timeout: Duration,
     _phantom: PhantomData<M>,
+    _phantom2: PhantomData<IM>,
+    _drop_guard: I2CDropGuard<'d>,
 }
 
-impl<'d> I2c<'d, Async> {
+impl<'d> I2c<'d, Async, Master> {
     /// Create a new I2C driver.
     pub fn new<T: Instance>(
         peri: Peri<'d, T>,
@@ -166,7 +173,7 @@ impl<'d> I2c<'d, Async> {
     }
 }
 
-impl<'d> I2c<'d, Blocking> {
+impl<'d> I2c<'d, Blocking, Master> {
     /// Create a new blocking I2C driver.
     pub fn new_blocking<T: Instance>(
         peri: Peri<'d, T>,
@@ -187,7 +194,7 @@ impl<'d> I2c<'d, Blocking> {
     }
 }
 
-impl<'d, M: Mode> I2c<'d, M> {
+impl<'d, M: Mode> I2c<'d, M, Master> {
     /// Create a new I2C driver.
     fn new_inner<T: Instance>(
         _peri: Peri<'d, T>,
@@ -205,15 +212,20 @@ impl<'d, M: Mode> I2c<'d, M> {
             info: T::info(),
             state: T::state(),
             kernel_clock: T::frequency(),
-            scl,
-            sda,
             tx_dma,
             rx_dma,
             #[cfg(feature = "time")]
             timeout: config.timeout,
             _phantom: PhantomData,
+            _phantom2: PhantomData,
+            _drop_guard: I2CDropGuard {
+                info: T::info(),
+                scl,
+                sda,
+            },
         };
         this.enable_and_init(freq, config);
+
         this
     }
 
@@ -221,7 +233,9 @@ impl<'d, M: Mode> I2c<'d, M> {
         self.info.rcc.enable_and_reset();
         self.init(freq, config);
     }
+}
 
+impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
     fn timeout(&self) -> Timeout {
         Timeout {
             #[cfg(feature = "time")]
@@ -230,15 +244,6 @@ impl<'d, M: Mode> I2c<'d, M> {
     }
 }
 
-impl<'d, M: Mode> Drop for I2c<'d, M> {
-    fn drop(&mut self) {
-        self.scl.as_ref().map(|x| x.set_as_disconnected());
-        self.sda.as_ref().map(|x| x.set_as_disconnected());
-
-        self.info.rcc.disable()
-    }
-}
-
 #[derive(Copy, Clone)]
 struct Timeout {
     #[cfg(feature = "time")]
@@ -347,7 +352,7 @@ foreach_peripheral!(
     };
 );
 
-impl<'d, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> embedded_hal_02::blocking::i2c::Read for I2c<'d, M, IM> {
     type Error = Error;
 
     fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
@@ -355,7 +360,7 @@ impl<'d, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, M> {
     }
 }
 
-impl<'d, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> embedded_hal_02::blocking::i2c::Write for I2c<'d, M, IM> {
     type Error = Error;
 
     fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
@@ -363,7 +368,7 @@ impl<'d, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, M> {
     }
 }
 
-impl<'d, M: Mode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, M, IM> {
     type Error = Error;
 
     fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
@@ -387,11 +392,11 @@ impl embedded_hal_1::i2c::Error for Error {
     }
 }
 
-impl<'d, M: Mode> embedded_hal_1::i2c::ErrorType for I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> embedded_hal_1::i2c::ErrorType for I2c<'d, M, IM> {
     type Error = Error;
 }
 
-impl<'d, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> embedded_hal_1::i2c::I2c for I2c<'d, M, IM> {
     fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
         self.blocking_read(address, read)
     }
@@ -413,7 +418,7 @@ impl<'d, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, M> {
     }
 }
 
-impl<'d> embedded_hal_async::i2c::I2c for I2c<'d, Async> {
+impl<'d, IM: MasterMode> embedded_hal_async::i2c::I2c for I2c<'d, Async, IM> {
     async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
         self.read(address, read).await
     }
@@ -529,9 +534,7 @@ fn operation_frames<'a, 'b: 'a>(
     let mut next_first_frame = true;
 
     Ok(iter::from_fn(move || {
-        let Some(op) = operations.next() else {
-            return None;
-        };
+        let op = operations.next()?;
 
         // Is `op` first frame of its type?
         let first_frame = next_first_frame;
diff --git a/embassy-stm32/src/i2c/v1.rs b/embassy-stm32/src/i2c/v1.rs
index 28026f83c..35f13ab46 100644
--- a/embassy-stm32/src/i2c/v1.rs
+++ b/embassy-stm32/src/i2c/v1.rs
@@ -11,6 +11,7 @@ use embassy_embedded_hal::SetConfig;
 use embassy_futures::select::{select, Either};
 use embassy_hal_internal::drop::OnDrop;
 use embedded_hal_1::i2c::Operation;
+use mode::Master;
 
 use super::*;
 use crate::mode::Mode as PeriMode;
@@ -41,7 +42,7 @@ pub unsafe fn on_interrupt<T: Instance>() {
     });
 }
 
-impl<'d, M: PeriMode> I2c<'d, M> {
+impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
     pub(crate) fn init(&mut self, freq: Hertz, _config: Config) {
         self.info.regs.cr1().modify(|reg| {
             reg.set_pe(false);
@@ -354,7 +355,7 @@ impl<'d, M: PeriMode> I2c<'d, M> {
     }
 }
 
-impl<'d> I2c<'d, Async> {
+impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     async fn write_frame(&mut self, address: u8, write: &[u8], frame: FrameOptions) -> Result<(), Error> {
         self.info.regs.cr2().modify(|w| {
             // Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for
@@ -800,7 +801,7 @@ impl Timings {
     }
 }
 
-impl<'d, M: PeriMode> SetConfig for I2c<'d, M> {
+impl<'d, M: PeriMode> SetConfig for I2c<'d, M, Master> {
     type Config = Hertz;
     type ConfigError = ();
     fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 50a25754e..e24cce5c6 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -2,22 +2,87 @@ use core::cmp;
 use core::future::poll_fn;
 use core::task::Poll;
 
+use config::{Address, OwnAddresses, OA2};
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::drop::OnDrop;
 use embedded_hal_1::i2c::Operation;
+use mode::{Master, MultiMaster};
+use stm32_metapac::i2c::vals::{Addmode, Oamsk};
 
 use super::*;
 use crate::pac::i2c;
 
+impl From<AddrMask> for Oamsk {
+    fn from(value: AddrMask) -> Self {
+        match value {
+            AddrMask::NOMASK => Oamsk::NO_MASK,
+            AddrMask::MASK1 => Oamsk::MASK1,
+            AddrMask::MASK2 => Oamsk::MASK2,
+            AddrMask::MASK3 => Oamsk::MASK3,
+            AddrMask::MASK4 => Oamsk::MASK4,
+            AddrMask::MASK5 => Oamsk::MASK5,
+            AddrMask::MASK6 => Oamsk::MASK6,
+            AddrMask::MASK7 => Oamsk::MASK7,
+        }
+    }
+}
+
+impl Address {
+    pub(super) fn add_mode(&self) -> stm32_metapac::i2c::vals::Addmode {
+        match self {
+            Address::SevenBit(_) => stm32_metapac::i2c::vals::Addmode::BIT7,
+            Address::TenBit(_) => stm32_metapac::i2c::vals::Addmode::BIT10,
+        }
+    }
+}
+
+enum ReceiveResult {
+    DataAvailable,
+    StopReceived,
+    NewStart,
+}
+
+fn debug_print_interrupts(isr: stm32_metapac::i2c::regs::Isr) {
+    if isr.tcr() {
+        trace!("interrupt: tcr");
+    }
+    if isr.tc() {
+        trace!("interrupt: tc");
+    }
+    if isr.addr() {
+        trace!("interrupt: addr");
+    }
+    if isr.stopf() {
+        trace!("interrupt: stopf");
+    }
+    if isr.nackf() {
+        trace!("interrupt: nackf");
+    }
+    if isr.berr() {
+        trace!("interrupt: berr");
+    }
+    if isr.arlo() {
+        trace!("interrupt: arlo");
+    }
+    if isr.ovr() {
+        trace!("interrupt: ovr");
+    }
+}
+
 pub(crate) unsafe fn on_interrupt<T: Instance>() {
     let regs = T::info().regs;
     let isr = regs.isr().read();
 
-    if isr.tcr() || isr.tc() || isr.nackf() || isr.berr() || isr.arlo() || isr.ovr() {
+    if isr.tcr() || isr.tc() || isr.addr() || isr.stopf() || isr.nackf() || isr.berr() || isr.arlo() || isr.ovr() {
+        debug_print_interrupts(isr);
+
         T::state().waker.wake();
     }
+
     critical_section::with(|_| {
         regs.cr1().modify(|w| {
+            w.set_addrie(false);
+            w.set_stopie(false);
             // The flag can only be cleared by writting to nbytes, we won't do that here
             w.set_tcie(false);
             // Error flags are to be read in the routines, so we also don't clear them here
@@ -27,7 +92,7 @@ pub(crate) unsafe fn on_interrupt<T: Instance>() {
     });
 }
 
-impl<'d, M: Mode> I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
     pub(crate) fn init(&mut self, freq: Hertz, _config: Config) {
         self.info.regs.cr1().modify(|reg| {
             reg.set_pe(false);
@@ -55,7 +120,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
     fn master_read(
         info: &'static Info,
-        address: u8,
+        address: Address,
         length: usize,
         stop: Stop,
         reload: bool,
@@ -84,8 +149,8 @@ impl<'d, M: Mode> I2c<'d, M> {
         };
 
         info.regs.cr2().modify(|w| {
-            w.set_sadd((address << 1 | 0) as u16);
-            w.set_add10(i2c::vals::Addmode::BIT7);
+            w.set_sadd(address.addr() << 1);
+            w.set_add10(address.add_mode());
             w.set_dir(i2c::vals::Dir::READ);
             w.set_nbytes(length as u8);
             w.set_start(true);
@@ -98,7 +163,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
     fn master_write(
         info: &'static Info,
-        address: u8,
+        address: Address,
         length: usize,
         stop: Stop,
         reload: bool,
@@ -128,8 +193,8 @@ impl<'d, M: Mode> I2c<'d, M> {
         // START bit can be set even if the bus is BUSY or
         // I2C is in slave mode.
         info.regs.cr2().modify(|w| {
-            w.set_sadd((address << 1 | 0) as u16);
-            w.set_add10(i2c::vals::Addmode::BIT7);
+            w.set_sadd(address.addr() << 1);
+            w.set_add10(address.add_mode());
             w.set_dir(i2c::vals::Dir::WRITE);
             w.set_nbytes(length as u8);
             w.set_start(true);
@@ -140,14 +205,14 @@ impl<'d, M: Mode> I2c<'d, M> {
         Ok(())
     }
 
-    fn master_continue(info: &'static Info, length: usize, reload: bool, timeout: Timeout) -> Result<(), Error> {
+    fn reload(info: &'static Info, length: usize, will_reload: bool, timeout: Timeout) -> Result<(), Error> {
         assert!(length < 256 && length > 0);
 
         while !info.regs.isr().read().tcr() {
             timeout.check()?;
         }
 
-        let reload = if reload {
+        let will_reload = if will_reload {
             i2c::vals::Reload::NOT_COMPLETED
         } else {
             i2c::vals::Reload::COMPLETED
@@ -155,7 +220,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
         info.regs.cr2().modify(|w| {
             w.set_nbytes(length as u8);
-            w.set_reload(reload);
+            w.set_reload(will_reload);
         });
 
         Ok(())
@@ -163,49 +228,132 @@ impl<'d, M: Mode> I2c<'d, M> {
 
     fn flush_txdr(&self) {
         if self.info.regs.isr().read().txis() {
-            self.info.regs.txdr().write(|w| w.set_txdata(0));
+            trace!("Flush TXDATA with zeroes");
+            self.info.regs.txdr().modify(|w| w.set_txdata(0));
         }
         if !self.info.regs.isr().read().txe() {
+            trace!("Flush TXDR");
             self.info.regs.isr().modify(|w| w.set_txe(true))
         }
     }
 
-    fn wait_txe(&self, timeout: Timeout) -> Result<(), Error> {
+    fn error_occurred(&self, isr: &i2c::regs::Isr, timeout: Timeout) -> Result<(), Error> {
+        if isr.nackf() {
+            trace!("NACK triggered.");
+            self.info.regs.icr().modify(|reg| reg.set_nackcf(true));
+            // NACK should be followed by STOP
+            if let Ok(()) = self.wait_stop(timeout) {
+                trace!("Got STOP after NACK, clearing flag.");
+                self.info.regs.icr().modify(|reg| reg.set_stopcf(true));
+            }
+            self.flush_txdr();
+            return Err(Error::Nack);
+        } else if isr.berr() {
+            trace!("BERR triggered.");
+            self.info.regs.icr().modify(|reg| reg.set_berrcf(true));
+            self.flush_txdr();
+            return Err(Error::Bus);
+        } else if isr.arlo() {
+            trace!("ARLO triggered.");
+            self.info.regs.icr().modify(|reg| reg.set_arlocf(true));
+            self.flush_txdr();
+            return Err(Error::Arbitration);
+        } else if isr.ovr() {
+            trace!("OVR triggered.");
+            self.info.regs.icr().modify(|reg| reg.set_ovrcf(true));
+            return Err(Error::Overrun);
+        }
+        return Ok(());
+    }
+
+    fn wait_txis(&self, timeout: Timeout) -> Result<(), Error> {
+        let mut first_loop = true;
+
         loop {
             let isr = self.info.regs.isr().read();
-            if isr.txe() {
+            self.error_occurred(&isr, timeout)?;
+            if isr.txis() {
+                trace!("TXIS");
                 return Ok(());
-            } else if isr.berr() {
-                self.info.regs.icr().write(|reg| reg.set_berrcf(true));
-                return Err(Error::Bus);
-            } else if isr.arlo() {
-                self.info.regs.icr().write(|reg| reg.set_arlocf(true));
-                return Err(Error::Arbitration);
-            } else if isr.nackf() {
-                self.info.regs.icr().write(|reg| reg.set_nackcf(true));
-                self.flush_txdr();
-                return Err(Error::Nack);
             }
 
+            {
+                if first_loop {
+                    trace!("Waiting for TXIS...");
+                    first_loop = false;
+                }
+            }
+            timeout.check()?;
+        }
+    }
+
+    fn wait_stop_or_err(&self, timeout: Timeout) -> Result<(), Error> {
+        loop {
+            let isr = self.info.regs.isr().read();
+            self.error_occurred(&isr, timeout)?;
+            if isr.stopf() {
+                trace!("STOP triggered.");
+                self.info.regs.icr().modify(|reg| reg.set_stopcf(true));
+                return Ok(());
+            }
+            timeout.check()?;
+        }
+    }
+    fn wait_stop(&self, timeout: Timeout) -> Result<(), Error> {
+        loop {
+            let isr = self.info.regs.isr().read();
+            if isr.stopf() {
+                trace!("STOP triggered.");
+                self.info.regs.icr().modify(|reg| reg.set_stopcf(true));
+                return Ok(());
+            }
             timeout.check()?;
         }
     }
 
-    fn wait_rxne(&self, timeout: Timeout) -> Result<(), Error> {
+    fn wait_af(&self, timeout: Timeout) -> Result<(), Error> {
         loop {
             let isr = self.info.regs.isr().read();
-            if isr.rxne() {
+            if isr.nackf() {
+                trace!("AF triggered.");
+                self.info.regs.icr().modify(|reg| reg.set_nackcf(true));
                 return Ok(());
-            } else if isr.berr() {
-                self.info.regs.icr().write(|reg| reg.set_berrcf(true));
-                return Err(Error::Bus);
-            } else if isr.arlo() {
-                self.info.regs.icr().write(|reg| reg.set_arlocf(true));
-                return Err(Error::Arbitration);
-            } else if isr.nackf() {
-                self.info.regs.icr().write(|reg| reg.set_nackcf(true));
-                self.flush_txdr();
-                return Err(Error::Nack);
+            }
+            timeout.check()?;
+        }
+    }
+
+    fn wait_rxne(&self, timeout: Timeout) -> Result<ReceiveResult, Error> {
+        let mut first_loop = true;
+
+        loop {
+            let isr = self.info.regs.isr().read();
+            self.error_occurred(&isr, timeout)?;
+            if isr.stopf() {
+                trace!("STOP when waiting for RXNE.");
+                if self.info.regs.isr().read().rxne() {
+                    trace!("Data received with STOP.");
+                    return Ok(ReceiveResult::DataAvailable);
+                }
+                trace!("STOP triggered without data.");
+                return Ok(ReceiveResult::StopReceived);
+            } else if isr.rxne() {
+                trace!("RXNE.");
+                return Ok(ReceiveResult::DataAvailable);
+            } else if isr.addr() {
+                // Another addr event received, which means START was sent again
+                // which happens when accessing memory registers (common i2c interface design)
+                // e.g. master sends: START, write 1 byte (register index), START, read N bytes (until NACK)
+                // Possible to receive this flag at the same time as rxne, so check rxne first
+                trace!("START when waiting for RXNE. Ending receive loop.");
+                // Return without clearing ADDR so `listen` can catch it
+                return Ok(ReceiveResult::NewStart);
+            }
+            {
+                if first_loop {
+                    trace!("Waiting for RXNE...");
+                    first_loop = false;
+                }
             }
 
             timeout.check()?;
@@ -215,25 +363,21 @@ impl<'d, M: Mode> I2c<'d, M> {
     fn wait_tc(&self, timeout: Timeout) -> Result<(), Error> {
         loop {
             let isr = self.info.regs.isr().read();
+            self.error_occurred(&isr, timeout)?;
             if isr.tc() {
                 return Ok(());
-            } else if isr.berr() {
-                self.info.regs.icr().write(|reg| reg.set_berrcf(true));
-                return Err(Error::Bus);
-            } else if isr.arlo() {
-                self.info.regs.icr().write(|reg| reg.set_arlocf(true));
-                return Err(Error::Arbitration);
-            } else if isr.nackf() {
-                self.info.regs.icr().write(|reg| reg.set_nackcf(true));
-                self.flush_txdr();
-                return Err(Error::Nack);
             }
-
             timeout.check()?;
         }
     }
 
-    fn read_internal(&mut self, address: u8, read: &mut [u8], restart: bool, timeout: Timeout) -> Result<(), Error> {
+    fn read_internal(
+        &mut self,
+        address: Address,
+        read: &mut [u8],
+        restart: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
         let completed_chunks = read.len() / 255;
         let total_chunks = if completed_chunks * 255 == read.len() {
             completed_chunks
@@ -254,7 +398,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
         for (number, chunk) in read.chunks_mut(255).enumerate() {
             if number != 0 {
-                Self::master_continue(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
             }
 
             for byte in chunk {
@@ -267,7 +411,13 @@ impl<'d, M: Mode> I2c<'d, M> {
         Ok(())
     }
 
-    fn write_internal(&mut self, address: u8, write: &[u8], send_stop: bool, timeout: Timeout) -> Result<(), Error> {
+    fn write_internal(
+        &mut self,
+        address: Address,
+        write: &[u8],
+        send_stop: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
         let completed_chunks = write.len() / 255;
         let total_chunks = if completed_chunks * 255 == write.len() {
             completed_chunks
@@ -295,14 +445,14 @@ impl<'d, M: Mode> I2c<'d, M> {
 
         for (number, chunk) in write.chunks(255).enumerate() {
             if number != 0 {
-                Self::master_continue(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
             }
 
             for byte in chunk {
                 // Wait until we are allowed to send data
                 // (START has been ACKed or last byte when
                 // through)
-                if let Err(err) = self.wait_txe(timeout) {
+                if let Err(err) = self.wait_txis(timeout) {
                     if send_stop {
                         self.master_stop();
                     }
@@ -325,20 +475,20 @@ impl<'d, M: Mode> I2c<'d, M> {
 
     /// Blocking read.
     pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Error> {
-        self.read_internal(address, read, false, self.timeout())
+        self.read_internal(address.into(), read, false, self.timeout())
         // Automatic Stop
     }
 
     /// Blocking write.
     pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
-        self.write_internal(address, write, true, self.timeout())
+        self.write_internal(address.into(), write, true, self.timeout())
     }
 
     /// Blocking write, restart, read.
     pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
         let timeout = self.timeout();
-        self.write_internal(address, write, false, timeout)?;
-        self.read_internal(address, read, true, timeout)
+        self.write_internal(address.into(), write, false, timeout)?;
+        self.read_internal(address.into(), read, true, timeout)
         // Automatic Stop
     }
 
@@ -368,7 +518,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
         if let Err(err) = Self::master_write(
             self.info,
-            address,
+            address.into(),
             first_length.min(255),
             Stop::Software,
             (first_length > 255) || (last_slice_index != 0),
@@ -389,7 +539,7 @@ impl<'d, M: Mode> I2c<'d, M> {
             let last_chunk_idx = total_chunks.saturating_sub(1);
 
             if idx != 0 {
-                if let Err(err) = Self::master_continue(
+                if let Err(err) = Self::reload(
                     self.info,
                     slice_len.min(255),
                     (idx != last_slice_index) || (slice_len > 255),
@@ -402,7 +552,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
             for (number, chunk) in slice.chunks(255).enumerate() {
                 if number != 0 {
-                    if let Err(err) = Self::master_continue(
+                    if let Err(err) = Self::reload(
                         self.info,
                         chunk.len(),
                         (number != last_chunk_idx) || (idx != last_slice_index),
@@ -417,7 +567,7 @@ impl<'d, M: Mode> I2c<'d, M> {
                     // Wait until we are allowed to send data
                     // (START has been ACKed or last byte when
                     // through)
-                    if let Err(err) = self.wait_txe(timeout) {
+                    if let Err(err) = self.wait_txis(timeout) {
                         self.master_stop();
                         return Err(err);
                     }
@@ -435,10 +585,10 @@ impl<'d, M: Mode> I2c<'d, M> {
     }
 }
 
-impl<'d> I2c<'d, Async> {
+impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     async fn write_dma_internal(
         &mut self,
-        address: u8,
+        address: Address,
         write: &[u8],
         first_slice: bool,
         last_slice: bool,
@@ -512,7 +662,7 @@ impl<'d> I2c<'d, Async> {
                         timeout,
                     )?;
                 } else {
-                    Self::master_continue(self.info, total_len.min(255), (total_len > 255) || !last_slice, timeout)?;
+                    Self::reload(self.info, total_len.min(255), (total_len > 255) || !last_slice, timeout)?;
                     self.info.regs.cr1().modify(|w| w.set_tcie(true));
                 }
             } else if !(isr.tcr() || isr.tc()) {
@@ -523,7 +673,7 @@ impl<'d> I2c<'d, Async> {
             } else {
                 let last_piece = (remaining_len <= 255) && last_slice;
 
-                if let Err(e) = Self::master_continue(self.info, remaining_len.min(255), !last_piece, timeout) {
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, timeout) {
                     return Poll::Ready(Err(e));
                 }
                 self.info.regs.cr1().modify(|w| w.set_tcie(true));
@@ -551,7 +701,7 @@ impl<'d> I2c<'d, Async> {
 
     async fn read_dma_internal(
         &mut self,
-        address: u8,
+        address: Address,
         buffer: &mut [u8],
         restart: bool,
         timeout: Timeout,
@@ -626,7 +776,7 @@ impl<'d> I2c<'d, Async> {
             } else {
                 let last_piece = remaining_len <= 255;
 
-                if let Err(e) = Self::master_continue(self.info, remaining_len.min(255), !last_piece, timeout) {
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, timeout) {
                     return Poll::Ready(Err(e));
                 }
                 // Return here if we are on last chunk,
@@ -647,7 +797,6 @@ impl<'d> I2c<'d, Async> {
 
         Ok(())
     }
-
     // =========================
     //  Async public API
 
@@ -655,10 +804,10 @@ impl<'d> I2c<'d, Async> {
     pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
         let timeout = self.timeout();
         if write.is_empty() {
-            self.write_internal(address, write, true, timeout)
+            self.write_internal(address.into(), write, true, timeout)
         } else {
             timeout
-                .with(self.write_dma_internal(address, write, true, true, true, timeout))
+                .with(self.write_dma_internal(address.into(), write, true, true, true, timeout))
                 .await
         }
     }
@@ -666,7 +815,7 @@ impl<'d> I2c<'d, Async> {
     /// Write multiple buffers.
     ///
     /// The buffers are concatenated in a single write transaction.
-    pub async fn write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error> {
+    pub async fn write_vectored(&mut self, address: Address, write: &[&[u8]]) -> Result<(), Error> {
         let timeout = self.timeout();
 
         if write.is_empty() {
@@ -693,9 +842,9 @@ impl<'d> I2c<'d, Async> {
         let timeout = self.timeout();
 
         if buffer.is_empty() {
-            self.read_internal(address, buffer, false, timeout)
+            self.read_internal(address.into(), buffer, false, timeout)
         } else {
-            let fut = self.read_dma_internal(address, buffer, false, timeout);
+            let fut = self.read_dma_internal(address.into(), buffer, false, timeout);
             timeout.with(fut).await
         }
     }
@@ -705,16 +854,16 @@ impl<'d> I2c<'d, Async> {
         let timeout = self.timeout();
 
         if write.is_empty() {
-            self.write_internal(address, write, false, timeout)?;
+            self.write_internal(address.into(), write, false, timeout)?;
         } else {
-            let fut = self.write_dma_internal(address, write, true, true, false, timeout);
+            let fut = self.write_dma_internal(address.into(), write, true, true, false, timeout);
             timeout.with(fut).await?;
         }
 
         if read.is_empty() {
-            self.read_internal(address, read, true, timeout)?;
+            self.read_internal(address.into(), read, true, timeout)?;
         } else {
-            let fut = self.read_dma_internal(address, read, true, timeout);
+            let fut = self.read_dma_internal(address.into(), read, true, timeout);
             timeout.with(fut).await?;
         }
 
@@ -733,6 +882,414 @@ impl<'d> I2c<'d, Async> {
     }
 }
 
+impl<'d, M: Mode> I2c<'d, M, Master> {
+    /// Configure the I2C driver for slave operations, allowing for the driver to be used as a slave and a master (multimaster)
+    pub fn into_slave_multimaster(mut self, slave_addr_config: SlaveAddrConfig) -> I2c<'d, M, MultiMaster> {
+        let mut slave = I2c {
+            info: self.info,
+            state: self.state,
+            kernel_clock: self.kernel_clock,
+            tx_dma: self.tx_dma.take(),
+            rx_dma: self.rx_dma.take(),
+            #[cfg(feature = "time")]
+            timeout: self.timeout,
+            _phantom: PhantomData,
+            _phantom2: PhantomData,
+            _drop_guard: self._drop_guard,
+        };
+        slave.init_slave(slave_addr_config);
+        slave
+    }
+}
+
+impl<'d, M: Mode> I2c<'d, M, MultiMaster> {
+    pub(crate) fn init_slave(&mut self, config: SlaveAddrConfig) {
+        self.info.regs.cr1().modify(|reg| {
+            reg.set_pe(false);
+        });
+
+        self.info.regs.cr1().modify(|reg| {
+            reg.set_nostretch(false);
+            reg.set_gcen(config.general_call);
+            reg.set_sbc(true);
+            reg.set_pe(true);
+        });
+
+        self.reconfigure_addresses(config.addr);
+    }
+
+    /// Configure the slave address.
+    pub fn reconfigure_addresses(&mut self, addresses: OwnAddresses) {
+        match addresses {
+            OwnAddresses::OA1(oa1) => self.configure_oa1(oa1),
+            OwnAddresses::OA2(oa2) => self.configure_oa2(oa2),
+            OwnAddresses::Both { oa1, oa2 } => {
+                self.configure_oa1(oa1);
+                self.configure_oa2(oa2);
+            }
+        }
+    }
+
+    fn configure_oa1(&mut self, oa1: Address) {
+        match oa1 {
+            Address::SevenBit(addr) => self.info.regs.oar1().write(|reg| {
+                reg.set_oa1en(false);
+                reg.set_oa1((addr << 1) as u16);
+                reg.set_oa1mode(Addmode::BIT7);
+                reg.set_oa1en(true);
+            }),
+            Address::TenBit(addr) => self.info.regs.oar1().write(|reg| {
+                reg.set_oa1en(false);
+                reg.set_oa1(addr);
+                reg.set_oa1mode(Addmode::BIT10);
+                reg.set_oa1en(true);
+            }),
+        }
+    }
+
+    fn configure_oa2(&mut self, oa2: OA2) {
+        self.info.regs.oar2().write(|reg| {
+            reg.set_oa2en(false);
+            reg.set_oa2msk(oa2.mask.into());
+            reg.set_oa2(oa2.addr << 1);
+            reg.set_oa2en(true);
+        });
+    }
+
+    fn determine_matched_address(&self) -> Result<Address, Error> {
+        let matched = self.info.regs.isr().read().addcode();
+
+        if matched >> 3 == 0b11110 {
+            // is 10-bit address and we need to get the other 8 bits from the rxdr
+            // we do this by doing a blocking read of 1 byte
+            let mut buffer = [0];
+            self.slave_read_internal(&mut buffer, self.timeout())?;
+            Ok(Address::TenBit((matched as u16) << 6 | buffer[0] as u16))
+        } else {
+            Ok(Address::SevenBit(matched))
+        }
+    }
+}
+
+impl<'d, M: Mode> I2c<'d, M, MultiMaster> {
+    /// # Safety
+    /// This function will clear the address flag which will stop the clock stretching.
+    /// This should only be done after the dma transfer has been set up.
+    fn slave_start(info: &'static Info, length: usize, reload: bool) {
+        assert!(length < 256);
+
+        let reload = if reload {
+            i2c::vals::Reload::NOT_COMPLETED
+        } else {
+            i2c::vals::Reload::COMPLETED
+        };
+
+        info.regs.cr2().modify(|w| {
+            w.set_nbytes(length as u8);
+            w.set_reload(reload);
+        });
+
+        // clear the address flag, will stop the clock stretching.
+        // this should only be done after the dma transfer has been set up.
+        info.regs.icr().modify(|reg| reg.set_addrcf(true));
+        trace!("ADDRCF cleared (ADDR interrupt enabled, clock stretching ended)");
+    }
+
+    // A blocking read operation
+    fn slave_read_internal(&self, read: &mut [u8], timeout: Timeout) -> Result<usize, Error> {
+        let completed_chunks = read.len() / 255;
+        let total_chunks = if completed_chunks * 255 == read.len() {
+            completed_chunks
+        } else {
+            completed_chunks + 1
+        };
+        let last_chunk_idx = total_chunks.saturating_sub(1);
+        let total_len = read.len();
+        let mut remaining_len = total_len;
+
+        for (number, chunk) in read.chunks_mut(255).enumerate() {
+            trace!(
+                "--- Slave RX transmission start - chunk: {}, expected (max) size: {}",
+                number,
+                chunk.len()
+            );
+            if number == 0 {
+                Self::slave_start(self.info, chunk.len(), number != last_chunk_idx);
+            } else {
+                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+            }
+
+            let mut index = 0;
+
+            for byte in chunk {
+                // Wait until we have received something
+                match self.wait_rxne(timeout) {
+                    Ok(ReceiveResult::StopReceived) | Ok(ReceiveResult::NewStart) => {
+                        trace!("--- Slave RX transmission end (early)");
+                        return Ok(total_len - remaining_len); // Return N bytes read
+                    }
+                    Ok(ReceiveResult::DataAvailable) => {
+                        *byte = self.info.regs.rxdr().read().rxdata();
+                        remaining_len = remaining_len.saturating_sub(1);
+                        {
+                            trace!("Slave RX data {}: {:#04x}", index, byte);
+                            index = index + 1;
+                        }
+                    }
+                    Err(e) => return Err(e),
+                };
+            }
+        }
+        self.wait_stop_or_err(timeout)?;
+
+        trace!("--- Slave RX transmission end");
+        Ok(total_len - remaining_len) // Return N bytes read
+    }
+
+    // A blocking write operation
+    fn slave_write_internal(&mut self, write: &[u8], timeout: Timeout) -> Result<(), Error> {
+        let completed_chunks = write.len() / 255;
+        let total_chunks = if completed_chunks * 255 == write.len() {
+            completed_chunks
+        } else {
+            completed_chunks + 1
+        };
+        let last_chunk_idx = total_chunks.saturating_sub(1);
+
+        for (number, chunk) in write.chunks(255).enumerate() {
+            trace!(
+                "--- Slave TX transmission start - chunk: {}, size: {}",
+                number,
+                chunk.len()
+            );
+            if number == 0 {
+                Self::slave_start(self.info, chunk.len(), number != last_chunk_idx);
+            } else {
+                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+            }
+
+            let mut index = 0;
+
+            for byte in chunk {
+                // Wait until we are allowed to send data
+                // (START has been ACKed or last byte when through)
+                self.wait_txis(timeout)?;
+
+                {
+                    trace!("Slave TX data {}: {:#04x}", index, byte);
+                    index = index + 1;
+                }
+                self.info.regs.txdr().write(|w| w.set_txdata(*byte));
+            }
+        }
+        self.wait_af(timeout)?;
+        self.flush_txdr();
+        self.wait_stop_or_err(timeout)?;
+
+        trace!("--- Slave TX transmission end");
+        Ok(())
+    }
+
+    /// Listen for incoming I2C messages.
+    ///
+    /// The listen method is an asynchronous method but it does not require DMA to be asynchronous.
+    pub async fn listen(&mut self) -> Result<SlaveCommand, Error> {
+        let state = self.state;
+        self.info.regs.cr1().modify(|reg| {
+            reg.set_addrie(true);
+            trace!("Enable ADDRIE");
+        });
+
+        poll_fn(|cx| {
+            state.waker.register(cx.waker());
+            let isr = self.info.regs.isr().read();
+            if !isr.addr() {
+                Poll::Pending
+            } else {
+                trace!("ADDR triggered (address match)");
+                // we do not clear the address flag here as it will be cleared by the dma read/write
+                // if we clear it here the clock stretching will stop and the master will read in data before the slave is ready to send it
+                match isr.dir() {
+                    i2c::vals::Dir::WRITE => {
+                        trace!("DIR: write");
+                        Poll::Ready(Ok(SlaveCommand {
+                            kind: SlaveCommandKind::Write,
+                            address: self.determine_matched_address()?,
+                        }))
+                    }
+                    i2c::vals::Dir::READ => {
+                        trace!("DIR: read");
+                        Poll::Ready(Ok(SlaveCommand {
+                            kind: SlaveCommandKind::Read,
+                            address: self.determine_matched_address()?,
+                        }))
+                    }
+                }
+            }
+        })
+        .await
+    }
+
+    /// Respond to a write command.
+    ///
+    /// Returns total number of bytes received.
+    pub fn blocking_respond_to_write(&self, read: &mut [u8]) -> Result<usize, Error> {
+        let timeout = self.timeout();
+        self.slave_read_internal(read, timeout)
+    }
+
+    /// Respond to a read command.
+    pub fn blocking_respond_to_read(&mut self, write: &[u8]) -> Result<(), Error> {
+        let timeout = self.timeout();
+        self.slave_write_internal(write, timeout)
+    }
+}
+
+impl<'d> I2c<'d, Async, MultiMaster> {
+    /// Respond to a write command.
+    ///
+    /// Returns the total number of bytes received.
+    pub async fn respond_to_write(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
+        let timeout = self.timeout();
+        timeout.with(self.read_dma_internal_slave(buffer, timeout)).await
+    }
+
+    /// Respond to a read request from an I2C master.
+    pub async fn respond_to_read(&mut self, write: &[u8]) -> Result<SendStatus, Error> {
+        let timeout = self.timeout();
+        timeout.with(self.write_dma_internal_slave(write, timeout)).await
+    }
+
+    // for data reception in slave mode
+    //
+    // returns the total number of bytes received
+    async fn read_dma_internal_slave(&mut self, buffer: &mut [u8], timeout: Timeout) -> Result<usize, Error> {
+        let total_len = buffer.len();
+        let mut remaining_len = total_len;
+
+        let regs = self.info.regs;
+
+        let dma_transfer = unsafe {
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(true);
+                w.set_stopie(true);
+                w.set_tcie(true);
+            });
+            let src = regs.rxdr().as_ptr() as *mut u8;
+
+            self.rx_dma.as_mut().unwrap().read(src, buffer, Default::default())
+        };
+
+        let state = self.state;
+
+        let on_drop = OnDrop::new(|| {
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(false);
+                w.set_stopie(false);
+                w.set_tcie(false);
+            });
+        });
+
+        let total_received = poll_fn(|cx| {
+            state.waker.register(cx.waker());
+
+            let isr = regs.isr().read();
+
+            if remaining_len == total_len {
+                Self::slave_start(self.info, total_len.min(255), total_len > 255);
+                remaining_len = remaining_len.saturating_sub(255);
+                Poll::Pending
+            } else if isr.tcr() {
+                let is_last_slice = remaining_len <= 255;
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !is_last_slice, timeout) {
+                    return Poll::Ready(Err(e));
+                }
+                remaining_len = remaining_len.saturating_sub(255);
+                regs.cr1().modify(|w| w.set_tcie(true));
+                Poll::Pending
+            } else if isr.stopf() {
+                regs.icr().write(|reg| reg.set_stopcf(true));
+                let poll = Poll::Ready(Ok(total_len - remaining_len));
+                poll
+            } else {
+                Poll::Pending
+            }
+        })
+        .await?;
+
+        dma_transfer.await;
+
+        drop(on_drop);
+
+        Ok(total_received)
+    }
+
+    async fn write_dma_internal_slave(&mut self, buffer: &[u8], timeout: Timeout) -> Result<SendStatus, Error> {
+        let total_len = buffer.len();
+        let mut remaining_len = total_len;
+
+        let mut dma_transfer = unsafe {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_txdmaen(true);
+                w.set_stopie(true);
+                w.set_tcie(true);
+            });
+            let dst = regs.txdr().as_ptr() as *mut u8;
+
+            self.tx_dma.as_mut().unwrap().write(buffer, dst, Default::default())
+        };
+
+        let on_drop = OnDrop::new(|| {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_txdmaen(false);
+                w.set_stopie(false);
+                w.set_tcie(false);
+            })
+        });
+
+        let state = self.state;
+
+        let size = poll_fn(|cx| {
+            state.waker.register(cx.waker());
+
+            let isr = self.info.regs.isr().read();
+
+            if remaining_len == total_len {
+                Self::slave_start(self.info, total_len.min(255), total_len > 255);
+                remaining_len = remaining_len.saturating_sub(255);
+                Poll::Pending
+            } else if isr.tcr() {
+                let is_last_slice = remaining_len <= 255;
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !is_last_slice, timeout) {
+                    return Poll::Ready(Err(e));
+                }
+                remaining_len = remaining_len.saturating_sub(255);
+                self.info.regs.cr1().modify(|w| w.set_tcie(true));
+                Poll::Pending
+            } else if isr.stopf() {
+                self.info.regs.icr().write(|reg| reg.set_stopcf(true));
+                if remaining_len > 0 {
+                    dma_transfer.request_stop();
+                    Poll::Ready(Ok(SendStatus::LeftoverBytes(remaining_len as usize)))
+                } else {
+                    Poll::Ready(Ok(SendStatus::Done))
+                }
+            } else {
+                Poll::Pending
+            }
+        })
+        .await?;
+
+        dma_transfer.await;
+
+        drop(on_drop);
+
+        Ok(size)
+    }
+}
+
 /// I2C Stop Configuration
 ///
 /// Peripheral options for generating the STOP condition
@@ -857,7 +1414,7 @@ impl Timings {
     }
 }
 
-impl<'d, M: Mode> SetConfig for I2c<'d, M> {
+impl<'d, M: Mode> SetConfig for I2c<'d, M, Master> {
     type Config = Hertz;
     type ConfigError = ();
     fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
@@ -882,3 +1439,21 @@ impl<'d, M: Mode> SetConfig for I2c<'d, M> {
         Ok(())
     }
 }
+
+impl<'d, M: Mode> SetConfig for I2c<'d, M, MultiMaster> {
+    type Config = (Hertz, SlaveAddrConfig);
+    type ConfigError = ();
+    fn set_config(&mut self, (config, addr_config): &Self::Config) -> Result<(), ()> {
+        let timings = Timings::new(self.kernel_clock, *config);
+        self.info.regs.timingr().write(|reg| {
+            reg.set_presc(timings.prescale);
+            reg.set_scll(timings.scll);
+            reg.set_sclh(timings.sclh);
+            reg.set_sdadel(timings.sdadel);
+            reg.set_scldel(timings.scldel);
+        });
+        self.init_slave(*addr_config);
+
+        Ok(())
+    }
+}
diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
index 20cd20dca..670d8332c 100644
--- a/embassy-stm32/src/ipcc.rs
+++ b/embassy-stm32/src/ipcc.rs
@@ -104,9 +104,6 @@ impl Ipcc {
         rcc::enable_and_reset::<IPCC>();
         IPCC::set_cpu2(true);
 
-        // set RF wake-up clock = LSE
-        crate::pac::RCC.csr().modify(|w| w.set_rfwkpsel(0b01));
-
         let regs = IPCC::regs();
 
         regs.cpu(0).cr().modify(|w| {
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 973acc9bb..c7a33ed72 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -178,7 +178,7 @@ pub use crate::_generated::interrupt;
 macro_rules! bind_interrupts {
     ($(#[$outer:meta])* $vis:vis struct $name:ident {
         $(
-            $(#[$inner:meta])*
+            $(#[doc = $doc:literal])*
             $(#[cfg($cond_irq:meta)])?
             $irq:ident => $(
                 $(#[cfg($cond_handler:meta)])?
@@ -194,13 +194,15 @@ macro_rules! bind_interrupts {
             #[allow(non_snake_case)]
             #[no_mangle]
             $(#[cfg($cond_irq)])?
-            $(#[$inner])*
+            $(#[doc = $doc])*
             unsafe extern "C" fn $irq() {
-                $(
-                    $(#[cfg($cond_handler)])?
-                    <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
+                unsafe {
+                    $(
+                        $(#[cfg($cond_handler)])?
+                        <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
 
-                )*
+                    )*
+                }
             }
 
             $(#[cfg($cond_irq)])?
@@ -242,12 +244,12 @@ pub struct Config {
     #[cfg(dbgmcu)]
     pub enable_debug_during_sleep: bool,
 
-    /// On low-power boards (eg. `stm32l4`, `stm32l5` and `stm32u5`),
+    /// On low-power boards (eg. `stm32l4`, `stm32l5`, `stm32wba` and `stm32u5`),
     /// some GPIO pins are powered by an auxiliary, independent power supply (`VDDIO2`),
     /// which needs to be enabled before these pins can be used.
     ///
     /// May increase power consumption. Defaults to true.
-    #[cfg(any(stm32l4, stm32l5, stm32u5))]
+    #[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba))]
     pub enable_independent_io_supply: bool,
 
     /// On the U5 series all analog peripherals are powered by a separate supply.
@@ -291,7 +293,7 @@ impl Default for Config {
             rcc: Default::default(),
             #[cfg(dbgmcu)]
             enable_debug_during_sleep: true,
-            #[cfg(any(stm32l4, stm32l5, stm32u5))]
+            #[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba))]
             enable_independent_io_supply: true,
             #[cfg(stm32u5)]
             enable_independent_analog_supply: true,
@@ -540,6 +542,13 @@ fn init_hw(config: Config) -> Peripherals {
                 w.set_iosv(config.enable_independent_io_supply);
             });
         }
+        #[cfg(stm32wba)]
+        {
+            use crate::pac::pwr::vals;
+            crate::pac::PWR.svmcr().modify(|w| {
+                w.set_io2sv(vals::Io2sv::B_0X1);
+            });
+        }
         #[cfg(stm32u5)]
         {
             crate::pac::PWR.svmcr().modify(|w| {
diff --git a/embassy-stm32/src/low_power.rs b/embassy-stm32/src/low_power.rs
index 7734365f1..d13df5a6b 100644
--- a/embassy-stm32/src/low_power.rs
+++ b/embassy-stm32/src/low_power.rs
@@ -124,15 +124,18 @@ pub enum StopMode {
     Stop2,
 }
 
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32u0))]
 use stm32_metapac::pwr::vals::Lpms;
 
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32u0))]
 impl Into<Lpms> for StopMode {
     fn into(self) -> Lpms {
         match self {
             StopMode::Stop1 => Lpms::STOP1,
+            #[cfg(not(stm32wba))]
             StopMode::Stop2 => Lpms::STOP2,
+            #[cfg(stm32wba)]
+            StopMode::Stop2 => Lpms::STOP1, // TODO: WBA has no STOP2?
         }
     }
 }
@@ -198,7 +201,7 @@ impl Executor {
 
     #[allow(unused_variables)]
     fn configure_stop(&mut self, stop_mode: StopMode) {
-        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
+        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0, stm32wba))]
         crate::pac::PWR.cr1().modify(|m| m.set_lpms(stop_mode.into()));
         #[cfg(stm32h5)]
         crate::pac::PWR.pmcr().modify(|v| {
diff --git a/embassy-stm32/src/lptim/timer/mod.rs b/embassy-stm32/src/lptim/timer/mod.rs
index a629be62b..648da5940 100644
--- a/embassy-stm32/src/lptim/timer/mod.rs
+++ b/embassy-stm32/src/lptim/timer/mod.rs
@@ -115,6 +115,31 @@ impl<'d, T: Instance> Timer<'d, T> {
             .ccmr(0)
             .modify(|w| w.set_ccsel(channel.index(), direction.into()));
     }
+
+    /// Enable the timer interrupt.
+    pub fn enable_interrupt(&self) {
+        T::regs().dier().modify(|w| w.set_arrmie(true));
+    }
+
+    /// Disable the timer interrupt.
+    pub fn disable_interrupt(&self) {
+        T::regs().dier().modify(|w| w.set_arrmie(false));
+    }
+
+    /// Check if the timer interrupt is enabled.
+    pub fn is_interrupt_enabled(&self) -> bool {
+        T::regs().dier().read().arrmie()
+    }
+
+    /// Check if the timer interrupt is pending.
+    pub fn is_interrupt_pending(&self) -> bool {
+        T::regs().isr().read().arrm()
+    }
+
+    /// Clear the timer interrupt.
+    pub fn clear_interrupt(&self) {
+        T::regs().icr().write(|w| w.set_arrmcf(true));
+    }
 }
 
 #[cfg(not(any(lptim_v2a, lptim_v2b)))]
@@ -128,4 +153,29 @@ impl<'d, T: Instance> Timer<'d, T> {
     pub fn get_compare_value(&self) -> u16 {
         T::regs().cmp().read().cmp()
     }
+
+    /// Enable the timer interrupt.
+    pub fn enable_interrupt(&self) {
+        T::regs().ier().modify(|w| w.set_arrmie(true));
+    }
+
+    /// Disable the timer interrupt.
+    pub fn disable_interrupt(&self) {
+        T::regs().ier().modify(|w| w.set_arrmie(false));
+    }
+
+    /// Check if the timer interrupt is enabled.
+    pub fn is_interrupt_enabled(&self) -> bool {
+        T::regs().ier().read().arrmie()
+    }
+
+    /// Check if the timer interrupt is pending.
+    pub fn is_interrupt_pending(&self) -> bool {
+        T::regs().isr().read().arrm()
+    }
+
+    /// Clear the timer interrupt.
+    pub fn clear_interrupt(&self) {
+        T::regs().icr().write(|w| w.set_arrmcf(true));
+    }
 }
diff --git a/embassy-stm32/src/macros.rs b/embassy-stm32/src/macros.rs
index 7526bb180..3a0b490ba 100644
--- a/embassy-stm32/src/macros.rs
+++ b/embassy-stm32/src/macros.rs
@@ -81,17 +81,28 @@ macro_rules! dma_trait {
             /// Note: in some chips, ST calls this the "channel", and calls channels "streams".
             /// `embassy-stm32` always uses the "channel" and "request number" names.
             fn request(&self) -> crate::dma::Request;
+            #[doc = "Remap the DMA channel"]
+            fn remap(&self);
         }
     };
 }
 
 #[allow(unused)]
 macro_rules! dma_trait_impl {
-    (crate::$mod:ident::$trait:ident$(<$mode:ident>)?, $instance:ident, $channel:ident, $request:expr) => {
+    (crate::$mod:ident::$trait:ident$(<$mode:ident>)?, $instance:ident, $channel:ident, $request:expr, $remap:expr) => {
         impl crate::$mod::$trait<crate::peripherals::$instance $(, crate::$mod::$mode)?> for crate::peripherals::$channel {
             fn request(&self) -> crate::dma::Request {
                 $request
             }
+
+            fn remap(&self) {
+                critical_section::with(|_| {
+                    #[allow(unused_unsafe)]
+                    unsafe {
+                        $remap;
+                    }
+                });
+            }
         }
     };
 }
@@ -111,6 +122,7 @@ macro_rules! new_dma_nonopt {
 macro_rules! new_dma {
     ($name:ident) => {{
         let dma = $name;
+        dma.remap();
         let request = dma.request();
         Some(crate::dma::ChannelAndRequest {
             channel: dma.into(),
diff --git a/embassy-stm32/src/opamp.rs b/embassy-stm32/src/opamp.rs
index 2eb2e61c1..e36719ef3 100644
--- a/embassy-stm32/src/opamp.rs
+++ b/embassy-stm32/src/opamp.rs
@@ -4,10 +4,12 @@
 use embassy_hal_internal::PeripheralType;
 
 use crate::pac::opamp::vals::*;
+#[cfg(not(any(stm32g4, stm32f3)))]
+use crate::rcc::RccInfo;
 use crate::Peri;
 
 /// Performs a busy-wait delay for a specified number of microseconds.
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 fn blocking_delay_ms(ms: u32) {
     #[cfg(feature = "time")]
     embassy_time::block_for(embassy_time::Duration::from_millis(ms as u64));
@@ -23,13 +25,13 @@ pub enum OpAmpGain {
     Mul4,
     Mul8,
     Mul16,
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     Mul32,
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     Mul64,
 }
 
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 enum OpAmpDifferentialPair {
     P,
     N,
@@ -53,7 +55,7 @@ pub struct OpAmpOutput<'d, T: Instance> {
 /// OpAmp internal outputs, wired directly to ADC inputs.
 ///
 /// This struct can be used as an ADC input.
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 pub struct OpAmpInternalOutput<'d, T: Instance> {
     _inner: &'d OpAmp<'d, T>,
 }
@@ -67,8 +69,10 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// Create a new driver instance.
     ///
     /// Does not enable the opamp, but does set the speed mode on some families.
-    pub fn new(opamp: Peri<'d, T>, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self {
-        #[cfg(opamp_g4)]
+    pub fn new(opamp: Peri<'d, T>, #[cfg(opamp_v5)] speed: OpAmpSpeed) -> Self {
+        #[cfg(not(any(stm32g4, stm32f3)))]
+        T::info().rcc.enable_and_reset();
+        #[cfg(opamp_v5)]
         T::regs().csr().modify(|w| {
             w.set_opahsm(speed == OpAmpSpeed::HighSpeed);
         });
@@ -94,15 +98,15 @@ impl<'d, T: Instance> OpAmp<'d, T> {
         in_pin.set_as_analog();
         out_pin.set_as_analog();
 
-        #[cfg(opamp_g4)]
+        #[cfg(opamp_v5)]
         let vm_sel = VmSel::OUTPUT;
-        #[cfg(not(opamp_g4))]
+        #[cfg(not(opamp_v5))]
         let vm_sel = VmSel::from_bits(0b11);
 
         T::regs().csr().modify(|w| {
             w.set_vp_sel(VpSel::from_bits(in_pin.channel()));
             w.set_vm_sel(vm_sel);
-            #[cfg(opamp_g4)]
+            #[cfg(opamp_v5)]
             w.set_opaintoen(false);
             w.set_opampen(true);
         });
@@ -129,12 +133,12 @@ impl<'d, T: Instance> OpAmp<'d, T> {
         in_pin.set_as_analog();
         out_pin.set_as_analog();
 
-        #[cfg(opamp_g4)]
+        #[cfg(opamp_v5)]
         let vm_sel = VmSel::PGA;
-        #[cfg(not(opamp_g4))]
+        #[cfg(not(opamp_v5))]
         let vm_sel = VmSel::from_bits(0b10);
 
-        #[cfg(opamp_g4)]
+        #[cfg(opamp_v5)]
         let pga_gain = match gain {
             OpAmpGain::Mul2 => PgaGain::GAIN2,
             OpAmpGain::Mul4 => PgaGain::GAIN4,
@@ -143,7 +147,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
             OpAmpGain::Mul32 => PgaGain::GAIN32,
             OpAmpGain::Mul64 => PgaGain::GAIN64,
         };
-        #[cfg(not(opamp_g4))]
+        #[cfg(not(opamp_v5))]
         let pga_gain = PgaGain::from_bits(match gain {
             OpAmpGain::Mul2 => 0b00,
             OpAmpGain::Mul4 => 0b01,
@@ -155,7 +159,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
             w.set_vp_sel(VpSel::from_bits(in_pin.channel()));
             w.set_vm_sel(vm_sel);
             w.set_pga_gain(pga_gain);
-            #[cfg(opamp_g4)]
+            #[cfg(opamp_v5)]
             w.set_opaintoen(false);
             w.set_opampen(true);
         });
@@ -170,7 +174,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// preventing it being used elsewhere. The `OpAmpOutput` can then be
     /// directly used as an ADC input. The opamp will be disabled when the
     /// [`OpAmpOutput`] is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn buffer_dac(&mut self, out_pin: Peri<'_, impl OutputPin<T> + crate::gpio::Pin>) -> OpAmpOutput<'_, T> {
         out_pin.set_as_analog();
 
@@ -194,7 +198,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     ///
     /// The returned `OpAmpInternalOutput` struct may be used as an ADC input.
     /// The opamp output will be disabled when it is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn buffer_int(
         &mut self,
         pin: Peri<'_, impl NonInvertingPin<T> + crate::gpio::Pin>,
@@ -204,7 +208,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
         T::regs().csr().modify(|w| {
             w.set_vp_sel(VpSel::from_bits(pin.channel()));
             w.set_vm_sel(VmSel::OUTPUT);
-            #[cfg(opamp_g4)]
+            #[cfg(opamp_v5)]
             w.set_opaintoen(true);
             w.set_opampen(true);
         });
@@ -220,7 +224,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     ///
     /// The returned `OpAmpInternalOutput` struct may be used as an ADC input.
     /// The opamp output will be disabled when it is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn pga_int(
         &mut self,
         pin: Peri<'_, impl NonInvertingPin<T> + crate::gpio::Pin>,
@@ -257,7 +261,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     ///
     /// The returned `OpAmpInternalOutput` struct may be used as an ADC
     /// input. The opamp output will be disabled when it is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn standalone_dac_int(
         &mut self,
         m_pin: Peri<'_, impl InvertingPin<T> + crate::gpio::Pin>,
@@ -285,7 +289,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// The output pin is held within the returned [`OpAmpOutput`] struct,
     /// preventing it being used elsewhere. The opamp will be disabled when
     /// the [`OpAmpOutput`] is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn standalone_dac_ext(
         &mut self,
         m_pin: Peri<'_, impl InvertingPin<T> + crate::gpio::Pin>,
@@ -315,7 +319,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// The output pin is held within the returned [`OpAmpOutput`] struct,
     /// preventing it being used elsewhere. The opamp will be disabled when
     /// the [`OpAmpOutput`] is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn standalone_ext(
         &mut self,
         p_pin: Peri<'d, impl NonInvertingPin<T> + crate::gpio::Pin>,
@@ -346,7 +350,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     ///
     /// The returned `OpAmpOutput` struct may be used as an ADC
     /// input. The opamp output will be disabled when it is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn standalone_int(
         &mut self,
         p_pin: Peri<'d, impl NonInvertingPin<T> + crate::gpio::Pin>,
@@ -374,7 +378,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// while for high-speed mode, only the P differential pair is calibrated.
     ///
     /// Calibrating a differential pair requires waiting 12ms in the worst case (binary method).
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn calibrate(&mut self) {
         T::regs().csr().modify(|w| {
             w.set_opampen(true);
@@ -403,7 +407,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// The calibration range is from 0 to 31.
     ///
     /// The result is stored in the OPAMP_CSR register.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     fn calibrate_differential_pair(&mut self, pair: OpAmpDifferentialPair) {
         let mut low = 0;
         let mut high = 31;
@@ -452,6 +456,13 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     }
 }
 
+#[cfg(not(any(stm32g4, stm32f3)))]
+impl<'d, T: Instance> Drop for OpAmp<'d, T> {
+    fn drop(&mut self) {
+        T::info().rcc.disable();
+    }
+}
+
 impl<'d, T: Instance> Drop for OpAmpOutput<'d, T> {
     fn drop(&mut self) {
         T::regs().csr().modify(|w| {
@@ -460,7 +471,7 @@ impl<'d, T: Instance> Drop for OpAmpOutput<'d, T> {
     }
 }
 
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 impl<'d, T: Instance> Drop for OpAmpInternalOutput<'d, T> {
     fn drop(&mut self) {
         T::regs().csr().modify(|w| {
@@ -469,7 +480,14 @@ impl<'d, T: Instance> Drop for OpAmpInternalOutput<'d, T> {
     }
 }
 
+#[cfg(not(any(stm32g4, stm32f3)))]
+pub(crate) struct Info {
+    rcc: RccInfo,
+}
+
 pub(crate) trait SealedInstance {
+    #[cfg(not(any(stm32g4, stm32f3)))]
+    fn info() -> &'static Info;
     fn regs() -> crate::pac::opamp::Opamp;
 }
 
@@ -545,7 +563,7 @@ foreach_peripheral!(
     };
 );
 
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 macro_rules! impl_opamp_internal_output {
     ($inst:ident, $adc:ident, $ch:expr) => {
         foreach_adc!(
@@ -567,7 +585,7 @@ macro_rules! impl_opamp_internal_output {
     };
 }
 
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 foreach_peripheral!(
     (opamp, OPAMP1) => {
         impl_opamp_internal_output!(OPAMP1, ADC1, 13);
@@ -600,6 +618,15 @@ foreach_peripheral!(
 foreach_peripheral! {
     (opamp, $inst:ident) => {
         impl SealedInstance for crate::peripherals::$inst {
+            // G4 and F3 use SYSCFGEN, which is always enabled
+            #[cfg(not(any(stm32g4, stm32f3)))]
+            fn info() -> &'static Info {
+                use crate::rcc::SealedRccPeripheral;
+                static INFO: Info = Info {
+                    rcc: crate::peripherals::$inst::RCC_INFO,
+                };
+                &INFO
+            }
             fn regs() -> crate::pac::opamp::Opamp {
                 crate::pac::$inst
             }
diff --git a/embassy-stm32/src/qspi/enums.rs b/embassy-stm32/src/qspi/enums.rs
index 9ec4c1b43..fa5e36d06 100644
--- a/embassy-stm32/src/qspi/enums.rs
+++ b/embassy-stm32/src/qspi/enums.rs
@@ -331,3 +331,19 @@ impl From<DummyCycles> for u8 {
         }
     }
 }
+
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum SampleShifting {
+    None,
+    HalfCycle,
+}
+
+impl From<SampleShifting> for bool {
+    fn from(value: SampleShifting) -> Self {
+        match value {
+            SampleShifting::None => false,
+            SampleShifting::HalfCycle => true,
+        }
+    }
+}
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index 0df057c53..1e20d7cd3 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -58,6 +58,8 @@ pub struct Config {
     pub fifo_threshold: FIFOThresholdLevel,
     /// Minimum number of cycles that chip select must be high between issued commands
     pub cs_high_time: ChipSelectHighTime,
+    /// Shift sampling point of input data (none, or half-cycle)
+    pub sample_shifting: SampleShifting,
 }
 
 impl Default for Config {
@@ -68,6 +70,7 @@ impl Default for Config {
             prescaler: 128,
             fifo_threshold: FIFOThresholdLevel::_17Bytes,
             cs_high_time: ChipSelectHighTime::_5Cycle,
+            sample_shifting: SampleShifting::None,
         }
     }
 }
@@ -120,7 +123,7 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
         T::REGS.cr().modify(|w| {
             w.set_en(true);
             //w.set_tcen(false);
-            w.set_sshift(false);
+            w.set_sshift(config.sample_shifting.into());
             w.set_fthres(config.fifo_threshold.into());
             w.set_prescaler(config.prescaler);
             w.set_fsel(fsel.into());
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index cac2a9149..c2295bab6 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -190,6 +190,8 @@ pub(crate) unsafe fn init(config: Config) {
         // TODO
         lsi: None,
         lse: None,
+        #[cfg(crs)]
+        hsi48: None,
     );
 
     RCC.ccipr()
diff --git a/embassy-stm32/src/rcc/hsi48.rs b/embassy-stm32/src/rcc/hsi48.rs
index 3ea5c96c9..49be4af5e 100644
--- a/embassy-stm32/src/rcc/hsi48.rs
+++ b/embassy-stm32/src/rcc/hsi48.rs
@@ -39,9 +39,9 @@ pub(crate) fn init_hsi48(config: Hsi48Config) -> Hertz {
     });
 
     // Enable HSI48
-    #[cfg(not(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32h7rs, stm32u5, stm32wba, stm32f0)))]
+    #[cfg(not(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32h7rs, stm32u5, stm32wba, stm32f0, stm32c071)))]
     let r = RCC.crrcr();
-    #[cfg(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32h7rs, stm32u5, stm32wba))]
+    #[cfg(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32h7rs, stm32u5, stm32wba, stm32c071))]
     let r = RCC.cr();
     #[cfg(any(stm32f0))]
     let r = RCC.cr2();
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index c50e071fb..96e628b1a 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -74,7 +74,7 @@ macro_rules! impl_peri {
     };
 }
 
-#[cfg(any(rcc_c0, rcc_g0, rcc_u0))]
+#[cfg(any(rcc_c0, rcc_c0v2, rcc_g0x0, rcc_g0x1, rcc_u0))]
 #[allow(unused_imports)]
 use self::{McoSource as Mco1Source, McoSource as Mco2Source};
 
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 3733fed56..c41f81816 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -95,6 +95,15 @@ pub(crate) unsafe fn get_freqs() -> &'static Clocks {
     unwrap!(CLOCK_FREQS_PTR.load(core::sync::atomic::Ordering::SeqCst).as_ref()).assume_init_ref()
 }
 
+/// Get the current clock configuration of the chip.
+pub fn clocks<'a>(_rcc: &'a crate::Peri<'a, crate::peripherals::RCC>) -> &'a Clocks {
+    // Safety: the existence of a `Peri<RCC>` means that `rcc::init()`
+    // has already been called, so `CLOCK_FREQS` must be initialized.
+    // The clocks could be modified again by `reinit()`, but reinit
+    // (for this reason) requires an exclusive reference to `Peri<RCC>`.
+    unsafe { get_freqs() }
+}
+
 pub(crate) trait SealedRccPeripheral {
     fn frequency() -> Hertz;
     #[allow(dead_code)]
@@ -381,7 +390,7 @@ pub fn disable<T: RccPeripheral>() {
 ///
 /// This should only be called after `init`.
 #[cfg(not(feature = "_dual-core"))]
-pub fn reinit(config: Config) {
+pub fn reinit<'a>(config: Config, _rcc: &'a mut crate::Peri<'a, crate::peripherals::RCC>) {
     critical_section::with(|cs| init_rcc(cs, config))
 }
 
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 97eb2eb6d..06895a99a 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -5,7 +5,7 @@ pub use crate::pac::rcc::vals::{
     Hpre as AHBPrescaler, Msirange, Msirange as MSIRange, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
     Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
 };
-use crate::pac::rcc::vals::{Hseext, Msirgsel, Pllmboost, Pllrge};
+use crate::pac::rcc::vals::{Hseext, Msipllfast, Msipllsel, Msirgsel, Pllmboost, Pllrge};
 #[cfg(all(peri_usb_otg_hs))]
 pub use crate::pac::{syscfg::vals::Usbrefcksel, SYSCFG};
 use crate::pac::{FLASH, PWR, RCC};
@@ -64,6 +64,46 @@ pub struct Pll {
     pub divr: Option<PllDiv>,
 }
 
+#[derive(Clone, Copy, PartialEq)]
+pub enum MsiAutoCalibration {
+    /// MSI auto-calibration is disabled
+    Disabled,
+    /// MSIS is given priority for auto-calibration
+    MSIS,
+    /// MSIK is given priority for auto-calibration
+    MSIK,
+    /// MSIS with fast mode (always on)
+    MsisFast,
+    /// MSIK with fast mode (always on)
+    MsikFast,
+}
+
+impl MsiAutoCalibration {
+    const fn default() -> Self {
+        MsiAutoCalibration::Disabled
+    }
+
+    fn base_mode(&self) -> Self {
+        match self {
+            MsiAutoCalibration::Disabled => MsiAutoCalibration::Disabled,
+            MsiAutoCalibration::MSIS => MsiAutoCalibration::MSIS,
+            MsiAutoCalibration::MSIK => MsiAutoCalibration::MSIK,
+            MsiAutoCalibration::MsisFast => MsiAutoCalibration::MSIS,
+            MsiAutoCalibration::MsikFast => MsiAutoCalibration::MSIK,
+        }
+    }
+
+    fn is_fast(&self) -> bool {
+        matches!(self, MsiAutoCalibration::MsisFast | MsiAutoCalibration::MsikFast)
+    }
+}
+
+impl Default for MsiAutoCalibration {
+    fn default() -> Self {
+        Self::default()
+    }
+}
+
 #[derive(Clone, Copy)]
 pub struct Config {
     // base clock sources
@@ -95,6 +135,7 @@ pub struct Config {
 
     /// Per-peripheral kernel clock selection muxes
     pub mux: super::mux::ClockMux,
+    pub auto_calibration: MsiAutoCalibration,
 }
 
 impl Config {
@@ -116,6 +157,7 @@ impl Config {
             voltage_range: VoltageScale::RANGE1,
             ls: crate::rcc::LsConfig::new(),
             mux: super::mux::ClockMux::default(),
+            auto_calibration: MsiAutoCalibration::default(),
         }
     }
 }
@@ -131,7 +173,42 @@ pub(crate) unsafe fn init(config: Config) {
     PWR.vosr().modify(|w| w.set_vos(config.voltage_range));
     while !PWR.vosr().read().vosrdy() {}
 
-    let msis = config.msis.map(|range| {
+    let lse_calibration_freq = if config.auto_calibration != MsiAutoCalibration::Disabled {
+        // LSE must be configured and peripherals clocked for MSI auto-calibration
+        let lse_config = config
+            .ls
+            .lse
+            .clone()
+            .expect("LSE must be configured for MSI auto-calibration");
+        assert!(lse_config.peripherals_clocked);
+
+        // Expect less than +/- 5% deviation for LSE frequency
+        if (31_100..=34_400).contains(&lse_config.frequency.0) {
+            // Check that the calibration is applied to an active clock
+            match (
+                config.auto_calibration.base_mode(),
+                config.msis.is_some(),
+                config.msik.is_some(),
+            ) {
+                (MsiAutoCalibration::MSIS, true, _) => {
+                    // MSIS is active and using LSE for auto-calibration
+                    Some(lse_config.frequency)
+                }
+                (MsiAutoCalibration::MSIK, _, true) => {
+                    // MSIK is active and using LSE for auto-calibration
+                    Some(lse_config.frequency)
+                }
+                // improper configuration
+                _ => panic!("MSIx auto-calibration is enabled for a source that has not been configured."),
+            }
+        } else {
+            panic!("LSE frequency more than 5% off from 32.768 kHz, cannot use for MSI auto-calibration");
+        }
+    } else {
+        None
+    };
+
+    let mut msis = config.msis.map(|range| {
         // Check MSI output per RM0456 § 11.4.10
         match config.voltage_range {
             VoltageScale::RANGE4 => {
@@ -156,11 +233,21 @@ pub(crate) unsafe fn init(config: Config) {
             w.set_msipllen(false);
             w.set_msison(true);
         });
+        let msis = if let (Some(freq), MsiAutoCalibration::MSIS) =
+            (lse_calibration_freq, config.auto_calibration.base_mode())
+        {
+            // Enable the MSIS auto-calibration feature
+            RCC.cr().modify(|w| w.set_msipllsel(Msipllsel::MSIS));
+            RCC.cr().modify(|w| w.set_msipllen(true));
+            calculate_calibrated_msi_frequency(range, freq)
+        } else {
+            msirange_to_hertz(range)
+        };
         while !RCC.cr().read().msisrdy() {}
-        msirange_to_hertz(range)
+        msis
     });
 
-    let msik = config.msik.map(|range| {
+    let mut msik = config.msik.map(|range| {
         // Check MSI output per RM0456 § 11.4.10
         match config.voltage_range {
             VoltageScale::RANGE4 => {
@@ -184,10 +271,44 @@ pub(crate) unsafe fn init(config: Config) {
         RCC.cr().modify(|w| {
             w.set_msikon(true);
         });
+        let msik = if let (Some(freq), MsiAutoCalibration::MSIK) =
+            (lse_calibration_freq, config.auto_calibration.base_mode())
+        {
+            // Enable the MSIK auto-calibration feature
+            RCC.cr().modify(|w| w.set_msipllsel(Msipllsel::MSIK));
+            RCC.cr().modify(|w| w.set_msipllen(true));
+            calculate_calibrated_msi_frequency(range, freq)
+        } else {
+            msirange_to_hertz(range)
+        };
         while !RCC.cr().read().msikrdy() {}
-        msirange_to_hertz(range)
+        msik
     });
 
+    if let Some(lse_freq) = lse_calibration_freq {
+        // If both MSIS and MSIK are enabled, we need to check if they are using the same internal source.
+        if let (Some(msis_range), Some(msik_range)) = (config.msis, config.msik) {
+            if (msis_range as u8 >> 2) == (msik_range as u8 >> 2) {
+                // Clock source is shared, both will be auto calibrated, recalculate other frequency
+                match config.auto_calibration.base_mode() {
+                    MsiAutoCalibration::MSIS => {
+                        msik = Some(calculate_calibrated_msi_frequency(msik_range, lse_freq));
+                    }
+                    MsiAutoCalibration::MSIK => {
+                        msis = Some(calculate_calibrated_msi_frequency(msis_range, lse_freq));
+                    }
+                    _ => {}
+                }
+            }
+        }
+        // Check if Fast mode should be used
+        if config.auto_calibration.is_fast() {
+            RCC.cr().modify(|w| {
+                w.set_msipllfast(Msipllfast::FAST);
+            });
+        }
+    }
+
     let hsi = config.hsi.then(|| {
         RCC.cr().modify(|w| w.set_hsion(true));
         while !RCC.cr().read().hsirdy() {}
@@ -514,3 +635,37 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput, voltag
 
     PllOutput { p, q, r }
 }
+
+/// Fraction structure for MSI auto-calibration
+/// Represents the multiplier as numerator/denominator that LSE frequency is multiplied by
+#[derive(Debug, Clone, Copy)]
+struct MsiFraction {
+    numerator: u32,
+    denominator: u32,
+}
+
+impl MsiFraction {
+    const fn new(numerator: u32, denominator: u32) -> Self {
+        Self { numerator, denominator }
+    }
+
+    /// Calculate the calibrated frequency given an LSE frequency
+    fn calculate_frequency(&self, lse_freq: Hertz) -> Hertz {
+        Hertz(lse_freq.0 * self.numerator / self.denominator)
+    }
+}
+
+fn get_msi_calibration_fraction(range: Msirange) -> MsiFraction {
+    // Exploiting the MSIx internals to make calculations compact
+    let denominator = (range as u32 & 0x03) + 1;
+    // Base multipliers are deduced from Table 82: MSI oscillator characteristics in data sheet
+    let numerator = [1465, 122, 94, 12][range as usize >> 2];
+
+    MsiFraction::new(numerator, denominator)
+}
+
+/// Calculate the calibrated MSI frequency for a given range and LSE frequency
+fn calculate_calibrated_msi_frequency(range: Msirange, lse_freq: Hertz) -> Hertz {
+    let fraction = get_msi_calibration_fraction(range);
+    fraction.calculate_frequency(lse_freq)
+}
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index b9fc4e423..b494997b3 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -176,6 +176,7 @@ pub(crate) unsafe fn init(config: Config) {
         // TODO
         lse: None,
         lsi: None,
+        pll1_p: None,
         pll1_q: None,
     );
 }
diff --git a/embassy-stm32/src/rtc/low_power.rs b/embassy-stm32/src/rtc/low_power.rs
index cd075f3de..78ccd3e6c 100644
--- a/embassy-stm32/src/rtc/low_power.rs
+++ b/embassy-stm32/src/rtc/low_power.rs
@@ -66,7 +66,7 @@ pub(crate) enum WakeupPrescaler {
 }
 
 #[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0
+    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba
 ))]
 impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
     fn from(val: WakeupPrescaler) -> Self {
@@ -82,7 +82,7 @@ impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
 }
 
 #[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0
+    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba
 ))]
 impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
     fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
@@ -227,7 +227,7 @@ impl Rtc {
         <RTC as crate::rtc::SealedInstance>::WakeupInterrupt::unpend();
         unsafe { <RTC as crate::rtc::SealedInstance>::WakeupInterrupt::enable() };
 
-        #[cfg(not(any(stm32u5, stm32u0)))]
+        #[cfg(not(any(stm32u5, stm32u0, stm32wba)))]
         {
             use crate::pac::EXTI;
             EXTI.rtsr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
@@ -247,5 +247,11 @@ impl Rtc {
             RCC.srdamr().modify(|w| w.set_rtcapbamen(true));
             RCC.apb3smenr().modify(|w| w.set_rtcapbsmen(true));
         }
+        #[cfg(stm32wba)]
+        {
+            use crate::pac::RCC;
+            // RCC.srdamr().modify(|w| w.set_rtcapbamen(true));
+            RCC.apb7smenr().modify(|w| w.set_rtcapbsmen(true));
+        }
     }
 }
diff --git a/embassy-stm32/src/rtc/mod.rs b/embassy-stm32/src/rtc/mod.rs
index 49f423f37..449f3008a 100644
--- a/embassy-stm32/src/rtc/mod.rs
+++ b/embassy-stm32/src/rtc/mod.rs
@@ -25,7 +25,7 @@ use crate::time::Hertz;
     ),
     path = "v2.rs"
 )]
-#[cfg_attr(any(rtc_v3, rtc_v3u5, rtc_v3l5, rtc_v3h7rs), path = "v3.rs")]
+#[cfg_attr(any(rtc_v3, rtc_v3u5, rtc_v3l5, rtc_v3h7rs, rtc_v3c0), path = "v3.rs")]
 mod _version;
 #[allow(unused_imports)]
 pub use _version::*;
@@ -296,7 +296,7 @@ trait SealedInstance {
     const BACKUP_REGISTER_COUNT: usize;
 
     #[cfg(feature = "low-power")]
-    #[cfg(not(any(stm32u5, stm32u0)))]
+    #[cfg(not(any(stm32wba, stm32u5, stm32u0)))]
     const EXTI_WAKEUP_LINE: usize;
 
     #[cfg(feature = "low-power")]
diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs
index 39aa6c5cb..d0b52049e 100644
--- a/embassy-stm32/src/rtc/v3.rs
+++ b/embassy-stm32/src/rtc/v3.rs
@@ -146,7 +146,7 @@ impl SealedInstance for crate::peripherals::RTC {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC_WKUP;
         } else if #[cfg(any(stm32g0, stm32u0))] {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC_TAMP;
-        } else if #[cfg(any(stm32l5, stm32h5, stm32u5))] {
+        } else if #[cfg(any(stm32l5, stm32h5, stm32u5, stm32wba))] {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC;
         }
     );
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index 6a02aae70..6e5d735d7 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -32,25 +32,48 @@ pub struct InterruptHandler<T: Instance> {
 }
 
 impl<T: Instance> InterruptHandler<T> {
-    fn data_interrupts(enable: bool) {
+    fn enable_interrupts() {
         let regs = T::regs();
         regs.maskr().write(|w| {
-            w.set_dcrcfailie(enable);
-            w.set_dtimeoutie(enable);
-            w.set_dataendie(enable);
+            w.set_dcrcfailie(true);
+            w.set_dtimeoutie(true);
+            w.set_dataendie(true);
+            w.set_dbckendie(true);
 
             #[cfg(sdmmc_v1)]
-            w.set_stbiterre(enable);
+            w.set_stbiterre(true);
             #[cfg(sdmmc_v2)]
-            w.set_dabortie(enable);
+            w.set_dabortie(true);
         });
     }
 }
 
 impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
     unsafe fn on_interrupt() {
-        Self::data_interrupts(false);
         T::state().wake();
+        let status = T::regs().star().read();
+        T::regs().maskr().modify(|w| {
+            if status.dcrcfail() {
+                w.set_dcrcfailie(false)
+            }
+            if status.dtimeout() {
+                w.set_dtimeoutie(false)
+            }
+            if status.dataend() {
+                w.set_dataendie(false)
+            }
+            if status.dbckend() {
+                w.set_dbckendie(false)
+            }
+            #[cfg(sdmmc_v1)]
+            if status.stbiterr() {
+                w.set_stbiterre(false)
+            }
+            #[cfg(sdmmc_v2)]
+            if status.dabort() {
+                w.set_dabortie(false)
+            }
+        });
     }
 }
 
@@ -225,8 +248,7 @@ fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u8, Hertz), Error> {
         return Ok((true, 0, ker_ck));
     }
 
-    // `ker_ck / sdmmc_ck` rounded up
-    let clk_div = match (ker_ck.0 + sdmmc_ck - 1) / sdmmc_ck {
+    let clk_div = match ker_ck.0.div_ceil(sdmmc_ck) {
         0 | 1 => Ok(0),
         x @ 2..=258 => Ok((x - 2) as u8),
         _ => Err(Error::BadClock),
@@ -244,12 +266,11 @@ fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u8, Hertz), Error> {
 /// `clk_div` is the divisor register value and `clk_f` is the resulting new clock frequency.
 #[cfg(sdmmc_v2)]
 fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u16, Hertz), Error> {
-    // `ker_ck / sdmmc_ck` rounded up
-    match (ker_ck.0 + sdmmc_ck - 1) / sdmmc_ck {
+    match ker_ck.0.div_ceil(sdmmc_ck) {
         0 | 1 => Ok((false, 0, ker_ck)),
         x @ 2..=2046 => {
             // SDMMC_CK frequency = SDMMCCLK / [CLKDIV * 2]
-            let clk_div = ((x + 1) / 2) as u16;
+            let clk_div = x.div_ceil(2) as u16;
             let clk = Hertz(ker_ck.0 / (clk_div as u32 * 2));
 
             Ok((false, clk_div, clk))
@@ -751,7 +772,6 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         Self::wait_idle();
         Self::clear_interrupt_flags();
 
-        regs.dtimer().write(|w| w.set_datatime(config.data_transfer_timeout));
         regs.dlenr().write(|w| w.set_datalength(length_bytes));
 
         #[cfg(sdmmc_v1)]
@@ -789,8 +809,6 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         Self::wait_idle();
         Self::clear_interrupt_flags();
 
-        regs.dtimer()
-            .write(|w| w.set_datatime(self.config.data_transfer_timeout));
         regs.dlenr().write(|w| w.set_datalength(length_bytes));
 
         #[cfg(sdmmc_v1)]
@@ -1007,14 +1025,14 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             // Wait for the abort
             while Self::data_active() {}
         }
-        InterruptHandler::<T>::data_interrupts(false);
+        regs.maskr().write(|_| ()); // disable irqs
         Self::clear_interrupt_flags();
         Self::stop_datapath();
     }
 
     /// Wait for a previously started datapath transfer to complete from an interrupt.
     #[inline]
-    async fn complete_datapath_transfer() -> Result<(), Error> {
+    async fn complete_datapath_transfer(block: bool) -> Result<(), Error> {
         let regs = T::regs();
 
         let res = poll_fn(|cx| {
@@ -1034,7 +1052,11 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             if status.stbiterr() {
                 return Poll::Ready(Err(Error::StBitErr));
             }
-            if status.dataend() {
+            let done = match block {
+                true => status.dbckend(),
+                false => status.dataend(),
+            };
+            if done {
                 return Poll::Ready(Ok(()));
             }
             Poll::Pending
@@ -1072,10 +1094,10 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             512,
             9,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
         Self::cmd(common_cmd::read_single_block(address), true)?;
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         if res.is_ok() {
             on_drop.defuse();
@@ -1105,7 +1127,6 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         };
         Self::cmd(common_cmd::set_block_length(512), false)?; // CMD16
 
-        let regs = T::regs();
         let on_drop = OnDrop::new(|| Self::on_drop());
 
         let transfer = Self::prepare_datapath_read(
@@ -1116,30 +1137,11 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             512 * blocks.len() as u32,
             9,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
 
         Self::cmd(common_cmd::read_multiple_blocks(address), true)?;
 
-        let res = poll_fn(|cx| {
-            T::state().register(cx.waker());
-            let status = regs.star().read();
-
-            if status.dcrcfail() {
-                return Poll::Ready(Err(Error::Crc));
-            }
-            if status.dtimeout() {
-                return Poll::Ready(Err(Error::Timeout));
-            }
-            #[cfg(sdmmc_v1)]
-            if status.stbiterr() {
-                return Poll::Ready(Err(Error::StBitErr));
-            }
-            if status.dataend() {
-                return Poll::Ready(Ok(()));
-            }
-            Poll::Pending
-        })
-        .await;
+        let res = Self::complete_datapath_transfer(false).await;
 
         Self::cmd(common_cmd::stop_transmission(), false)?; // CMD12
         Self::clear_interrupt_flags();
@@ -1174,12 +1176,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         Self::cmd(common_cmd::write_single_block(address), true)?;
 
         let transfer = self.prepare_datapath_write(buffer, 512, 9);
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
 
         #[cfg(sdmmc_v2)]
         Self::cmd(common_cmd::write_single_block(address), true)?;
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         match res {
             Ok(_) => {
@@ -1230,7 +1232,6 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
         let block_count = blocks.len();
 
-        let regs = T::regs();
         let on_drop = OnDrop::new(|| Self::on_drop());
 
         #[cfg(sdmmc_v1)]
@@ -1238,36 +1239,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
         // Setup write command
         let transfer = self.prepare_datapath_write(buffer, 512 * block_count as u32, 9);
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
 
         #[cfg(sdmmc_v2)]
         Self::cmd(common_cmd::write_multiple_blocks(address), true)?; // CMD25
 
-        let res = poll_fn(|cx| {
-            T::state().register(cx.waker());
-
-            let status = regs.star().read();
-
-            if status.dcrcfail() {
-                return Poll::Ready(Err(Error::Crc));
-            }
-            if status.dtimeout() {
-                return Poll::Ready(Err(Error::Timeout));
-            }
-            if status.txunderr() {
-                return Poll::Ready(Err(Error::Underrun));
-            }
-            #[cfg(sdmmc_v1)]
-            if status.stbiterr() {
-                return Poll::Ready(Err(Error::StBitErr));
-            }
-            if status.dataend() {
-                return Poll::Ready(Ok(()));
-            }
-
-            Poll::Pending
-        })
-        .await;
+        let res = Self::complete_datapath_transfer(false).await;
 
         Self::cmd(common_cmd::stop_transmission(), false)?; // CMD12
         Self::clear_interrupt_flags();
@@ -1349,6 +1326,8 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             #[cfg(sdmmc_v1)]
             w.set_bypass(_bypass);
         });
+        regs.dtimer()
+            .write(|w| w.set_datatime(self.config.data_transfer_timeout));
 
         regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::On as u8));
         Self::cmd(common_cmd::idle(), false)?;
@@ -1600,10 +1579,10 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             64,
             6,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
         Self::cmd(sd_cmd::cmd6(set_function), true)?; // CMD6
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         // Host is allowed to use the new functions at least 8
         // clocks after the end of the switch command
@@ -1660,10 +1639,10 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             8,
             3,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
         Self::cmd(sd_cmd::send_scr(), true)?;
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         if res.is_ok() {
             on_drop.defuse();
@@ -1706,10 +1685,10 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             64,
             6,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
         Self::cmd(sd_cmd::sd_status(), true)?;
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         if res.is_ok() {
             on_drop.defuse();
@@ -1756,10 +1735,10 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             512,
             9,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
         Self::cmd(emmc_cmd::send_ext_csd(), true)?;
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         if res.is_ok() {
             on_drop.defuse();
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 9e2ba093a..c8d83f07e 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -843,7 +843,7 @@ impl<'d> Spi<'d, Async> {
 
         set_rxdmaen(self.info.regs, true);
 
-        let rx_src = self.info.regs.rx_ptr();
+        let rx_src = self.info.regs.rx_ptr::<W>();
         let rx_f = unsafe { self.rx_dma.as_mut().unwrap().read_raw(rx_src, read, Default::default()) };
 
         let tx_dst: *mut W = self.info.regs.tx_ptr();
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 8eec6c0c7..b00cc18ad 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -5,14 +5,12 @@ use core::marker::PhantomData;
 use stm32_metapac::timer::vals::Ckd;
 
 use super::low_level::{CountingMode, OutputPolarity, Timer};
-use super::simple_pwm::{Ch1, Ch2, Ch3, Ch4, PwmPin};
-use super::{
-    AdvancedInstance4Channel, Channel, Channel1ComplementaryPin, Channel2ComplementaryPin, Channel3ComplementaryPin,
-    Channel4ComplementaryPin,
-};
+use super::simple_pwm::PwmPin;
+use super::{AdvancedInstance4Channel, Ch1, Ch2, Ch3, Ch4, Channel, TimerComplementaryPin};
 use crate::gpio::{AnyPin, OutputType};
 use crate::time::Hertz;
 use crate::timer::low_level::OutputCompareMode;
+use crate::timer::TimerChannel;
 use crate::Peri;
 
 /// Complementary PWM pin wrapper.
@@ -23,32 +21,23 @@ pub struct ComplementaryPwmPin<'d, T, C> {
     phantom: PhantomData<(T, C)>,
 }
 
-macro_rules! complementary_channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: AdvancedInstance4Channel> ComplementaryPwmPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " complementary PWM pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, output_type: OutputType) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        crate::gpio::AfType::output(output_type, crate::gpio::Speed::VeryHigh),
-                    );
-                });
-                ComplementaryPwmPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: AdvancedInstance4Channel, C: TimerChannel> ComplementaryPwmPin<'d, T, C> {
+    /// Create a new  complementary PWM pin instance.
+    pub fn new(pin: Peri<'d, impl TimerComplementaryPin<T, C>>, output_type: OutputType) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            pin.set_as_af(
+                pin.af_num(),
+                crate::gpio::AfType::output(output_type, crate::gpio::Speed::VeryHigh),
+            );
+        });
+        ComplementaryPwmPin {
+            _pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
+    }
 }
 
-complementary_channel_impl!(new_ch1, Ch1, Channel1ComplementaryPin);
-complementary_channel_impl!(new_ch2, Ch2, Channel2ComplementaryPin);
-complementary_channel_impl!(new_ch3, Ch3, Channel3ComplementaryPin);
-complementary_channel_impl!(new_ch4, Ch4, Channel4ComplementaryPin);
-
 /// PWM driver with support for standard and complementary outputs.
 pub struct ComplementaryPwm<'d, T: AdvancedInstance4Channel> {
     inner: Timer<'d, T>,
@@ -88,6 +77,7 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
                 this.inner.set_output_compare_mode(channel, OutputCompareMode::PwmMode1);
                 this.inner.set_output_compare_preload(channel, true);
             });
+        this.inner.set_autoreload_preload(true);
 
         this
     }
@@ -121,7 +111,11 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
     pub fn get_max_duty(&self) -> u16 {
-        self.inner.get_max_compare_value() as u16 + 1
+        if self.inner.get_counting_mode().is_center_aligned() {
+            self.inner.get_max_compare_value() as u16
+        } else {
+            self.inner.get_max_compare_value() as u16 + 1
+        }
     }
 
     /// Set the duty for a given channel.
@@ -171,7 +165,11 @@ impl<'d, T: AdvancedInstance4Channel> embedded_hal_02::Pwm for ComplementaryPwm<
     }
 
     fn get_max_duty(&self) -> Self::Duty {
-        self.inner.get_max_compare_value() as u16 + 1
+        if self.inner.get_counting_mode().is_center_aligned() {
+            self.inner.get_max_compare_value() as u16
+        } else {
+            self.inner.get_max_compare_value() as u16 + 1
+        }
     }
 
     fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index ec8b1ddf1..dda33e7f1 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -6,14 +6,12 @@ use core::pin::Pin;
 use core::task::{Context, Poll};
 
 use super::low_level::{CountingMode, FilterValue, InputCaptureMode, InputTISelection, Timer};
-use super::{
-    CaptureCompareInterruptHandler, Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin,
-    GeneralInstance4Channel,
-};
+use super::{CaptureCompareInterruptHandler, Channel, GeneralInstance4Channel, TimerPin};
 pub use super::{Ch1, Ch2, Ch3, Ch4};
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::time::Hertz;
+use crate::timer::TimerChannel;
 use crate::Peri;
 
 /// Capture pin wrapper.
@@ -23,27 +21,17 @@ pub struct CapturePin<'d, T, C> {
     _pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
-
-macro_rules! channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> CapturePin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " capture pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, pull: Pull) -> Self {
-                pin.set_as_af(pin.af_num(), AfType::input(pull));
-                CapturePin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: GeneralInstance4Channel, C: TimerChannel> CapturePin<'d, T, C> {
+    /// Create a new capture pin instance.
+    pub fn new(pin: Peri<'d, impl TimerPin<T, C>>, pull: Pull) -> Self {
+        pin.set_as_af(pin.af_num(), AfType::input(pull));
+        CapturePin {
+            _pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
+    }
 }
 
-channel_impl!(new_ch1, Ch1, Channel1Pin);
-channel_impl!(new_ch2, Ch2, Channel2Pin);
-channel_impl!(new_ch3, Ch3, Channel3Pin);
-channel_impl!(new_ch4, Ch4, Channel4Pin);
-
 /// Input capture driver.
 pub struct InputCapture<'d, T: GeneralInstance4Channel> {
     inner: Timer<'d, T>,
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index b29382fc8..7062f5f4c 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -51,6 +51,80 @@ pub enum Ch3 {}
 /// Channel 4 marker type.
 pub enum Ch4 {}
 
+/// Timer channel trait.
+#[allow(private_bounds)]
+pub trait TimerChannel: SealedTimerChannel {
+    /// The runtime channel.
+    const CHANNEL: Channel;
+}
+
+trait SealedTimerChannel {}
+
+impl TimerChannel for Ch1 {
+    const CHANNEL: Channel = Channel::Ch1;
+}
+
+impl TimerChannel for Ch2 {
+    const CHANNEL: Channel = Channel::Ch2;
+}
+
+impl TimerChannel for Ch3 {
+    const CHANNEL: Channel = Channel::Ch3;
+}
+
+impl TimerChannel for Ch4 {
+    const CHANNEL: Channel = Channel::Ch4;
+}
+
+impl SealedTimerChannel for Ch1 {}
+impl SealedTimerChannel for Ch2 {}
+impl SealedTimerChannel for Ch3 {}
+impl SealedTimerChannel for Ch4 {}
+
+/// Timer break input.
+#[derive(Clone, Copy)]
+pub enum BkIn {
+    /// Break input 1.
+    BkIn1,
+    /// Break input 2.
+    BkIn2,
+}
+
+impl BkIn {
+    /// Get the channel index (0..3)
+    pub fn index(&self) -> usize {
+        match self {
+            BkIn::BkIn1 => 0,
+            BkIn::BkIn2 => 1,
+        }
+    }
+}
+
+/// Break input 1 marker type.
+pub enum BkIn1 {}
+/// Break input 2 marker type.
+pub enum BkIn2 {}
+
+/// Timer channel trait.
+#[allow(private_bounds)]
+pub trait BreakInput: SealedBreakInput {
+    /// The runtim timer channel.
+    const INPUT: BkIn;
+}
+
+trait SealedBreakInput {}
+
+impl BreakInput for BkIn1 {
+    const INPUT: BkIn = BkIn::BkIn1;
+}
+
+impl BreakInput for BkIn2 {
+    const INPUT: BkIn = BkIn::BkIn2;
+}
+
+impl SealedBreakInput for BkIn1 {}
+impl SealedBreakInput for BkIn2 {}
+
 /// Amount of bits of a timer.
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -149,33 +223,20 @@ pub trait AdvancedInstance2Channel: BasicInstance + GeneralInstance2Channel + Ad
 /// Advanced 16-bit timer with 4 channels instance.
 pub trait AdvancedInstance4Channel: AdvancedInstance2Channel + GeneralInstance4Channel {}
 
-pin_trait!(Channel1Pin, GeneralInstance4Channel);
-pin_trait!(Channel2Pin, GeneralInstance4Channel);
-pin_trait!(Channel3Pin, GeneralInstance4Channel);
-pin_trait!(Channel4Pin, GeneralInstance4Channel);
+pin_trait!(TimerPin, GeneralInstance4Channel, TimerChannel);
 pin_trait!(ExternalTriggerPin, GeneralInstance4Channel);
 
-pin_trait!(Channel1ComplementaryPin, AdvancedInstance4Channel);
-pin_trait!(Channel2ComplementaryPin, AdvancedInstance4Channel);
-pin_trait!(Channel3ComplementaryPin, AdvancedInstance4Channel);
-pin_trait!(Channel4ComplementaryPin, AdvancedInstance4Channel);
-
-pin_trait!(BreakInputPin, AdvancedInstance4Channel);
-pin_trait!(BreakInput2Pin, AdvancedInstance4Channel);
+pin_trait!(TimerComplementaryPin, AdvancedInstance4Channel, TimerChannel);
 
-pin_trait!(BreakInputComparator1Pin, AdvancedInstance4Channel);
-pin_trait!(BreakInputComparator2Pin, AdvancedInstance4Channel);
+pin_trait!(BreakInputPin, AdvancedInstance4Channel, BreakInput);
 
-pin_trait!(BreakInput2Comparator1Pin, AdvancedInstance4Channel);
-pin_trait!(BreakInput2Comparator2Pin, AdvancedInstance4Channel);
+pin_trait!(BreakInputComparator1Pin, AdvancedInstance4Channel, BreakInput);
+pin_trait!(BreakInputComparator2Pin, AdvancedInstance4Channel, BreakInput);
 
 // Update Event trigger DMA for every timer
 dma_trait!(UpDma, BasicInstance);
 
-dma_trait!(Ch1Dma, GeneralInstance4Channel);
-dma_trait!(Ch2Dma, GeneralInstance4Channel);
-dma_trait!(Ch3Dma, GeneralInstance4Channel);
-dma_trait!(Ch4Dma, GeneralInstance4Channel);
+dma_trait!(Dma, GeneralInstance4Channel, TimerChannel);
 
 #[allow(unused)]
 macro_rules! impl_core_timer {
diff --git a/embassy-stm32/src/timer/one_pulse.rs b/embassy-stm32/src/timer/one_pulse.rs
index 933165ef9..498d9c082 100644
--- a/embassy-stm32/src/timer/one_pulse.rs
+++ b/embassy-stm32/src/timer/one_pulse.rs
@@ -7,11 +7,9 @@ use core::pin::Pin;
 use core::task::{Context, Poll};
 
 use super::low_level::{
-    CountingMode, FilterValue, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource,
-};
-use super::{
-    CaptureCompareInterruptHandler, Channel, Channel1Pin, Channel2Pin, ExternalTriggerPin, GeneralInstance4Channel,
+    CountingMode, FilterValue, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource as Ts,
 };
+use super::{CaptureCompareInterruptHandler, Channel, ExternalTriggerPin, GeneralInstance4Channel, TimerPin};
 pub use super::{Ch1, Ch2};
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
@@ -48,24 +46,78 @@ pub struct TriggerPin<'d, T, C> {
     phantom: PhantomData<(T, C)>,
 }
 
-macro_rules! channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> TriggerPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " trigger pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, pull: Pull) -> Self {
-                pin.set_as_af(pin.af_num(), AfType::input(pull));
-                TriggerPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
-        }
-    };
+trait SealedTriggerSource {}
+
+/// Marker trait for a trigger source.
+#[expect(private_bounds)]
+pub trait TriggerSource: SealedTriggerSource {}
+
+impl TriggerSource for Ch1 {}
+impl TriggerSource for Ch2 {}
+impl TriggerSource for Ext {}
+
+impl SealedTriggerSource for Ch1 {}
+impl SealedTriggerSource for Ch2 {}
+impl SealedTriggerSource for Ext {}
+
+trait SealedTimerTriggerPin<T, S>: crate::gpio::Pin {}
+
+/// Marker trait for a trigger pin.
+#[expect(private_bounds)]
+// TODO: find better naming scheme than prefixing all pin traits with "Timer".
+// The trait name cannot conflict with the corresponding type's name.
+// Applies to other timer submodules as well.
+pub trait TimerTriggerPin<T, S>: SealedTimerTriggerPin<T, S> {
+    /// Get the AF number needed to use this pin as a trigger source.
+    fn af_num(&self) -> u8;
+}
+
+impl<T, P, C> TimerTriggerPin<T, C> for P
+where
+    T: GeneralInstance4Channel,
+    P: TimerPin<T, C>,
+    C: super::TimerChannel + TriggerSource,
+{
+    fn af_num(&self) -> u8 {
+        TimerPin::af_num(self)
+    }
+}
+
+impl<T, P> TimerTriggerPin<T, Ext> for P
+where
+    T: GeneralInstance4Channel,
+    P: ExternalTriggerPin<T>,
+{
+    fn af_num(&self) -> u8 {
+        ExternalTriggerPin::af_num(self)
+    }
+}
+
+impl<T, P, C> SealedTimerTriggerPin<T, C> for P
+where
+    T: GeneralInstance4Channel,
+    P: TimerPin<T, C>,
+    C: super::TimerChannel + TriggerSource,
+{
 }
 
-channel_impl!(new_ch1, Ch1, Channel1Pin);
-channel_impl!(new_ch2, Ch2, Channel2Pin);
-channel_impl!(new_ext, Ext, ExternalTriggerPin);
+impl<T, P> SealedTimerTriggerPin<T, Ext> for P
+where
+    T: GeneralInstance4Channel,
+    P: ExternalTriggerPin<T>,
+{
+}
+
+impl<'d, T: GeneralInstance4Channel, C: TriggerSource> TriggerPin<'d, T, C> {
+    /// "Create a new Ch1 trigger pin instance.
+    pub fn new(pin: Peri<'d, impl TimerTriggerPin<T, C>>, pull: Pull) -> Self {
+        pin.set_as_af(pin.af_num(), AfType::input(pull));
+        TriggerPin {
+            _pin: pin.into(),
+            phantom: PhantomData,
+        }
+    }
+}
 
 /// One pulse driver.
 ///
@@ -89,7 +141,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
-        this.inner.set_trigger_source(TriggerSource::TI1F_ED);
+        this.inner.set_trigger_source(Ts::TI1F_ED);
         this.inner
             .set_input_ti_selection(Channel::Ch1, InputTISelection::Normal);
         this.inner
@@ -114,7 +166,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
-        this.inner.set_trigger_source(TriggerSource::TI1FP1);
+        this.inner.set_trigger_source(Ts::TI1FP1);
         this.inner
             .set_input_ti_selection(Channel::Ch1, InputTISelection::Normal);
         this.inner
@@ -131,7 +183,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     /// as an output.
     pub fn new_ch2(
         tim: Peri<'d, T>,
-        _pin: TriggerPin<'d, T, Ch1>,
+        _pin: TriggerPin<'d, T, Ch2>,
         _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
         freq: Hertz,
         pulse_end: u32,
@@ -140,7 +192,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
-        this.inner.set_trigger_source(TriggerSource::TI2FP2);
+        this.inner.set_trigger_source(Ts::TI2FP2);
         this.inner
             .set_input_ti_selection(Channel::Ch2, InputTISelection::Normal);
         this.inner
@@ -172,7 +224,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
             // No filtering
             r.set_etf(FilterValue::NO_FILTER);
         });
-        this.inner.set_trigger_source(TriggerSource::ETRF);
+        this.inner.set_trigger_source(Ts::ETRF);
         this.new_inner(freq, pulse_end, counting_mode);
 
         this
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index 98b798634..1e55f2919 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -1,12 +1,16 @@
 //! PWM Input driver.
 
 use super::low_level::{CountingMode, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource};
-use super::{Channel, Channel1Pin, Channel2Pin, GeneralInstance4Channel};
+use super::{Ch1, Ch2, Channel, GeneralInstance4Channel, TimerPin};
 use crate::gpio::{AfType, Pull};
 use crate::time::Hertz;
 use crate::Peri;
 
 /// PWM Input driver.
+///
+/// Only works with CH1 or CH2
+/// Note: Not all timer peripherals are supported
+/// Double check your chips reference manual
 pub struct PwmInput<'d, T: GeneralInstance4Channel> {
     channel: Channel,
     inner: Timer<'d, T>,
@@ -14,14 +18,14 @@ pub struct PwmInput<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
     /// Create a new PWM input driver.
-    pub fn new(tim: Peri<'d, T>, pin: Peri<'d, impl Channel1Pin<T>>, pull: Pull, freq: Hertz) -> Self {
+    pub fn new_ch1(tim: Peri<'d, T>, pin: Peri<'d, impl TimerPin<T, Ch1>>, pull: Pull, freq: Hertz) -> Self {
         pin.set_as_af(pin.af_num(), AfType::input(pull));
 
         Self::new_inner(tim, freq, Channel::Ch1, Channel::Ch2)
     }
 
     /// Create a new PWM input driver.
-    pub fn new_alt(tim: Peri<'d, T>, pin: Peri<'d, impl Channel2Pin<T>>, pull: Pull, freq: Hertz) -> Self {
+    pub fn new_ch2(tim: Peri<'d, T>, pin: Peri<'d, impl TimerPin<T, Ch2>>, pull: Pull, freq: Hertz) -> Self {
         pin.set_as_af(pin.af_num(), AfType::input(pull));
 
         Self::new_inner(tim, freq, Channel::Ch2, Channel::Ch1)
@@ -37,6 +41,7 @@ impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
 
         // Configuration steps from ST RM0390 (STM32F446) chapter 17.3.6
         // or ST RM0008 (STM32F103) chapter 15.3.6 Input capture mode
+        // or ST RM0440 (STM32G4) chapter 30.4.8 PWM input mode
         inner.set_input_ti_selection(ch1, InputTISelection::Normal);
         inner.set_input_capture_mode(ch1, InputCaptureMode::Rising);
 
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index f3c81667c..eabe1b22a 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -6,8 +6,9 @@ use stm32_metapac::timer::vals;
 
 use super::low_level::Timer;
 pub use super::{Ch1, Ch2};
-use super::{Channel1Pin, Channel2Pin, GeneralInstance4Channel};
+use super::{GeneralInstance4Channel, TimerPin};
 use crate::gpio::{AfType, AnyPin, Pull};
+use crate::timer::TimerChannel;
 use crate::Peri;
 
 /// Counting direction
@@ -24,26 +25,31 @@ pub struct QeiPin<'d, T, Channel> {
     phantom: PhantomData<(T, Channel)>,
 }
 
-macro_rules! channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> QeiPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " QEI pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(pin.af_num(), AfType::input(Pull::None));
-                });
-                QeiPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: GeneralInstance4Channel, C: QeiChannel> QeiPin<'d, T, C> {
+    /// Create a new  QEI pin instance.
+    pub fn new(pin: Peri<'d, impl TimerPin<T, C>>) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            pin.set_as_af(pin.af_num(), AfType::input(Pull::None));
+        });
+        QeiPin {
+            _pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
+    }
 }
 
-channel_impl!(new_ch1, Ch1, Channel1Pin);
-channel_impl!(new_ch2, Ch2, Channel2Pin);
+trait SealedQeiChannel: TimerChannel {}
+
+/// Marker trait for a timer channel eligible for use with QEI.
+#[expect(private_bounds)]
+pub trait QeiChannel: SealedQeiChannel {}
+
+impl QeiChannel for Ch1 {}
+impl QeiChannel for Ch2 {}
+
+impl SealedQeiChannel for Ch1 {}
+impl SealedQeiChannel for Ch2 {}
 
 /// Quadrature decoder driver.
 pub struct Qei<'d, T: GeneralInstance4Channel> {
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index f7f433154..c04b1ab97 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -4,22 +4,13 @@ use core::marker::PhantomData;
 use core::mem::ManuallyDrop;
 
 use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
-use super::{Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin, GeneralInstance4Channel, TimerBits};
+use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerBits, TimerChannel, TimerPin};
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::time::Hertz;
 use crate::Peri;
 
-/// Channel 1 marker type.
-pub enum Ch1 {}
-/// Channel 2 marker type.
-pub enum Ch2 {}
-/// Channel 3 marker type.
-pub enum Ch3 {}
-/// Channel 4 marker type.
-pub enum Ch4 {}
-
 /// PWM pin wrapper.
 ///
 /// This wraps a pin to make it usable with PWM.
@@ -43,46 +34,37 @@ pub struct PwmPinConfig {
     pub pull: Pull,
 }
 
-macro_rules! channel_impl {
-    ($new_chx:ident, $new_chx_with_config:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> PwmPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, output_type: OutputType) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(pin.af_num(), AfType::output(output_type, Speed::VeryHigh));
-                });
-                PwmPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
-
-            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance with config.")]
-            pub fn $new_chx_with_config(pin: Peri<'d, impl $pin_trait<T>>, pin_config: PwmPinConfig) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        #[cfg(gpio_v1)]
-                        AfType::output(pin_config.output_type, pin_config.speed),
-                        #[cfg(gpio_v2)]
-                        AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull),
-                    );
-                });
-                PwmPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: GeneralInstance4Channel, C: TimerChannel> PwmPin<'d, T, C> {
+    /// Create a new PWM pin instance.
+    pub fn new(pin: Peri<'d, impl TimerPin<T, C>>, output_type: OutputType) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            pin.set_as_af(pin.af_num(), AfType::output(output_type, Speed::VeryHigh));
+        });
+        PwmPin {
+            _pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
-}
+    }
 
-channel_impl!(new_ch1, new_ch1_with_config, Ch1, Channel1Pin);
-channel_impl!(new_ch2, new_ch2_with_config, Ch2, Channel2Pin);
-channel_impl!(new_ch3, new_ch3_with_config, Ch3, Channel3Pin);
-channel_impl!(new_ch4, new_ch4_with_config, Ch4, Channel4Pin);
+    /// Create a new PWM pin instance with config.
+    pub fn new_with_config(pin: Peri<'d, impl TimerPin<T, C>>, pin_config: PwmPinConfig) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            pin.set_as_af(
+                pin.af_num(),
+                #[cfg(gpio_v1)]
+                AfType::output(pin_config.output_type, pin_config.speed),
+                #[cfg(gpio_v2)]
+                AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull),
+            );
+        });
+        PwmPin {
+            _pin: pin.into(),
+            phantom: PhantomData,
+        }
+    }
+}
 
 /// A single channel of a pwm, obtained from [`SimplePwm::split`],
 /// [`SimplePwm::channel`], [`SimplePwm::ch1`], etc.
@@ -466,107 +448,98 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     }
 }
 
-macro_rules! impl_waveform_chx {
-    ($fn_name:ident, $dma_ch:ident, $cc_ch:ident) => {
-        impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
-            /// Generate a sequence of PWM waveform
-            pub async fn $fn_name(&mut self, dma: Peri<'_, impl super::$dma_ch<T>>, duty: &[u16]) {
-                use crate::pac::timer::vals::Ccds;
+impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
+    /// Generate a sequence of PWM waveform
+    pub async fn waveform<C: TimerChannel>(&mut self, dma: Peri<'_, impl super::Dma<T, C>>, duty: &[u16]) {
+        use crate::pac::timer::vals::Ccds;
+
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
 
-                #[allow(clippy::let_unit_value)] // eg. stm32f334
-                let req = dma.request();
+        let cc_channel = C::CHANNEL;
 
-                let cc_channel = Channel::$cc_ch;
+        let original_duty_state = self.channel(cc_channel).current_duty_cycle();
+        let original_enable_state = self.channel(cc_channel).is_enabled();
+        let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ON_UPDATE;
+        let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
 
-                let original_duty_state = self.channel(cc_channel).current_duty_cycle();
-                let original_enable_state = self.channel(cc_channel).is_enabled();
-                let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ON_UPDATE;
-                let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
+        // redirect CC DMA request onto Update Event
+        if !original_cc_dma_on_update {
+            self.inner.set_cc_dma_selection(Ccds::ON_UPDATE)
+        }
 
-                // redirect CC DMA request onto Update Event
-                if !original_cc_dma_on_update {
-                    self.inner.set_cc_dma_selection(Ccds::ON_UPDATE)
-                }
+        if !original_cc_dma_enabled {
+            self.inner.set_cc_dma_enable_state(cc_channel, true);
+        }
 
-                if !original_cc_dma_enabled {
-                    self.inner.set_cc_dma_enable_state(cc_channel, true);
-                }
+        if !original_enable_state {
+            self.channel(cc_channel).enable();
+        }
 
-                if !original_enable_state {
-                    self.channel(cc_channel).enable();
-                }
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
 
-                unsafe {
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr8,
+                ..Default::default()
+            };
+
+            match self.inner.bits() {
+                TimerBits::Bits16 => {
+                    Transfer::new_write(
+                        dma,
+                        req,
+                        duty,
+                        self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16,
+                        dma_transfer_option,
+                    )
+                    .await
+                }
+                #[cfg(not(any(stm32l0)))]
+                TimerBits::Bits32 => {
                     #[cfg(not(any(bdma, gpdma)))]
-                    use crate::dma::{Burst, FifoThreshold};
-                    use crate::dma::{Transfer, TransferOptions};
-
-                    let dma_transfer_option = TransferOptions {
-                        #[cfg(not(any(bdma, gpdma)))]
-                        fifo_threshold: Some(FifoThreshold::Full),
-                        #[cfg(not(any(bdma, gpdma)))]
-                        mburst: Burst::Incr8,
-                        ..Default::default()
-                    };
-
-                    match self.inner.bits() {
-                        TimerBits::Bits16 => {
-                            Transfer::new_write(
-                                dma,
-                                req,
-                                duty,
-                                self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16,
-                                dma_transfer_option,
-                            )
-                            .await
-                        }
-                        #[cfg(not(any(stm32l0)))]
-                        TimerBits::Bits32 => {
-                            #[cfg(not(any(bdma, gpdma)))]
-                            panic!("unsupported timer bits");
-
-                            #[cfg(any(bdma, gpdma))]
-                            Transfer::new_write(
-                                dma,
-                                req,
-                                duty,
-                                self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32,
-                                dma_transfer_option,
-                            )
-                            .await
-                        }
-                    };
-                };
-
-                // restore output compare state
-                if !original_enable_state {
-                    self.channel(cc_channel).disable();
+                    panic!("unsupported timer bits");
+
+                    #[cfg(any(bdma, gpdma))]
+                    Transfer::new_write(
+                        dma,
+                        req,
+                        duty,
+                        self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32,
+                        dma_transfer_option,
+                    )
+                    .await
                 }
+            };
+        };
+
+        // restore output compare state
+        if !original_enable_state {
+            self.channel(cc_channel).disable();
+        }
 
-                self.channel(cc_channel).set_duty_cycle(original_duty_state);
+        self.channel(cc_channel).set_duty_cycle(original_duty_state);
 
-                // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
-                // this can almost always trigger a DMA FIFO error.
-                //
-                // optional TODO:
-                // clean FEIF after disable UDE
-                if !original_cc_dma_enabled {
-                    self.inner.set_cc_dma_enable_state(cc_channel, false);
-                }
+        // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
+        // this can almost always trigger a DMA FIFO error.
+        //
+        // optional TODO:
+        // clean FEIF after disable UDE
+        if !original_cc_dma_enabled {
+            self.inner.set_cc_dma_enable_state(cc_channel, false);
+        }
 
-                if !original_cc_dma_on_update {
-                    self.inner.set_cc_dma_selection(Ccds::ON_COMPARE)
-                }
-            }
+        if !original_cc_dma_on_update {
+            self.inner.set_cc_dma_selection(Ccds::ON_COMPARE)
         }
-    };
+    }
 }
 
-impl_waveform_chx!(waveform_ch1, Ch1Dma, Ch1);
-impl_waveform_chx!(waveform_ch2, Ch2Dma, Ch2);
-impl_waveform_chx!(waveform_ch3, Ch3Dma, Ch3);
-impl_waveform_chx!(waveform_ch4, Ch4Dma, Ch4);
-
 impl<'d, T: GeneralInstance4Channel> embedded_hal_1::pwm::ErrorType for SimplePwmChannel<'d, T> {
     type Error = core::convert::Infallible;
 }
diff --git a/embassy-stm32/src/tsc/acquisition_banks.rs b/embassy-stm32/src/tsc/acquisition_banks.rs
index 6791ef6c1..7d6442b48 100644
--- a/embassy-stm32/src/tsc/acquisition_banks.rs
+++ b/embassy-stm32/src/tsc/acquisition_banks.rs
@@ -32,7 +32,7 @@ impl AcquisitionBankPins {
     /// Returns an iterator over the pins in this acquisition bank.
     ///
     /// This method allows for easy traversal of all configured pins in the bank.
-    pub fn iter(&self) -> AcquisitionBankPinsIterator {
+    pub fn iter(&self) -> AcquisitionBankPinsIterator<'_> {
         AcquisitionBankPinsIterator(AcquisitionBankIterator::new(self))
     }
 }
@@ -90,7 +90,7 @@ impl<'a> Iterator for AcquisitionBankPinsIterator<'a> {
 
 impl AcquisitionBankPins {
     /// Returns an iterator over the available pins in the bank
-    pub fn pins_iterator(&self) -> AcquisitionBankPinsIterator {
+    pub fn pins_iterator(&self) -> AcquisitionBankPinsIterator<'_> {
         AcquisitionBankPinsIterator(AcquisitionBankIterator::new(self))
     }
 }
@@ -107,7 +107,7 @@ pub struct AcquisitionBank {
 
 impl AcquisitionBank {
     /// Returns an iterator over the available pins in the bank.
-    pub fn pins_iterator(&self) -> AcquisitionBankPinsIterator {
+    pub fn pins_iterator(&self) -> AcquisitionBankPinsIterator<'_> {
         self.pins.pins_iterator()
     }
 
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 73ab46404..729440c46 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -87,6 +87,8 @@ unsafe fn on_interrupt(r: Regs, state: &'static State) {
 
         r.cr1().modify(|w| {
             w.set_tcie(false);
+            // Reenable receiver for half-duplex if it was disabled
+            w.set_re(true);
         });
 
         state.tx_done.store(true, Ordering::Release);
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index b3f8bc00c..5bece6d66 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -550,6 +550,20 @@ impl<'d, M: Mode> UartTx<'d, M> {
         reconfigure(self.info, self.kernel_clock, config)
     }
 
+    /// Write a single u8 if there is tx empty, otherwise return WouldBlock
+    pub(crate) fn nb_write(&mut self, byte: u8) -> Result<(), nb::Error<Error>> {
+        let r = self.info.regs;
+        let sr = sr(r).read();
+        if sr.txe() {
+            unsafe {
+                tdr(r).write_volatile(byte);
+            }
+            Ok(())
+        } else {
+            Err(nb::Error::WouldBlock)
+        }
+    }
+
     /// Perform a blocking UART write
     pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
         let r = self.info.regs;
@@ -637,7 +651,7 @@ pub fn send_break(regs: &Regs) {
 /// In case of readback, keep Receiver enabled
 fn half_duplex_set_rx_tx_before_write(r: &Regs, enable_readback: bool) {
     let mut cr1 = r.cr1().read();
-    if r.cr3().read().hdsel() && !cr1.te() {
+    if r.cr3().read().hdsel() {
         cr1.set_te(true);
         cr1.set_re(enable_readback);
         r.cr1().write_value(cr1);
@@ -1864,7 +1878,7 @@ impl<'d, M: Mode> embedded_hal_nb::serial::Read for UartRx<'d, M> {
 
 impl<'d, M: Mode> embedded_hal_nb::serial::Write for UartTx<'d, M> {
     fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
-        self.blocking_write(&[char]).map_err(nb::Error::Other)
+        self.nb_write(char)
     }
 
     fn flush(&mut self) -> nb::Result<(), Self::Error> {
diff --git a/embassy-stm32/src/usb/mod.rs b/embassy-stm32/src/usb/mod.rs
index ae5963420..692897b59 100644
--- a/embassy-stm32/src/usb/mod.rs
+++ b/embassy-stm32/src/usb/mod.rs
@@ -15,7 +15,7 @@ fn common_init<T: Instance>() {
     let freq = T::frequency();
 
     // On the H7RS, the USBPHYC embeds a PLL accepting one of the input frequencies listed below and providing 48MHz to OTG_FS and 60MHz to OTG_HS internally
-    #[cfg(any(stm32h7rs, all(stm32u5, peri_usb_otg_hs)))]
+    #[cfg(any(stm32h7rs, all(stm32u5, peri_usb_otg_hs), all(stm32wba, peri_usb_otg_hs)))]
     if ![16_000_000, 19_200_000, 20_000_000, 24_000_000, 26_000_000, 32_000_000].contains(&freq.0) {
         panic!(
             "USB clock should be one of 16, 19.2, 20, 24, 26, 32Mhz but is {} Hz. Please double-check your RCC settings.",
@@ -25,7 +25,7 @@ fn common_init<T: Instance>() {
     // Check frequency is within the 0.25% tolerance allowed by the spec.
     // Clock might not be exact 48Mhz due to rounding errors in PLL calculation, or if the user
     // has tight clock restrictions due to something else (like audio).
-    #[cfg(not(any(stm32h7rs, all(stm32u5, peri_usb_otg_hs))))]
+    #[cfg(not(any(stm32h7rs, all(stm32u5, peri_usb_otg_hs), all(stm32wba, peri_usb_otg_hs))))]
     if freq.0.abs_diff(48_000_000) > 120_000 {
         panic!(
             "USB clock should be 48Mhz but is {} Hz. Please double-check your RCC settings.",
@@ -102,6 +102,30 @@ fn common_init<T: Instance>() {
         }
     }
 
+    #[cfg(stm32wba)]
+    {
+        // Enable USB power
+        critical_section::with(|_| {
+            crate::pac::PWR.svmcr().modify(|w| {
+                w.set_usv(crate::pac::pwr::vals::Usv::B_0X1);
+                // w.set_uvmen(true);
+            })
+        });
+
+        // Wait for USB power to stabilize
+        while !crate::pac::PWR.vosr().read().vdd11usbrdy() {}
+
+        // Now set up transceiver power if it's a OTG-HS
+        #[cfg(peri_usb_otg_hs)]
+        {
+            crate::pac::PWR.vosr().modify(|w| {
+                w.set_usbpwren(true);
+                w.set_usbboosten(true);
+            });
+            while !crate::pac::PWR.vosr().read().usbboostrdy() {}
+        }
+    }
+
     T::Interrupt::unpend();
     unsafe { T::Interrupt::enable() };
 
diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index 590d1a427..b074cfa1b 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -105,7 +105,7 @@ impl<'d, T: Instance> Driver<'d, T> {
         config: Config,
     ) -> Self {
         // For STM32U5 High speed pins need to be left in analog mode
-        #[cfg(not(all(stm32u5, peri_usb_otg_hs)))]
+        #[cfg(not(any(all(stm32u5, peri_usb_otg_hs), all(stm32wba, peri_usb_otg_hs))))]
         {
             _dp.set_as_af(_dp.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
             _dm.set_as_af(_dm.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
@@ -231,19 +231,23 @@ impl<'d, T: Instance> embassy_usb_driver::Driver<'d> for Driver<'d, T> {
     fn alloc_endpoint_in(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointIn, EndpointAllocError> {
-        self.inner.alloc_endpoint_in(ep_type, max_packet_size, interval_ms)
+        self.inner
+            .alloc_endpoint_in(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn alloc_endpoint_out(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointOut, EndpointAllocError> {
-        self.inner.alloc_endpoint_out(ep_type, max_packet_size, interval_ms)
+        self.inner
+            .alloc_endpoint_out(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn start(self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
@@ -323,6 +327,20 @@ impl<'d, T: Instance> Bus<'d, T> {
             });
         }
 
+        #[cfg(all(stm32wba, peri_usb_otg_hs))]
+        {
+            crate::pac::SYSCFG.otghsphycr().modify(|w| {
+                w.set_en(true);
+            });
+
+            critical_section::with(|_| {
+                crate::pac::RCC.ahb2enr().modify(|w| {
+                    w.set_usb_otg_hsen(true);
+                    w.set_otghsphyen(true);
+                });
+            });
+        }
+
         let r = T::regs();
         let core_id = r.cid().read().0;
         trace!("Core id {:08x}", core_id);
@@ -464,6 +482,7 @@ foreach_interrupt!(
                     stm32f7,
                     stm32l4,
                     stm32u5,
+                    stm32wba,
                 ))] {
                     const FIFO_DEPTH_WORDS: u16 = 320;
                     const ENDPOINT_COUNT: usize = 6;
@@ -473,7 +492,7 @@ foreach_interrupt!(
                 } else if #[cfg(any(stm32h7, stm32h7rs))] {
                     const FIFO_DEPTH_WORDS: u16 = 1024;
                     const ENDPOINT_COUNT: usize = 9;
-                } else if #[cfg(stm32u5)] {
+                } else if #[cfg(any(stm32wba, stm32u5))] {
                     const FIFO_DEPTH_WORDS: u16 = 320;
                     const ENDPOINT_COUNT: usize = 6;
                 } else {
@@ -523,7 +542,7 @@ foreach_interrupt!(
                 ))] {
                     const FIFO_DEPTH_WORDS: u16 = 1024;
                     const ENDPOINT_COUNT: usize = 9;
-                } else if #[cfg(stm32u5)] {
+                } else if #[cfg(any(stm32u5, stm32wba))] {
                     const FIFO_DEPTH_WORDS: u16 = 1024;
                     const ENDPOINT_COUNT: usize = 9;
                 } else {
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 3e8e74a1f..92c1601cc 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -359,9 +359,38 @@ impl<'d, T: Instance> Driver<'d, T> {
         addr
     }
 
+    fn is_endpoint_available<D: Dir>(&self, index: usize, ep_type: EndpointType) -> bool {
+        if index == 0 && ep_type != EndpointType::Control {
+            return false; // EP0 is reserved for control
+        }
+
+        let ep = match self.alloc.get(index) {
+            Some(ep) => ep,
+            None => return false,
+        };
+
+        let used = ep.used_out || ep.used_in;
+
+        if used && ep.ep_type == EndpointType::Isochronous {
+            // Isochronous endpoints are always double-buffered.
+            // Their corresponding endpoint/channel registers are forced to be unidirectional.
+            // Do not reuse this index.
+            // FIXME: Bulk endpoints can be double buffered, but are not in the current implementation.
+            return false;
+        }
+
+        let used_dir = match D::dir() {
+            Direction::Out => ep.used_out,
+            Direction::In => ep.used_in,
+        };
+
+        !used || (ep.ep_type == ep_type && !used_dir)
+    }
+
     fn alloc_endpoint<D: Dir>(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Endpoint<'d, T, D>, driver::EndpointAllocError> {
@@ -373,28 +402,17 @@ impl<'d, T: Instance> Driver<'d, T> {
             D::dir()
         );
 
-        let index = self.alloc.iter_mut().enumerate().find(|(i, ep)| {
-            if *i == 0 && ep_type != EndpointType::Control {
-                return false; // reserved for control pipe
-            }
-            let used = ep.used_out || ep.used_in;
-            if used && (ep.ep_type == EndpointType::Isochronous) {
-                // Isochronous endpoints are always double-buffered.
-                // Their corresponding endpoint/channel registers are forced to be unidirectional.
-                // Do not reuse this index.
-                // FIXME: Bulk endpoints can be double buffered, but are not in the current implementation.
-                return false;
-            }
-
-            let used_dir = match D::dir() {
-                Direction::Out => ep.used_out,
-                Direction::In => ep.used_in,
-            };
-            !used || (ep.ep_type == ep_type && !used_dir)
-        });
+        let index = if let Some(addr) = ep_addr {
+            // Use the specified endpoint address
+            self.is_endpoint_available::<D>(addr.index(), ep_type)
+                .then_some(addr.index())
+        } else {
+            // Find any available endpoint
+            (0..self.alloc.len()).find(|&i| self.is_endpoint_available::<D>(i, ep_type))
+        };
 
         let (index, ep) = match index {
-            Some(x) => x,
+            Some(i) => (i, &mut self.alloc[i]),
             None => return Err(EndpointAllocError),
         };
 
@@ -479,27 +497,29 @@ impl<'d, T: Instance> driver::Driver<'d> for Driver<'d, T> {
     fn alloc_endpoint_in(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointIn, driver::EndpointAllocError> {
-        self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
+        self.alloc_endpoint(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn alloc_endpoint_out(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointOut, driver::EndpointAllocError> {
-        self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
+        self.alloc_endpoint(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn start(mut self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
         let ep_out = self
-            .alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
+            .alloc_endpoint(EndpointType::Control, None, control_max_packet_size, 0)
             .unwrap();
         let ep_in = self
-            .alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
+            .alloc_endpoint(EndpointType::Control, None, control_max_packet_size, 0)
             .unwrap();
         assert_eq!(ep_out.info.addr.index(), 0);
         assert_eq!(ep_in.info.addr.index(), 0);
diff --git a/embassy-sync/Cargo.toml b/embassy-sync/Cargo.toml
index 99962f9f6..9e5c39f5e 100644
--- a/embassy-sync/Cargo.toml
+++ b/embassy-sync/Cargo.toml
@@ -28,7 +28,7 @@ defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.14", optional = true }
 
 futures-sink = { version = "0.3", default-features = false, features = [] }
-futures-util = { version = "0.3.17", default-features = false }
+futures-core = { version = "0.3.31", default-features = false }
 critical-section = "1.1"
 heapless = "0.8"
 cfg-if = "1.0.0"
@@ -43,3 +43,4 @@ futures-util = { version = "0.3.17", features = [ "channel", "sink" ] }
 # Enable critical-section implementation for std, for tests
 critical-section = { version = "1.1", features = ["std"] }
 static_cell = { version = "2" }
+trybuild = "1.0.105"
diff --git a/embassy-sync/src/channel.rs b/embassy-sync/src/channel.rs
index 856551417..a0e39fcb5 100644
--- a/embassy-sync/src/channel.rs
+++ b/embassy-sync/src/channel.rs
@@ -17,6 +17,31 @@
 //! messages that it can store, and if this limit is reached, trying to send
 //! another message will result in an error being returned.
 //!
+//! # Example: Message passing between task and interrupt handler
+//!
+//! ```rust
+//! use embassy_sync::channel::Channel;
+//! use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+//!
+//! static SHARED_CHANNEL: Channel<CriticalSectionRawMutex, u32, 8> = Channel::new();
+//!
+//! fn my_interrupt_handler() {
+//!     // Do some work..
+//!     // ...
+//!     if let Err(e) = SHARED_CHANNEL.sender().try_send(42) {
+//!         // Channel is full..
+//!     }
+//! }
+//!
+//! async fn my_async_task() {
+//!     // ...
+//!     let receiver = SHARED_CHANNEL.receiver();
+//!     loop {
+//!         let data_from_interrupt = receiver.receive().await;
+//!         // Do something with the data.
+//!     }
+//! }
+//! ```
 
 use core::cell::RefCell;
 use core::future::Future;
@@ -443,7 +468,7 @@ where
     }
 }
 
-impl<'ch, M, T, const N: usize> futures_util::Stream for Receiver<'ch, M, T, N>
+impl<'ch, M, T, const N: usize> futures_core::Stream for Receiver<'ch, M, T, N>
 where
     M: RawMutex,
 {
@@ -962,7 +987,7 @@ where
     }
 }
 
-impl<M, T, const N: usize> futures_util::Stream for Channel<M, T, N>
+impl<M, T, const N: usize> futures_core::Stream for Channel<M, T, N>
 where
     M: RawMutex,
 {
diff --git a/embassy-sync/src/lazy_lock.rs b/embassy-sync/src/lazy_lock.rs
index 18e3c2019..f1bd88b61 100644
--- a/embassy-sync/src/lazy_lock.rs
+++ b/embassy-sync/src/lazy_lock.rs
@@ -31,7 +31,12 @@ union Data<T, F> {
     f: ManuallyDrop<F>,
 }
 
-unsafe impl<T, F> Sync for LazyLock<T, F> {}
+unsafe impl<T, F> Sync for LazyLock<T, F>
+where
+    T: Sync,
+    F: Sync,
+{
+}
 
 impl<T, F: FnOnce() -> T> LazyLock<T, F> {
     /// Create a new uninitialized `StaticLock`.
diff --git a/embassy-sync/src/mutex.rs b/embassy-sync/src/mutex.rs
index 7528a9f68..8496f34bf 100644
--- a/embassy-sync/src/mutex.rs
+++ b/embassy-sync/src/mutex.rs
@@ -23,7 +23,7 @@ struct State {
 
 /// Async mutex.
 ///
-/// The mutex is generic over a blocking [`RawMutex`](crate::blocking_mutex::raw::RawMutex).
+/// The mutex is generic over a blocking [`RawMutex`].
 /// The raw mutex is used to guard access to the internal "is locked" flag. It
 /// is held for very short periods only, while locking and unlocking. It is *not* held
 /// for the entire time the async Mutex is locked.
diff --git a/embassy-sync/src/once_lock.rs b/embassy-sync/src/once_lock.rs
index cd05b986d..1e848685a 100644
--- a/embassy-sync/src/once_lock.rs
+++ b/embassy-sync/src/once_lock.rs
@@ -42,7 +42,7 @@ pub struct OnceLock<T> {
     data: Cell<MaybeUninit<T>>,
 }
 
-unsafe impl<T> Sync for OnceLock<T> {}
+unsafe impl<T> Sync for OnceLock<T> where T: Sync {}
 
 impl<T> OnceLock<T> {
     /// Create a new uninitialized `OnceLock`.
diff --git a/embassy-sync/src/pipe.rs b/embassy-sync/src/pipe.rs
index 2598652d2..df3b28b45 100644
--- a/embassy-sync/src/pipe.rs
+++ b/embassy-sync/src/pipe.rs
@@ -152,7 +152,7 @@ where
 
 impl<'p, M, const N: usize> Unpin for ReadFuture<'p, M, N> where M: RawMutex {}
 
-/// Future returned by [`Pipe::fill_buf`] and  [`Reader::fill_buf`].
+/// Future returned by [`Reader::fill_buf`].
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct FillBufFuture<'p, M, const N: usize>
 where
@@ -587,7 +587,7 @@ where
     }
 }
 
-/// Write-only access to a [`DynamicPipe`].
+/// Write-only access to the dynamic pipe.
 pub struct DynamicWriter<'p> {
     pipe: &'p dyn DynamicPipe,
 }
@@ -657,7 +657,7 @@ where
     }
 }
 
-/// Read-only access to a [`DynamicPipe`].
+/// Read-only access to a dynamic pipe.
 pub struct DynamicReader<'p> {
     pipe: &'p dyn DynamicPipe,
 }
@@ -742,7 +742,7 @@ where
     }
 }
 
-/// Future returned by [`DynamicPipe::fill_buf`] and  [`DynamicReader::fill_buf`].
+/// Future returned by [`DynamicReader::fill_buf`].
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct DynamicFillBufFuture<'p> {
     pipe: Option<&'p dyn DynamicPipe>,
diff --git a/embassy-sync/src/priority_channel.rs b/embassy-sync/src/priority_channel.rs
index 623c52993..715a20e86 100644
--- a/embassy-sync/src/priority_channel.rs
+++ b/embassy-sync/src/priority_channel.rs
@@ -1,7 +1,7 @@
 //! A queue for sending values between asynchronous tasks.
 //!
 //! Similar to a [`Channel`](crate::channel::Channel), however [`PriorityChannel`] sifts higher priority items to the front of the queue.
-//! Priority is determined by the `Ord` trait. Priority behavior is determined by the [`Kind`](heapless::binary_heap::Kind) parameter of the channel.
+//! Priority is determined by the `Ord` trait. Priority behavior is determined by the [`Kind`] parameter of the channel.
 
 use core::cell::RefCell;
 use core::future::Future;
@@ -473,7 +473,7 @@ where
 /// received from the channel.
 ///
 /// Sent data may be reordered based on their priority within the channel.
-/// For example, in a [`Max`](heapless::binary_heap::Max) [`PriorityChannel`]
+/// For example, in a [`Max`] [`PriorityChannel`]
 /// containing `u32`'s, data sent in the following order `[1, 2, 3]` will be received as `[3, 2, 1]`.
 pub struct PriorityChannel<M, T, K, const N: usize>
 where
diff --git a/embassy-sync/src/pubsub/mod.rs b/embassy-sync/src/pubsub/mod.rs
index 606efff0a..9206b9383 100644
--- a/embassy-sync/src/pubsub/mod.rs
+++ b/embassy-sync/src/pubsub/mod.rs
@@ -88,7 +88,7 @@ impl<M: RawMutex, T: Clone, const CAP: usize, const SUBS: usize, const PUBS: usi
     /// Create a new subscriber. It will only receive messages that are published after its creation.
     ///
     /// If there are no subscriber slots left, an error will be returned.
-    pub fn subscriber(&self) -> Result<Subscriber<M, T, CAP, SUBS, PUBS>, Error> {
+    pub fn subscriber(&self) -> Result<Subscriber<'_, M, T, CAP, SUBS, PUBS>, Error> {
         self.inner.lock(|inner| {
             let mut s = inner.borrow_mut();
 
@@ -120,7 +120,7 @@ impl<M: RawMutex, T: Clone, const CAP: usize, const SUBS: usize, const PUBS: usi
     /// Create a new publisher
     ///
     /// If there are no publisher slots left, an error will be returned.
-    pub fn publisher(&self) -> Result<Publisher<M, T, CAP, SUBS, PUBS>, Error> {
+    pub fn publisher(&self) -> Result<Publisher<'_, M, T, CAP, SUBS, PUBS>, Error> {
         self.inner.lock(|inner| {
             let mut s = inner.borrow_mut();
 
@@ -151,13 +151,13 @@ impl<M: RawMutex, T: Clone, const CAP: usize, const SUBS: usize, const PUBS: usi
 
     /// Create a new publisher that can only send immediate messages.
     /// This kind of publisher does not take up a publisher slot.
-    pub fn immediate_publisher(&self) -> ImmediatePublisher<M, T, CAP, SUBS, PUBS> {
+    pub fn immediate_publisher(&self) -> ImmediatePublisher<'_, M, T, CAP, SUBS, PUBS> {
         ImmediatePublisher(ImmediatePub::new(self))
     }
 
     /// Create a new publisher that can only send immediate messages.
     /// This kind of publisher does not take up a publisher slot.
-    pub fn dyn_immediate_publisher(&self) -> DynImmediatePublisher<T> {
+    pub fn dyn_immediate_publisher(&self) -> DynImmediatePublisher<'_, T> {
         DynImmediatePublisher(ImmediatePub::new(self))
     }
 
diff --git a/embassy-sync/src/pubsub/publisher.rs b/embassy-sync/src/pubsub/publisher.rs
index 7a1ab66de..52a52f926 100644
--- a/embassy-sync/src/pubsub/publisher.rs
+++ b/embassy-sync/src/pubsub/publisher.rs
@@ -75,7 +75,7 @@ impl<'a, PSB: PubSubBehavior<T> + ?Sized, T: Clone> Pub<'a, PSB, T> {
         self.channel.is_full()
     }
 
-    /// Create a [`futures::Sink`] adapter for this publisher.
+    /// Create a [`futures_sink::Sink`] adapter for this publisher.
     #[inline]
     pub const fn sink(&self) -> PubSink<'a, '_, PSB, T> {
         PubSink { publ: self, fut: None }
diff --git a/embassy-sync/src/pubsub/subscriber.rs b/embassy-sync/src/pubsub/subscriber.rs
index 6ad660cb3..649382cf1 100644
--- a/embassy-sync/src/pubsub/subscriber.rs
+++ b/embassy-sync/src/pubsub/subscriber.rs
@@ -115,7 +115,7 @@ impl<'a, PSB: PubSubBehavior<T> + ?Sized, T: Clone> Unpin for Sub<'a, PSB, T> {}
 
 /// Warning: The stream implementation ignores lag results and returns all messages.
 /// This might miss some messages without you knowing it.
-impl<'a, PSB: PubSubBehavior<T> + ?Sized, T: Clone> futures_util::Stream for Sub<'a, PSB, T> {
+impl<'a, PSB: PubSubBehavior<T> + ?Sized, T: Clone> futures_core::Stream for Sub<'a, PSB, T> {
     type Item = T;
 
     fn poll_next(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Option<Self::Item>> {
diff --git a/embassy-sync/tests/ui.rs b/embassy-sync/tests/ui.rs
new file mode 100644
index 000000000..e8b1080d8
--- /dev/null
+++ b/embassy-sync/tests/ui.rs
@@ -0,0 +1,13 @@
+#[cfg(not(miri))]
+#[test]
+fn ui() {
+    let t = trybuild::TestCases::new();
+
+    // These test cases should fail to compile since OnceLock and LazyLock should not unconditionally implement sync
+    // for all types. These tests are regression tests against the following issues:
+    // * https://github.com/embassy-rs/embassy/issues/4307
+    // * https://github.com/embassy-rs/embassy/issues/3904
+    t.compile_fail("tests/ui/sync_impl/lazy_lock_function.rs");
+    t.compile_fail("tests/ui/sync_impl/lazy_lock_type.rs");
+    t.compile_fail("tests/ui/sync_impl/once_lock.rs");
+}
diff --git a/embassy-sync/tests/ui/sync_impl/lazy_lock_function.rs b/embassy-sync/tests/ui/sync_impl/lazy_lock_function.rs
new file mode 100644
index 000000000..35f5587c0
--- /dev/null
+++ b/embassy-sync/tests/ui/sync_impl/lazy_lock_function.rs
@@ -0,0 +1,11 @@
+use embassy_sync::lazy_lock::LazyLock;
+
+fn main() {
+    let x = 128u8;
+    let x_ptr: *const u8 = core::ptr::addr_of!(x);
+    let closure_capturing_non_sync_variable = || unsafe { core::ptr::read(x_ptr) };
+
+    check_sync(LazyLock::new(closure_capturing_non_sync_variable));
+}
+
+fn check_sync<T: Sync>(_lazy_lock: T) {}
diff --git a/embassy-sync/tests/ui/sync_impl/lazy_lock_function.stderr b/embassy-sync/tests/ui/sync_impl/lazy_lock_function.stderr
new file mode 100644
index 000000000..daf79ad28
--- /dev/null
+++ b/embassy-sync/tests/ui/sync_impl/lazy_lock_function.stderr
@@ -0,0 +1,24 @@
+error[E0277]: `*const u8` cannot be shared between threads safely
+  --> tests/ui/sync_impl/lazy_lock_function.rs:8:16
+   |
+6  |     let closure_capturing_non_sync_variable = || unsafe { core::ptr::read(x_ptr) };
+   |                                               -- within this `{closure@$DIR/tests/ui/sync_impl/lazy_lock_function.rs:6:47: 6:49}`
+7  |
+8  |     check_sync(LazyLock::new(closure_capturing_non_sync_variable));
+   |     ---------- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ `*const u8` cannot be shared between threads safely
+   |     |
+   |     required by a bound introduced by this call
+   |
+   = help: within `{closure@$DIR/tests/ui/sync_impl/lazy_lock_function.rs:6:47: 6:49}`, the trait `Sync` is not implemented for `*const u8`
+   = note: required because it appears within the type `&*const u8`
+note: required because it's used within this closure
+  --> tests/ui/sync_impl/lazy_lock_function.rs:6:47
+   |
+6  |     let closure_capturing_non_sync_variable = || unsafe { core::ptr::read(x_ptr) };
+   |                                               ^^
+   = note: required for `embassy_sync::lazy_lock::LazyLock<u8, {closure@$DIR/tests/ui/sync_impl/lazy_lock_function.rs:6:47: 6:49}>` to implement `Sync`
+note: required by a bound in `check_sync`
+  --> tests/ui/sync_impl/lazy_lock_function.rs:11:18
+   |
+11 | fn check_sync<T: Sync>(_lazy_lock: T) {}
+   |                  ^^^^ required by this bound in `check_sync`
diff --git a/embassy-sync/tests/ui/sync_impl/lazy_lock_type.rs b/embassy-sync/tests/ui/sync_impl/lazy_lock_type.rs
new file mode 100644
index 000000000..4e1383143
--- /dev/null
+++ b/embassy-sync/tests/ui/sync_impl/lazy_lock_type.rs
@@ -0,0 +1,6 @@
+use embassy_sync::lazy_lock::LazyLock;
+
+// *mut u8 is not Sync, so LazyLock should not implement Sync for this type. This should fail to compile.
+static GLOBAL: LazyLock<*mut u8> = LazyLock::new(|| core::ptr::null_mut());
+
+fn main() {}
diff --git a/embassy-sync/tests/ui/sync_impl/lazy_lock_type.stderr b/embassy-sync/tests/ui/sync_impl/lazy_lock_type.stderr
new file mode 100644
index 000000000..1ccc54c7a
--- /dev/null
+++ b/embassy-sync/tests/ui/sync_impl/lazy_lock_type.stderr
@@ -0,0 +1,9 @@
+error[E0277]: `*mut u8` cannot be shared between threads safely
+ --> tests/ui/sync_impl/lazy_lock_type.rs:4:16
+  |
+4 | static GLOBAL: LazyLock<*mut u8> = LazyLock::new(|| core::ptr::null_mut());
+  |                ^^^^^^^^^^^^^^^^^ `*mut u8` cannot be shared between threads safely
+  |
+  = help: the trait `Sync` is not implemented for `*mut u8`
+  = note: required for `embassy_sync::lazy_lock::LazyLock<*mut u8>` to implement `Sync`
+  = note: shared static variables must have a type that implements `Sync`
diff --git a/embassy-sync/tests/ui/sync_impl/once_lock.rs b/embassy-sync/tests/ui/sync_impl/once_lock.rs
new file mode 100644
index 000000000..8f50d583b
--- /dev/null
+++ b/embassy-sync/tests/ui/sync_impl/once_lock.rs
@@ -0,0 +1,6 @@
+use embassy_sync::once_lock::OnceLock;
+
+// *mut u8 is not Sync, so OnceLock should not implement Sync for this type. This should fail to compile.
+static GLOBAL: OnceLock<*mut u8> = OnceLock::new();
+
+fn main() {}
diff --git a/embassy-sync/tests/ui/sync_impl/once_lock.stderr b/embassy-sync/tests/ui/sync_impl/once_lock.stderr
new file mode 100644
index 000000000..e2419f844
--- /dev/null
+++ b/embassy-sync/tests/ui/sync_impl/once_lock.stderr
@@ -0,0 +1,9 @@
+error[E0277]: `*mut u8` cannot be shared between threads safely
+ --> tests/ui/sync_impl/once_lock.rs:4:16
+  |
+4 | static GLOBAL: OnceLock<*mut u8> = OnceLock::new();
+  |                ^^^^^^^^^^^^^^^^^ `*mut u8` cannot be shared between threads safely
+  |
+  = help: the trait `Sync` is not implemented for `*mut u8`
+  = note: required for `embassy_sync::once_lock::OnceLock<*mut u8>` to implement `Sync`
+  = note: shared static variables must have a type that implements `Sync`
diff --git a/embassy-time-driver/CHANGELOG.md b/embassy-time-driver/CHANGELOG.md
index 744b0f648..b61a10bf6 100644
--- a/embassy-time-driver/CHANGELOG.md
+++ b/embassy-time-driver/CHANGELOG.md
@@ -5,6 +5,12 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+<!-- next-header -->
+## Unreleased - ReleaseDate
+
+- Allow inlining on time driver boundary
+- add 133MHz tick rate to support PR2040 @ 133MHz when `TIMERx`'s `SOURCE` is set to `SYSCLK`
+
 ## 0.2.0 - 2025-01-02
 
 - The `allocate_alarm`, `set_alarm_callback`, `set_alarm` functions have been removed.
diff --git a/embassy-time-driver/release.toml b/embassy-time-driver/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/embassy-time-driver/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/embassy-time/CHANGELOG.md b/embassy-time/CHANGELOG.md
index 09e951ce4..a0c1abe8d 100644
--- a/embassy-time/CHANGELOG.md
+++ b/embassy-time/CHANGELOG.md
@@ -5,6 +5,17 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+<!-- next-header -->
+## Unreleased - ReleaseDate
+
+- Allow inlining on time driver boundary
+- Add `saturating_add` and `saturating_sub` to `Instant`
+- Add `Instant::try_from_*` constructor functions
+- Add `Duration::try_from_*` constructor functions
+- Don't select `critical-section` impl for `std`
+- Manually implement the future for `with_timeout`
+- Add 133MHz tick rate to support PR2040 @ 133MHz when `TIMERx`'s `SOURCE` is set to `SYSCLK`
+
 ## 0.4.0 - 2025-01-02
 
 - `embassy-time-driver` updated from v0.1 to v0.2.
diff --git a/embassy-time/Cargo.toml b/embassy-time/Cargo.toml
index 76983d880..2284906b0 100644
--- a/embassy-time/Cargo.toml
+++ b/embassy-time/Cargo.toml
@@ -427,7 +427,7 @@ embedded-hal-02 = { package = "embedded-hal", version = "0.2.6" }
 embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
 embedded-hal-async = { version = "1.0" }
 
-futures-util = { version = "0.3.17", default-features = false }
+futures-core = { version = "0.3.31", default-features = false }
 critical-section = "1.1"
 cfg-if = "1.0.0"
 
diff --git a/embassy-time/release.toml b/embassy-time/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/embassy-time/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/embassy-time/src/timer.rs b/embassy-time/src/timer.rs
index d1162eadd..d3f1e1621 100644
--- a/embassy-time/src/timer.rs
+++ b/embassy-time/src/timer.rs
@@ -2,8 +2,8 @@ use core::future::{poll_fn, Future};
 use core::pin::Pin;
 use core::task::{Context, Poll};
 
-use futures_util::stream::FusedStream;
-use futures_util::Stream;
+use futures_core::stream::FusedStream;
+use futures_core::Stream;
 
 use crate::{Duration, Instant};
 
diff --git a/embassy-usb-dfu/Cargo.toml b/embassy-usb-dfu/Cargo.toml
index 8b2467bca..011046ba4 100644
--- a/embassy-usb-dfu/Cargo.toml
+++ b/embassy-usb-dfu/Cargo.toml
@@ -31,11 +31,11 @@ log = { version = "0.4.17", optional = true }
 
 bitflags = "2.4.1"
 cortex-m = { version = "0.7.7", features = ["inline-asm"], optional = true }
-embassy-boot = { version = "0.4.0", path = "../embassy-boot" }
+embassy-boot = { version = "0.5.0", path = "../embassy-boot" }
 embassy-futures = { version = "0.1.1", path = "../embassy-futures" }
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
 embassy-time = { version = "0.4.0", path = "../embassy-time" }
-embassy-usb = { version = "0.4.0", path = "../embassy-usb", default-features = false }
+embassy-usb = { version = "0.5.0", path = "../embassy-usb", default-features = false }
 embedded-storage = { version = "0.3.1" }
 esp32c3-hal = { version = "0.13.0", optional = true, default-features = false }
 
diff --git a/embassy-usb-driver/CHANGELOG.md b/embassy-usb-driver/CHANGELOG.md
new file mode 100644
index 000000000..15875e087
--- /dev/null
+++ b/embassy-usb-driver/CHANGELOG.md
@@ -0,0 +1,17 @@
+# Changelog for embassy-usb-driver
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
+and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
+
+<!-- next-header -->
+## Unreleased - ReleaseDate
+
+## 0.2.0 - 2025-07-16
+
+- Make USB endpoint allocator methods accept an optional `EndpointAddress`.
+
+## 0.1.1 - 2025-07-15
+
+- Add `embedded_io_async::Error` implementation for `EndpointError` ([#4176](https://github.com/embassy-rs/embassy/pull/4176))
diff --git a/embassy-usb-driver/Cargo.toml b/embassy-usb-driver/Cargo.toml
index e40421649..de69bf694 100644
--- a/embassy-usb-driver/Cargo.toml
+++ b/embassy-usb-driver/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-usb-driver"
-version = "0.1.0"
+version = "0.2.0"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "Driver trait for `embassy-usb`, an async USB device stack for embedded devices."
diff --git a/embassy-usb-driver/release.toml b/embassy-usb-driver/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/embassy-usb-driver/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/embassy-usb-driver/src/lib.rs b/embassy-usb-driver/src/lib.rs
index d204e4d85..99616f1ec 100644
--- a/embassy-usb-driver/src/lib.rs
+++ b/embassy-usb-driver/src/lib.rs
@@ -136,6 +136,7 @@ pub trait Driver<'a> {
     fn alloc_endpoint_out(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointOut, EndpointAllocError>;
@@ -153,6 +154,7 @@ pub trait Driver<'a> {
     fn alloc_endpoint_in(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointIn, EndpointAllocError>;
diff --git a/embassy-usb-logger/CHANGELOG.md b/embassy-usb-logger/CHANGELOG.md
index 86a9fb032..79ea25839 100644
--- a/embassy-usb-logger/CHANGELOG.md
+++ b/embassy-usb-logger/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## Unreleased
 
+## 0.5.0 - 2025-07-22
+
+- Update `embassy-usb` to 0.5.0
+
 ## 0.4.0 - 2025-01-15
 
 - Update `embassy-usb` to 0.4.0
diff --git a/embassy-usb-logger/Cargo.toml b/embassy-usb-logger/Cargo.toml
index 6b8e9af47..68b11ad8a 100644
--- a/embassy-usb-logger/Cargo.toml
+++ b/embassy-usb-logger/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-usb-logger"
-version = "0.4.0"
+version = "0.5.0"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "`log` implementation for USB serial using `embassy-usb`."
@@ -15,7 +15,7 @@ src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-usb-l
 target = "thumbv7em-none-eabi"
 
 [dependencies]
-embassy-usb = { version = "0.4.0", path = "../embassy-usb" }
+embassy-usb = { version = "0.5.0", path = "../embassy-usb" }
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
 log = "0.4"
diff --git a/embassy-usb-synopsys-otg/CHANGELOG.md b/embassy-usb-synopsys-otg/CHANGELOG.md
index 293363d9a..9913ee533 100644
--- a/embassy-usb-synopsys-otg/CHANGELOG.md
+++ b/embassy-usb-synopsys-otg/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## Unreleased
 
+## 0.3.0 - 2025-07-22
+
+- Bump `embassy-usb-driver` to v0.2.0
+
 ## 0.2.0 - 2024-12-06
 
 - Fix corruption in CONTROL OUT transfers (and remove `quirk_setup_late_cnak`)
diff --git a/embassy-usb-synopsys-otg/Cargo.toml b/embassy-usb-synopsys-otg/Cargo.toml
index 6252feaef..78cce24de 100644
--- a/embassy-usb-synopsys-otg/Cargo.toml
+++ b/embassy-usb-synopsys-otg/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-usb-synopsys-otg"
-version = "0.2.0"
+version = "0.3.0"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "`embassy-usb-driver` implementation for Synopsys OTG USB controllers"
@@ -19,7 +19,7 @@ target = "thumbv7em-none-eabi"
 critical-section = "1.1"
 
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
-embassy-usb-driver = { version = "0.1.0", path = "../embassy-usb-driver" }
+embassy-usb-driver = { version = "0.2.0", path = "../embassy-usb-driver" }
 
 defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.14", optional = true }
diff --git a/embassy-usb-synopsys-otg/src/lib.rs b/embassy-usb-synopsys-otg/src/lib.rs
index fc4428b54..9d74c046d 100644
--- a/embassy-usb-synopsys-otg/src/lib.rs
+++ b/embassy-usb-synopsys-otg/src/lib.rs
@@ -345,6 +345,7 @@ impl<'d, const MAX_EP_COUNT: usize> Driver<'d, MAX_EP_COUNT> {
     fn alloc_endpoint<D: Dir>(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Endpoint<'d, D>, EndpointAllocError> {
@@ -379,15 +380,31 @@ impl<'d, const MAX_EP_COUNT: usize> Driver<'d, MAX_EP_COUNT> {
             Direction::In => &mut self.ep_in[..self.instance.endpoint_count],
         };
 
-        // Find free endpoint slot
-        let slot = eps.iter_mut().enumerate().find(|(i, ep)| {
-            if *i == 0 && ep_type != EndpointType::Control {
-                // reserved for control pipe
-                false
-            } else {
-                ep.is_none()
+        // Find endpoint slot
+        let slot = if let Some(addr) = ep_addr {
+            // Use the specified endpoint address
+            let requested_index = addr.index();
+            if requested_index >= self.instance.endpoint_count {
+                return Err(EndpointAllocError);
             }
-        });
+            if requested_index == 0 && ep_type != EndpointType::Control {
+                return Err(EndpointAllocError); // EP0 is reserved for control
+            }
+            if eps[requested_index].is_some() {
+                return Err(EndpointAllocError); // Already allocated
+            }
+            Some((requested_index, &mut eps[requested_index]))
+        } else {
+            // Find any free endpoint slot
+            eps.iter_mut().enumerate().find(|(i, ep)| {
+                if *i == 0 && ep_type != EndpointType::Control {
+                    // reserved for control pipe
+                    false
+                } else {
+                    ep.is_none()
+                }
+            })
+        };
 
         let index = match slot {
             Some((index, ep)) => {
@@ -438,27 +455,29 @@ impl<'d, const MAX_EP_COUNT: usize> embassy_usb_driver::Driver<'d> for Driver<'d
     fn alloc_endpoint_in(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointIn, EndpointAllocError> {
-        self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
+        self.alloc_endpoint(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn alloc_endpoint_out(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointOut, EndpointAllocError> {
-        self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
+        self.alloc_endpoint(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn start(mut self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
         let ep_out = self
-            .alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
+            .alloc_endpoint(EndpointType::Control, None, control_max_packet_size, 0)
             .unwrap();
         let ep_in = self
-            .alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
+            .alloc_endpoint(EndpointType::Control, None, control_max_packet_size, 0)
             .unwrap();
         assert_eq!(ep_out.info.addr.index(), 0);
         assert_eq!(ep_in.info.addr.index(), 0);
@@ -1210,10 +1229,23 @@ impl<'d> embassy_usb_driver::EndpointIn for Endpoint<'d, In> {
             });
 
             // Write data to FIFO
-            for chunk in buf.chunks(4) {
+            let chunks = buf.chunks_exact(4);
+            // Stash the last partial chunk
+            let rem = chunks.remainder();
+            let last_chunk = (!rem.is_empty()).then(|| {
                 let mut tmp = [0u8; 4];
-                tmp[0..chunk.len()].copy_from_slice(chunk);
-                self.regs.fifo(index).write_value(regs::Fifo(u32::from_ne_bytes(tmp)));
+                tmp[0..rem.len()].copy_from_slice(rem);
+                u32::from_ne_bytes(tmp)
+            });
+
+            let fifo = self.regs.fifo(index);
+            for chunk in chunks {
+                let val = u32::from_ne_bytes(chunk.try_into().unwrap());
+                fifo.write_value(regs::Fifo(val));
+            }
+            // Write any last chunk
+            if let Some(val) = last_chunk {
+                fifo.write_value(regs::Fifo(val));
             }
         });
 
diff --git a/embassy-usb/CHANGELOG.md b/embassy-usb/CHANGELOG.md
index 76fafed31..3ee75e226 100644
--- a/embassy-usb/CHANGELOG.md
+++ b/embassy-usb/CHANGELOG.md
@@ -5,7 +5,18 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## Unreleased
+<!-- next-header -->
+## Unreleased - ReleaseDate
+
+## 0.5.0 - 2025-07-16
+
+- `UAC1`: unmute by default ([#3992](https://github.com/embassy-rs/embassy/pull/3992))
+- `cdc_acm`: `State::new` is now `const` ([#4000](https://github.com/embassy-rs/embassy/pull/4000))
+- Add support for CMSIS-DAP v2 USB class ([#4107](https://github.com/embassy-rs/embassy/pull/4107))
+- Reduce `UsbDevice` builder logs to `trace` ([#4130](https://github.com/embassy-rs/embassy/pull/4130))
+- Implement `embedded-io-async` traits for USB CDC ACM ([#4176](https://github.com/embassy-rs/embassy/pull/4176))
+- Update `embassy-sync` to v0.7.0
+- Fix CDC ACM BufferedReceiver buffer calculation
 
 ## 0.4.0 - 2025-01-15
 
diff --git a/embassy-usb/Cargo.toml b/embassy-usb/Cargo.toml
index 31fd1c1e0..4743fde65 100644
--- a/embassy-usb/Cargo.toml
+++ b/embassy-usb/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-usb"
-version = "0.4.0"
+version = "0.5.0"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "Async USB device stack for embedded devices in Rust."
@@ -47,9 +47,9 @@ max-handler-count-8 = []
 
 [dependencies]
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
-embassy-usb-driver = { version = "0.1.0", path = "../embassy-usb-driver" }
+embassy-usb-driver = { version = "0.2.0", path = "../embassy-usb-driver" }
 embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
-embassy-net-driver-channel = { version = "0.3.0", path = "../embassy-net-driver-channel" }
+embassy-net-driver-channel = { version = "0.3.1", path = "../embassy-net-driver-channel" }
 
 defmt = { version = "1", optional = true }
 log = { version = "0.4.14", optional = true }
diff --git a/embassy-usb/release.toml b/embassy-usb/release.toml
new file mode 100644
index 000000000..fb6feaf21
--- /dev/null
+++ b/embassy-usb/release.toml
@@ -0,0 +1,5 @@
+pre-release-replacements = [
+    {file="CHANGELOG.md", search="Unreleased", replace="{{version}}", min=1},
+    {file="CHANGELOG.md", search="ReleaseDate", replace="{{date}}", min=1},
+    {file="CHANGELOG.md", search="<!-- next-header -->", replace="<!-- next-header -->\n## Unreleased - ReleaseDate\n", exactly=1},
+]
diff --git a/embassy-usb/src/builder.rs b/embassy-usb/src/builder.rs
index 6c4b3f9a4..8d7abe46c 100644
--- a/embassy-usb/src/builder.rs
+++ b/embassy-usb/src/builder.rs
@@ -2,7 +2,7 @@ use heapless::Vec;
 
 use crate::config::MAX_HANDLER_COUNT;
 use crate::descriptor::{BosWriter, DescriptorWriter, SynchronizationType, UsageType};
-use crate::driver::{Driver, Endpoint, EndpointInfo, EndpointType};
+use crate::driver::{Driver, Endpoint, EndpointAddress, EndpointInfo, EndpointType};
 use crate::msos::{DeviceLevelDescriptor, FunctionLevelDescriptor, MsOsDescriptorWriter};
 use crate::types::{InterfaceNumber, StringIndex};
 use crate::{Handler, Interface, UsbDevice, MAX_INTERFACE_COUNT, STRING_INDEX_CUSTOM_START};
@@ -465,11 +465,17 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     /// Allocate an IN endpoint, without writing its descriptor.
     ///
     /// Used for granular control over the order of endpoint and descriptor creation.
-    pub fn alloc_endpoint_in(&mut self, ep_type: EndpointType, max_packet_size: u16, interval_ms: u8) -> D::EndpointIn {
+    pub fn alloc_endpoint_in(
+        &mut self,
+        ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
+        max_packet_size: u16,
+        interval_ms: u8,
+    ) -> D::EndpointIn {
         let ep = self
             .builder
             .driver
-            .alloc_endpoint_in(ep_type, max_packet_size, interval_ms)
+            .alloc_endpoint_in(ep_type, ep_addr, max_packet_size, interval_ms)
             .expect("alloc_endpoint_in failed");
 
         ep
@@ -478,13 +484,14 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     fn endpoint_in(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
         synchronization_type: SynchronizationType,
         usage_type: UsageType,
         extra_fields: &[u8],
     ) -> D::EndpointIn {
-        let ep = self.alloc_endpoint_in(ep_type, max_packet_size, interval_ms);
+        let ep = self.alloc_endpoint_in(ep_type, ep_addr, max_packet_size, interval_ms);
         self.endpoint_descriptor(ep.info(), synchronization_type, usage_type, extra_fields);
 
         ep
@@ -496,13 +503,14 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     pub fn alloc_endpoint_out(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> D::EndpointOut {
         let ep = self
             .builder
             .driver
-            .alloc_endpoint_out(ep_type, max_packet_size, interval_ms)
+            .alloc_endpoint_out(ep_type, ep_addr, max_packet_size, interval_ms)
             .expect("alloc_endpoint_out failed");
 
         ep
@@ -511,13 +519,14 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     fn endpoint_out(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
         synchronization_type: SynchronizationType,
         usage_type: UsageType,
         extra_fields: &[u8],
     ) -> D::EndpointOut {
-        let ep = self.alloc_endpoint_out(ep_type, max_packet_size, interval_ms);
+        let ep = self.alloc_endpoint_out(ep_type, ep_addr, max_packet_size, interval_ms);
         self.endpoint_descriptor(ep.info(), synchronization_type, usage_type, extra_fields);
 
         ep
@@ -527,9 +536,10 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     ///
     /// Descriptors are written in the order builder functions are called. Note that some
     /// classes care about the order.
-    pub fn endpoint_bulk_in(&mut self, max_packet_size: u16) -> D::EndpointIn {
+    pub fn endpoint_bulk_in(&mut self, ep_addr: Option<EndpointAddress>, max_packet_size: u16) -> D::EndpointIn {
         self.endpoint_in(
             EndpointType::Bulk,
+            ep_addr,
             max_packet_size,
             0,
             SynchronizationType::NoSynchronization,
@@ -542,9 +552,10 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     ///
     /// Descriptors are written in the order builder functions are called. Note that some
     /// classes care about the order.
-    pub fn endpoint_bulk_out(&mut self, max_packet_size: u16) -> D::EndpointOut {
+    pub fn endpoint_bulk_out(&mut self, ep_addr: Option<EndpointAddress>, max_packet_size: u16) -> D::EndpointOut {
         self.endpoint_out(
             EndpointType::Bulk,
+            ep_addr,
             max_packet_size,
             0,
             SynchronizationType::NoSynchronization,
@@ -557,9 +568,15 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     ///
     /// Descriptors are written in the order builder functions are called. Note that some
     /// classes care about the order.
-    pub fn endpoint_interrupt_in(&mut self, max_packet_size: u16, interval_ms: u8) -> D::EndpointIn {
+    pub fn endpoint_interrupt_in(
+        &mut self,
+        ep_addr: Option<EndpointAddress>,
+        max_packet_size: u16,
+        interval_ms: u8,
+    ) -> D::EndpointIn {
         self.endpoint_in(
             EndpointType::Interrupt,
+            ep_addr,
             max_packet_size,
             interval_ms,
             SynchronizationType::NoSynchronization,
@@ -569,9 +586,15 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     }
 
     /// Allocate a INTERRUPT OUT endpoint and write its descriptor.
-    pub fn endpoint_interrupt_out(&mut self, max_packet_size: u16, interval_ms: u8) -> D::EndpointOut {
+    pub fn endpoint_interrupt_out(
+        &mut self,
+        ep_addr: Option<EndpointAddress>,
+        max_packet_size: u16,
+        interval_ms: u8,
+    ) -> D::EndpointOut {
         self.endpoint_out(
             EndpointType::Interrupt,
+            ep_addr,
             max_packet_size,
             interval_ms,
             SynchronizationType::NoSynchronization,
@@ -586,6 +609,7 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     /// classes care about the order.
     pub fn endpoint_isochronous_in(
         &mut self,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
         synchronization_type: SynchronizationType,
@@ -594,6 +618,7 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     ) -> D::EndpointIn {
         self.endpoint_in(
             EndpointType::Isochronous,
+            ep_addr,
             max_packet_size,
             interval_ms,
             synchronization_type,
@@ -605,6 +630,7 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     /// Allocate a ISOCHRONOUS OUT endpoint and write its descriptor.
     pub fn endpoint_isochronous_out(
         &mut self,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
         synchronization_type: SynchronizationType,
@@ -613,6 +639,7 @@ impl<'a, 'd, D: Driver<'d>> InterfaceAltBuilder<'a, 'd, D> {
     ) -> D::EndpointOut {
         self.endpoint_out(
             EndpointType::Isochronous,
+            ep_addr,
             max_packet_size,
             interval_ms,
             synchronization_type,
diff --git a/embassy-usb/src/class/cdc_acm.rs b/embassy-usb/src/class/cdc_acm.rs
index 732a433f8..0a1a5e64f 100644
--- a/embassy-usb/src/class/cdc_acm.rs
+++ b/embassy-usb/src/class/cdc_acm.rs
@@ -254,14 +254,14 @@ impl<'d, D: Driver<'d>> CdcAcmClass<'d, D> {
             ],
         );
 
-        let comm_ep = alt.endpoint_interrupt_in(8, 255);
+        let comm_ep = alt.endpoint_interrupt_in(None, 8, 255);
 
         // Data interface
         let mut iface = func.interface();
         let data_if = iface.interface_number();
         let mut alt = iface.alt_setting(USB_CLASS_CDC_DATA, 0x00, CDC_PROTOCOL_NONE, None);
-        let read_ep = alt.endpoint_bulk_out(max_packet_size);
-        let write_ep = alt.endpoint_bulk_in(max_packet_size);
+        let read_ep = alt.endpoint_bulk_out(None, max_packet_size);
+        let write_ep = alt.endpoint_bulk_in(None, max_packet_size);
 
         drop(func);
 
@@ -501,7 +501,7 @@ impl<'d, D: Driver<'d>> BufferedReceiver<'d, D> {
     fn read_from_buffer(&mut self, buf: &mut [u8]) -> usize {
         let available = &self.buffer[self.start..self.end];
         let len = core::cmp::min(available.len(), buf.len());
-        buf[..len].copy_from_slice(&self.buffer[..len]);
+        buf[..len].copy_from_slice(&available[..len]);
         self.start += len;
         len
     }
diff --git a/embassy-usb/src/class/cdc_ncm/mod.rs b/embassy-usb/src/class/cdc_ncm/mod.rs
index 09d923d2a..3af853091 100644
--- a/embassy-usb/src/class/cdc_ncm/mod.rs
+++ b/embassy-usb/src/class/cdc_ncm/mod.rs
@@ -313,15 +313,15 @@ impl<'d, D: Driver<'d>> CdcNcmClass<'d, D> {
             ],
         );
 
-        let comm_ep = alt.endpoint_interrupt_in(8, 255);
+        let comm_ep = alt.endpoint_interrupt_in(None, 8, 255);
 
         // Data interface
         let mut iface = func.interface();
         let data_if = iface.interface_number();
         let _alt = iface.alt_setting(USB_CLASS_CDC_DATA, 0x00, CDC_PROTOCOL_NTB, None);
         let mut alt = iface.alt_setting(USB_CLASS_CDC_DATA, 0x00, CDC_PROTOCOL_NTB, None);
-        let read_ep = alt.endpoint_bulk_out(max_packet_size);
-        let write_ep = alt.endpoint_bulk_in(max_packet_size);
+        let read_ep = alt.endpoint_bulk_out(None, max_packet_size);
+        let write_ep = alt.endpoint_bulk_in(None, max_packet_size);
 
         drop(func);
 
diff --git a/embassy-usb/src/class/cmsis_dap_v2.rs b/embassy-usb/src/class/cmsis_dap_v2.rs
index a94e3ddb7..a9fd9cdf0 100644
--- a/embassy-usb/src/class/cmsis_dap_v2.rs
+++ b/embassy-usb/src/class/cmsis_dap_v2.rs
@@ -61,10 +61,10 @@ impl<'d, D: Driver<'d>> CmsisDapV2Class<'d, D> {
         ));
         let mut interface = function.interface();
         let mut alt = interface.alt_setting(0xFF, 0, 0, Some(iface_string));
-        let read_ep = alt.endpoint_bulk_out(max_packet_size);
-        let write_ep = alt.endpoint_bulk_in(max_packet_size);
+        let read_ep = alt.endpoint_bulk_out(None, max_packet_size);
+        let write_ep = alt.endpoint_bulk_in(None, max_packet_size);
         let trace_ep = if trace {
-            Some(alt.endpoint_bulk_in(max_packet_size))
+            Some(alt.endpoint_bulk_in(None, max_packet_size))
         } else {
             None
         };
diff --git a/embassy-usb/src/class/hid.rs b/embassy-usb/src/class/hid.rs
index 6d9e0aced..182e1f83f 100644
--- a/embassy-usb/src/class/hid.rs
+++ b/embassy-usb/src/class/hid.rs
@@ -133,9 +133,9 @@ fn build<'d, D: Driver<'d>>(
         ],
     );
 
-    let ep_in = alt.endpoint_interrupt_in(config.max_packet_size, config.poll_ms);
+    let ep_in = alt.endpoint_interrupt_in(None, config.max_packet_size, config.poll_ms);
     let ep_out = if with_out_endpoint {
-        Some(alt.endpoint_interrupt_out(config.max_packet_size, config.poll_ms))
+        Some(alt.endpoint_interrupt_out(None, config.max_packet_size, config.poll_ms))
     } else {
         None
     };
diff --git a/embassy-usb/src/class/midi.rs b/embassy-usb/src/class/midi.rs
index 52a96f278..1d152ca44 100644
--- a/embassy-usb/src/class/midi.rs
+++ b/embassy-usb/src/class/midi.rs
@@ -129,14 +129,14 @@ impl<'d, D: Driver<'d>> MidiClass<'d, D> {
         for i in 0..n_out_jacks {
             endpoint_data[2 + i as usize] = in_jack_id_emb(i);
         }
-        let read_ep = alt.endpoint_bulk_out(max_packet_size);
+        let read_ep = alt.endpoint_bulk_out(None, max_packet_size);
         alt.descriptor(CS_ENDPOINT, &endpoint_data[0..2 + n_out_jacks as usize]);
 
         endpoint_data[1] = n_in_jacks;
         for i in 0..n_in_jacks {
             endpoint_data[2 + i as usize] = out_jack_id_emb(i);
         }
-        let write_ep = alt.endpoint_bulk_in(max_packet_size);
+        let write_ep = alt.endpoint_bulk_in(None, max_packet_size);
         alt.descriptor(CS_ENDPOINT, &endpoint_data[0..2 + n_in_jacks as usize]);
 
         MidiClass { read_ep, write_ep }
diff --git a/embassy-usb/src/class/uac1/speaker.rs b/embassy-usb/src/class/uac1/speaker.rs
index 1ff29088c..9565e2a25 100644
--- a/embassy-usb/src/class/uac1/speaker.rs
+++ b/embassy-usb/src/class/uac1/speaker.rs
@@ -268,9 +268,10 @@ impl<'d, D: Driver<'d>> Speaker<'d, D> {
 
         alt.descriptor(CS_INTERFACE, &format_descriptor);
 
-        let streaming_endpoint = alt.alloc_endpoint_out(EndpointType::Isochronous, max_packet_size, 1);
+        let streaming_endpoint = alt.alloc_endpoint_out(EndpointType::Isochronous, None, max_packet_size, 1);
         let feedback_endpoint = alt.alloc_endpoint_in(
             EndpointType::Isochronous,
+            None,
             4, // Feedback packets are 24 bit (10.14 format).
             1,
         );
diff --git a/embassy-usb/src/class/web_usb.rs b/embassy-usb/src/class/web_usb.rs
index 405944f14..154b219ca 100644
--- a/embassy-usb/src/class/web_usb.rs
+++ b/embassy-usb/src/class/web_usb.rs
@@ -84,7 +84,7 @@ impl<'d> Control<'d> {
 }
 
 impl<'d> Handler for Control<'d> {
-    fn control_in(&mut self, req: Request, _data: &mut [u8]) -> Option<InResponse> {
+    fn control_in(&mut self, req: Request, _data: &mut [u8]) -> Option<InResponse<'_>> {
         let landing_value = if self.landing_url.is_some() { 1 } else { 0 };
         if req.request_type == RequestType::Vendor
             && req.recipient == Recipient::Device
diff --git a/examples/boot/application/nrf/Cargo.toml b/examples/boot/application/nrf/Cargo.toml
index 4d633e8a8..37183df97 100644
--- a/examples/boot/application/nrf/Cargo.toml
+++ b/examples/boot/application/nrf/Cargo.toml
@@ -8,10 +8,10 @@ license = "MIT OR Apache-2.0"
 embassy-sync = { version = "0.7.0", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.7.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.4.0", path = "../../../../embassy-time", features = [] }
-embassy-nrf = { version = "0.3.1", path = "../../../../embassy-nrf", features = ["time-driver-rtc1", "gpiote", ] }
-embassy-boot = { version = "0.4.0", path = "../../../../embassy-boot", features = [] }
-embassy-boot-nrf = { version = "0.4.0", path = "../../../../embassy-boot-nrf", features = [] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../../../embassy-embedded-hal" }
+embassy-nrf = { version = "0.5.0", path = "../../../../embassy-nrf", features = ["time-driver-rtc1", "gpiote", ] }
+embassy-boot = { version = "0.5.0", path = "../../../../embassy-boot", features = [] }
+embassy-boot-nrf = { version = "0.6.0", path = "../../../../embassy-boot-nrf", features = [] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../../../embassy-embedded-hal" }
 
 defmt = { version = "1.0.1", optional = true }
 defmt-rtt = { version = "1.0.0", optional = true }
diff --git a/examples/boot/application/rp/Cargo.toml b/examples/boot/application/rp/Cargo.toml
index be283fb27..e5568f6bb 100644
--- a/examples/boot/application/rp/Cargo.toml
+++ b/examples/boot/application/rp/Cargo.toml
@@ -8,9 +8,9 @@ license = "MIT OR Apache-2.0"
 embassy-sync = { version = "0.7.0", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.7.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.4.0", path = "../../../../embassy-time", features = [] }
-embassy-rp = { version = "0.4.0", path = "../../../../embassy-rp", features = ["time-driver", "rp2040"] }
-embassy-boot-rp = { version = "0.5.0", path = "../../../../embassy-boot-rp", features = [] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../../../embassy-embedded-hal" }
+embassy-rp = { version = "0.6.0", path = "../../../../embassy-rp", features = ["time-driver", "rp2040"] }
+embassy-boot-rp = { version = "0.6.0", path = "../../../../embassy-boot-rp", features = [] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../../../embassy-embedded-hal" }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/boot/application/rp/src/bin/a.rs b/examples/boot/application/rp/src/bin/a.rs
index ede0c07da..e6d7b3d4f 100644
--- a/examples/boot/application/rp/src/bin/a.rs
+++ b/examples/boot/application/rp/src/bin/a.rs
@@ -54,7 +54,7 @@ async fn main(_s: Spawner) {
     for chunk in APP_B.chunks(4096) {
         buf.0[..chunk.len()].copy_from_slice(chunk);
         defmt::info!("writing block at offset {}", offset);
-        writer.write(offset, &buf.0[..]).unwrap();
+        writer.write(offset, &buf.0[..chunk.len()]).unwrap();
         offset += chunk.len() as u32;
     }
     watchdog.feed();
diff --git a/examples/boot/application/stm32f3/Cargo.toml b/examples/boot/application/stm32f3/Cargo.toml
index b3466e288..be8b7bff1 100644
--- a/examples/boot/application/stm32f3/Cargo.toml
+++ b/examples/boot/application/stm32f3/Cargo.toml
@@ -9,8 +9,8 @@ embassy-sync = { version = "0.7.0", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.7.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.4.0", path = "../../../../embassy-time", features = [ "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.2.0", path = "../../../../embassy-stm32", features = ["stm32f303re", "time-driver-any", "exti"]  }
-embassy-boot-stm32 = { version = "0.3.0", path = "../../../../embassy-boot-stm32" }
-embassy-embedded-hal = { version = "0.3.0", path = "../../../../embassy-embedded-hal" }
+embassy-boot-stm32 = { version = "0.4.0", path = "../../../../embassy-boot-stm32" }
+embassy-embedded-hal = { version = "0.3.1", path = "../../../../embassy-embedded-hal" }
 
 defmt = { version = "1.0.1", optional = true }
 defmt-rtt = { version = "1.0.0", optional = true }
diff --git a/examples/boot/application/stm32f7/Cargo.toml b/examples/boot/application/stm32f7/Cargo.toml
index 72dbded5f..2b0175a0c 100644
--- a/examples/boot/application/stm32f7/Cargo.toml
+++ b/examples/boot/application/stm32f7/Cargo.toml
@@ -9,8 +9,8 @@ embassy-sync = { version = "0.7.0", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.7.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.4.0", path = "../../../../embassy-time", features = [ "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.2.0", path = "../../../../embassy-stm32", features = ["stm32f767zi", "time-driver-any", "exti", "single-bank"]  }
-embassy-boot-stm32 = { version = "0.3.0", path = "../../../../embassy-boot-stm32", features = [] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../../../embassy-embedded-hal" }
+embassy-boot-stm32 = { version = "0.4.0", path = "../../../../embassy-boot-stm32", features = [] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../../../embassy-embedded-hal" }
 
 defmt = { version = "1.0.1", optional = true }
 defmt-rtt = { version = "1.0.0", optional = true }
diff --git a/examples/boot/application/stm32h7/Cargo.toml b/examples/boot/application/stm32h7/Cargo.toml
index 57fb8312c..3c88f4241 100644
--- a/examples/boot/application/stm32h7/Cargo.toml
+++ b/examples/boot/application/stm32h7/Cargo.toml
@@ -9,8 +9,8 @@ embassy-sync = { version = "0.7.0", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.7.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.4.0", path = "../../../../embassy-time", features = [ "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.2.0", path = "../../../../embassy-stm32", features = ["stm32h743zi", "time-driver-any", "exti"]  }
-embassy-boot-stm32 = { version = "0.3.0", path = "../../../../embassy-boot-stm32", features = [] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../../../embassy-embedded-hal" }
+embassy-boot-stm32 = { version = "0.4.0", path = "../../../../embassy-boot-stm32", features = [] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../../../embassy-embedded-hal" }
 
 defmt = { version = "1.0.1", optional = true }
 defmt-rtt = { version = "1.0.0", optional = true }
diff --git a/examples/boot/application/stm32l0/Cargo.toml b/examples/boot/application/stm32l0/Cargo.toml
index 7dbbba138..b4e7e090a 100644
--- a/examples/boot/application/stm32l0/Cargo.toml
+++ b/examples/boot/application/stm32l0/Cargo.toml
@@ -9,8 +9,8 @@ embassy-sync = { version = "0.7.0", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.7.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.4.0", path = "../../../../embassy-time", features = [ "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.2.0", path = "../../../../embassy-stm32", features = ["stm32l072cz", "time-driver-any", "exti", "memory-x"]  }
-embassy-boot-stm32 = { version = "0.3.0", path = "../../../../embassy-boot-stm32", features = [] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../../../embassy-embedded-hal" }
+embassy-boot-stm32 = { version = "0.4.0", path = "../../../../embassy-boot-stm32", features = [] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../../../embassy-embedded-hal" }
 
 defmt = { version = "1.0.1", optional = true }
 defmt-rtt = { version = "1.0.0", optional = true }
diff --git a/examples/boot/application/stm32l1/Cargo.toml b/examples/boot/application/stm32l1/Cargo.toml
index 9549b2048..394578e1a 100644
--- a/examples/boot/application/stm32l1/Cargo.toml
+++ b/examples/boot/application/stm32l1/Cargo.toml
@@ -9,8 +9,8 @@ embassy-sync = { version = "0.7.0", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.7.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.4.0", path = "../../../../embassy-time", features = [ "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.2.0", path = "../../../../embassy-stm32", features = ["stm32l151cb-a", "time-driver-any", "exti"]  }
-embassy-boot-stm32 = { version = "0.3.0", path = "../../../../embassy-boot-stm32", features = [] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../../../embassy-embedded-hal" }
+embassy-boot-stm32 = { version = "0.4.0", path = "../../../../embassy-boot-stm32", features = [] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../../../embassy-embedded-hal" }
 
 defmt = { version = "1.0.1", optional = true }
 defmt-rtt = { version = "1.0.0", optional = true }
diff --git a/examples/boot/application/stm32l4/Cargo.toml b/examples/boot/application/stm32l4/Cargo.toml
index 03daeb0bc..abe0451fd 100644
--- a/examples/boot/application/stm32l4/Cargo.toml
+++ b/examples/boot/application/stm32l4/Cargo.toml
@@ -9,8 +9,8 @@ embassy-sync = { version = "0.7.0", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.7.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.4.0", path = "../../../../embassy-time", features = [ "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.2.0", path = "../../../../embassy-stm32", features = ["stm32l475vg", "time-driver-any", "exti"]  }
-embassy-boot-stm32 = { version = "0.3.0", path = "../../../../embassy-boot-stm32", features = [] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../../../embassy-embedded-hal" }
+embassy-boot-stm32 = { version = "0.4.0", path = "../../../../embassy-boot-stm32", features = [] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../../../embassy-embedded-hal" }
 
 defmt = { version = "1.0.1", optional = true }
 defmt-rtt = { version = "1.0.0", optional = true }
diff --git a/examples/boot/application/stm32wb-dfu/Cargo.toml b/examples/boot/application/stm32wb-dfu/Cargo.toml
index e582628aa..bc4681f79 100644
--- a/examples/boot/application/stm32wb-dfu/Cargo.toml
+++ b/examples/boot/application/stm32wb-dfu/Cargo.toml
@@ -9,9 +9,9 @@ embassy-sync = { version = "0.7.0", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.7.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.4.0", path = "../../../../embassy-time", features = [ "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.2.0", path = "../../../../embassy-stm32", features = ["stm32wb55rg", "time-driver-any", "exti"]  }
-embassy-boot-stm32 = { version = "0.3.0", path = "../../../../embassy-boot-stm32", features = [] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../../../embassy-embedded-hal" }
-embassy-usb = { version = "0.4.0", path = "../../../../embassy-usb" }
+embassy-boot-stm32 = { version = "0.4.0", path = "../../../../embassy-boot-stm32", features = [] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../../../embassy-embedded-hal" }
+embassy-usb = { version = "0.5.0", path = "../../../../embassy-usb" }
 embassy-usb-dfu = { version = "0.1.0", path = "../../../../embassy-usb-dfu", features = ["application", "cortex-m"] }
 
 defmt = { version = "1.0.1", optional = true }
diff --git a/examples/boot/application/stm32wl/Cargo.toml b/examples/boot/application/stm32wl/Cargo.toml
index 3ed04b472..0552d109a 100644
--- a/examples/boot/application/stm32wl/Cargo.toml
+++ b/examples/boot/application/stm32wl/Cargo.toml
@@ -9,8 +9,8 @@ embassy-sync = { version = "0.7.0", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.7.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.4.0", path = "../../../../embassy-time", features = [ "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.2.0", path = "../../../../embassy-stm32", features = ["stm32wl55jc-cm4", "time-driver-any", "exti"]  }
-embassy-boot-stm32 = { version = "0.3.0", path = "../../../../embassy-boot-stm32", features = [] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../../../embassy-embedded-hal" }
+embassy-boot-stm32 = { version = "0.4.0", path = "../../../../embassy-boot-stm32", features = [] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../../../embassy-embedded-hal" }
 
 defmt = { version = "1.0.1", optional = true }
 defmt-rtt = { version = "1.0.0", optional = true }
diff --git a/examples/boot/bootloader/stm32wb-dfu/Cargo.toml b/examples/boot/bootloader/stm32wb-dfu/Cargo.toml
index 0bb93b12e..d101e6ace 100644
--- a/examples/boot/bootloader/stm32wb-dfu/Cargo.toml
+++ b/examples/boot/bootloader/stm32wb-dfu/Cargo.toml
@@ -18,7 +18,7 @@ embedded-storage = "0.3.1"
 embedded-storage-async = "0.4.0"
 cfg-if = "1.0.0"
 embassy-usb-dfu = { version = "0.1.0", path = "../../../../embassy-usb-dfu", features = ["dfu", "cortex-m"] }
-embassy-usb = { version = "0.4.0", path = "../../../../embassy-usb", default-features = false }
+embassy-usb = { version = "0.5.0", path = "../../../../embassy-usb", default-features = false }
 embassy-futures = { version = "0.1.1", path = "../../../../embassy-futures" }
 
 [features]
diff --git a/examples/lpc55s69/Cargo.toml b/examples/lpc55s69/Cargo.toml
index 7f81e9c7f..1724a22d4 100644
--- a/examples/lpc55s69/Cargo.toml
+++ b/examples/lpc55s69/Cargo.toml
@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 
 [dependencies]
-embassy-nxp = { version = "0.1.0", path = "../../embassy-nxp", features = ["rt"] }
+embassy-nxp = { version = "0.1.0", path = "../../embassy-nxp", features = ["lpc55", "rt", "defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt"] }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt"] }
diff --git a/examples/mimxrt1011/.cargo/config.toml b/examples/mimxrt1011/.cargo/config.toml
new file mode 100644
index 000000000..12f4b27b2
--- /dev/null
+++ b/examples/mimxrt1011/.cargo/config.toml
@@ -0,0 +1,8 @@
+[target.thumbv7em-none-eabihf]
+runner = 'probe-rs run --chip MIMXRT1010'
+
+[build]
+target = "thumbv7em-none-eabihf" # Cortex-M7
+
+[env]
+DEFMT_LOG = "trace"
diff --git a/examples/mimxrt1011/Cargo.toml b/examples/mimxrt1011/Cargo.toml
new file mode 100644
index 000000000..cf4e4c163
--- /dev/null
+++ b/examples/mimxrt1011/Cargo.toml
@@ -0,0 +1,29 @@
+[package]
+name = "embassy-imxrt1011-examples"
+version = "0.1.0"
+edition = "2021"
+license = "MIT or Apache-2.0"
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.3"
+defmt = "1.0.1"
+defmt-rtt = "1.0.0"
+
+embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
+embassy-futures = { version = "0.1.1", path = "../../embassy-futures" }
+embassy-nxp = { version = "0.1.0", path = "../../embassy-nxp", features = ["defmt", "mimxrt1011", "unstable-pac", "time-driver-pit"] }
+embassy-time = { version = "0.4", path = "../../embassy-time", features = ["defmt", ] } # "defmt-timestamp-uptime" # RT1011 hard faults currently with this enabled.
+embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
+embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
+embedded-hal-async = "1.0.0"
+
+imxrt-boot-gen = { version = "0.3.4", features = ["imxrt1010"] }
+panic-probe = { version = "1.0.0", features = ["print-defmt"] }
+panic-semihosting = "0.6.0"
+
+[build-dependencies]
+imxrt-rt = { version = "0.1.7", features = ["device"] }
+
+[profile.release]
+debug = 2
diff --git a/examples/mimxrt1011/build.rs b/examples/mimxrt1011/build.rs
new file mode 100644
index 000000000..99e172aba
--- /dev/null
+++ b/examples/mimxrt1011/build.rs
@@ -0,0 +1,14 @@
+use imxrt_rt::{Family, RuntimeBuilder};
+
+fn main() {
+    // The IMXRT1010-EVK technically has 128M of flash, but we only ever use 8MB so that the examples
+    // will build fine on the Adafruit Metro M7 boards.
+    RuntimeBuilder::from_flexspi(Family::Imxrt1010, 8 * 1024 * 1024)
+        .build()
+        .unwrap();
+
+    println!("cargo:rustc-link-arg-bins=--nmagic");
+    println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
+    // Not link.x, as imxrt-rt needs to do some special things
+    println!("cargo:rustc-link-arg-bins=-Timxrt-link.x");
+}
diff --git a/examples/mimxrt1011/src/bin/blinky.rs b/examples/mimxrt1011/src/bin/blinky.rs
new file mode 100644
index 000000000..a5d5de6b3
--- /dev/null
+++ b/examples/mimxrt1011/src/bin/blinky.rs
@@ -0,0 +1,48 @@
+//! This example works on the following boards:
+//! - IMXRT1010-EVK
+//! - Adafruit Metro M7 (with microSD or with AirLift), requires an external button
+//! - Makerdiary iMX RT1011 Nano Kit (TODO: currently untested, please change this)
+//!
+//! Although beware you will need to change the GPIO pins being used (scroll down).
+
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_nxp::gpio::{Level, Output};
+use embassy_time::Timer;
+// Must include `embassy_imxrt1011_examples` to ensure the FCB gets linked.
+use {defmt_rtt as _, embassy_imxrt1011_examples as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+    let p = embassy_nxp::init(Default::default());
+    info!("Hello world!");
+
+    /* Pick the pins to use depending on your board. */
+
+    // IMXRT1010-EVK
+    //
+    // LED (D25)
+    let led = p.GPIO_11;
+
+    // Adafruit Metro M7 (both microSD and AirLift variants)
+    //
+    // The LED is connected to D13 on the board.
+    // let led = p.GPIO_03;
+
+    // Makerdiary iMX RT1011 Nano Kit
+    //
+    // LED0
+    // let led = p.GPIO_SD_04;
+
+    let mut led = Output::new(led, Level::Low);
+
+    loop {
+        Timer::after_millis(500).await;
+
+        info!("Toggle");
+        led.toggle();
+    }
+}
diff --git a/examples/mimxrt1011/src/bin/button.rs b/examples/mimxrt1011/src/bin/button.rs
new file mode 100644
index 000000000..e63d7171d
--- /dev/null
+++ b/examples/mimxrt1011/src/bin/button.rs
@@ -0,0 +1,62 @@
+//! This example works on the following boards:
+//! - IMXRT1010-EVK
+//! - Adafruit Metro M7 (with microSD or with AirLift), requires an external button
+//! - Makerdiary iMX RT1011 Nano Kit (TODO: currently untested, please change this)
+//!
+//! Although beware you will need to change the GPIO pins being used (scroll down).
+
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_nxp::gpio::{Input, Level, Output, Pull};
+// Must include `embassy_imxrt1011_examples` to ensure the FCB gets linked.
+use {defmt_rtt as _, embassy_imxrt1011_examples as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+    let p = embassy_nxp::init(Default::default());
+    info!("Hello world!");
+
+    /* Pick the pins to use depending on your board. */
+
+    // IMXRT1010-EVK
+    //
+    // LED (D25) and user button (SW4)
+    let (led, button) = (p.GPIO_11, p.GPIO_SD_05);
+
+    // Adafruit Metro M7 (both microSD and AirLift variants)
+    //
+    // The LED is connected to D13 on the board.
+    //
+    // In particular the Metro M7 has no board user buttons, so you will need to connect a button.
+    // Any other GPIO pin can be used. GPIO_04 is used for example since it is on pin D12.
+    // let (led, button) = (p.GPIO_03, p.GPIO_04);
+
+    // Makerdiary iMX RT1011 Nano Kit
+    //
+    // LED0 and user button.
+    // let (led, button) = (p.GPIO_SD_04, p.GPIO_SD_03);
+
+    let mut button = Input::new(button, Pull::Up100K);
+    let mut led = Output::new(led, Level::Low);
+    led.set_high();
+
+    loop {
+        button.wait_for_falling_edge().await;
+
+        info!("Toggled");
+        led.toggle();
+
+        // The RT1010EVK has a 100 nF debouncing capacitor which results in false positive events
+        // when listening for a falling edge in a loop, wait for the rising edge and then wait for
+        // stabilization.
+        button.wait_for_rising_edge().await;
+
+        // Stabilization.
+        for _ in 0..100_000 {
+            cortex_m::asm::nop();
+        }
+    }
+}
diff --git a/examples/mimxrt1011/src/lib.rs b/examples/mimxrt1011/src/lib.rs
new file mode 100644
index 000000000..f0391ef57
--- /dev/null
+++ b/examples/mimxrt1011/src/lib.rs
@@ -0,0 +1,75 @@
+//! FlexSPI configuration block (FCB) for iMXRT1011 boards.
+//!
+//! This is a generic FCB that should work with most QSPI flash.
+
+#![no_std]
+
+use imxrt_boot_gen::flexspi;
+use imxrt_boot_gen::flexspi::opcodes::sdr::*;
+use imxrt_boot_gen::flexspi::{
+    ColumnAddressWidth, Command, DeviceModeConfiguration, FlashPadType, Instr, LookupTable, Pads,
+    ReadSampleClockSource, Sequence, SequenceBuilder, SerialClockFrequency, SerialFlashRegion,
+    WaitTimeConfigurationCommands,
+};
+use imxrt_boot_gen::serial_flash::nor;
+
+/// While the IMXRT1010-EVK and Makerdiary iMX RT1011 Nano Kit have 128MBit of flash we limit to 64Mbit
+/// to allow the Metro M7 boards to use the same FCB configuration.
+const DENSITY_BITS: u32 = 64 * 1024 * 1024;
+const DENSITY_BYTES: u32 = DENSITY_BITS / 8;
+
+const SEQ_READ: Sequence = SequenceBuilder::new()
+    .instr(Instr::new(CMD, Pads::One, 0xEB))
+    .instr(Instr::new(RADDR, Pads::Four, 0x18))
+    .instr(Instr::new(DUMMY, Pads::Four, 0x06))
+    .instr(Instr::new(READ, Pads::Four, 0x04))
+    .build();
+
+const SEQ_READ_STATUS: Sequence = SequenceBuilder::new()
+    .instr(Instr::new(CMD, Pads::One, 0x05))
+    .instr(Instr::new(READ, Pads::One, 0x01))
+    .build();
+
+const SEQ_WRITE_ENABLE: Sequence = SequenceBuilder::new().instr(Instr::new(CMD, Pads::One, 0x06)).build();
+
+const SEQ_ERASE_SECTOR: Sequence = SequenceBuilder::new()
+    .instr(Instr::new(CMD, Pads::One, 0x20))
+    .instr(Instr::new(RADDR, Pads::One, 0x18))
+    .build();
+
+const SEQ_PAGE_PROGRAM: Sequence = SequenceBuilder::new()
+    .instr(Instr::new(CMD, Pads::One, 0x02))
+    .instr(Instr::new(RADDR, Pads::One, 0x18))
+    .instr(Instr::new(WRITE, Pads::One, 0x04))
+    .build();
+
+const SEQ_CHIP_ERASE: Sequence = SequenceBuilder::new().instr(Instr::new(CMD, Pads::One, 0x60)).build();
+
+const LUT: LookupTable = LookupTable::new()
+    .command(Command::Read, SEQ_READ)
+    .command(Command::ReadStatus, SEQ_READ_STATUS)
+    .command(Command::WriteEnable, SEQ_WRITE_ENABLE)
+    .command(Command::EraseSector, SEQ_ERASE_SECTOR)
+    .command(Command::PageProgram, SEQ_PAGE_PROGRAM)
+    .command(Command::ChipErase, SEQ_CHIP_ERASE);
+
+const COMMON_CONFIGURATION_BLOCK: flexspi::ConfigurationBlock = flexspi::ConfigurationBlock::new(LUT)
+    .read_sample_clk_src(ReadSampleClockSource::LoopbackFromDQSPad)
+    .cs_hold_time(0x03)
+    .cs_setup_time(0x03)
+    .column_address_width(ColumnAddressWidth::OtherDevices)
+    .device_mode_configuration(DeviceModeConfiguration::Disabled)
+    .wait_time_cfg_commands(WaitTimeConfigurationCommands::disable())
+    .flash_size(SerialFlashRegion::A1, DENSITY_BYTES)
+    .serial_clk_freq(SerialClockFrequency::MHz120)
+    .serial_flash_pad_type(FlashPadType::Quad);
+
+pub const SERIAL_NOR_CONFIGURATION_BLOCK: nor::ConfigurationBlock =
+    nor::ConfigurationBlock::new(COMMON_CONFIGURATION_BLOCK)
+        .page_size(256)
+        .sector_size(4096)
+        .ip_cmd_serial_clk_freq(nor::SerialClockFrequency::MHz30);
+
+#[unsafe(no_mangle)]
+#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".fcb")]
+pub static FLEXSPI_CONFIGURATION_BLOCK: nor::ConfigurationBlock = SERIAL_NOR_CONFIGURATION_BLOCK;
diff --git a/examples/mimxrt1062-evk/.cargo/config.toml b/examples/mimxrt1062-evk/.cargo/config.toml
new file mode 100644
index 000000000..ca4c606dc
--- /dev/null
+++ b/examples/mimxrt1062-evk/.cargo/config.toml
@@ -0,0 +1,8 @@
+[target.thumbv7em-none-eabihf]
+runner = 'probe-rs run --chip MIMXRT1060'
+
+[build]
+target = "thumbv7em-none-eabihf" # Cortex-M7
+
+[env]
+DEFMT_LOG = "trace"
diff --git a/examples/mimxrt1062-evk/Cargo.toml b/examples/mimxrt1062-evk/Cargo.toml
new file mode 100644
index 000000000..430a26b41
--- /dev/null
+++ b/examples/mimxrt1062-evk/Cargo.toml
@@ -0,0 +1,29 @@
+[package]
+name = "embassy-imxrt1062-evk-examples"
+version = "0.1.0"
+edition = "2021"
+license = "MIT or Apache-2.0"
+
+[dependencies]
+cortex-m = { version = "0.7.7", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.3"
+defmt = "1.0.1"
+defmt-rtt = "1.0.0"
+
+embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
+embassy-futures = { version = "0.1.1", path = "../../embassy-futures" }
+embassy-nxp = { version = "0.1.0", path = "../../embassy-nxp", features = ["defmt", "mimxrt1062", "unstable-pac", "time-driver-pit"] }
+embassy-time = { version = "0.4", path = "../../embassy-time", features = ["defmt", ] } # "defmt-timestamp-uptime"
+embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
+embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
+embedded-hal-async = "1.0.0"
+
+imxrt-boot-gen = { version = "0.3.4", features = ["imxrt1060"] }
+panic-probe = { version = "1.0.0", features = ["print-defmt"] }
+panic-semihosting = "0.6.0"
+
+[build-dependencies]
+imxrt-rt = { version = "0.1.7", features = ["device"] }
+
+[profile.release]
+debug = 2
diff --git a/examples/mimxrt1062-evk/build.rs b/examples/mimxrt1062-evk/build.rs
new file mode 100644
index 000000000..e0e0d547e
--- /dev/null
+++ b/examples/mimxrt1062-evk/build.rs
@@ -0,0 +1,12 @@
+use imxrt_rt::{Family, RuntimeBuilder};
+
+fn main() {
+    RuntimeBuilder::from_flexspi(Family::Imxrt1060, 8 * 1024 * 1024)
+        .build()
+        .unwrap();
+
+    println!("cargo:rustc-link-arg-bins=--nmagic");
+    println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
+    // Not link.x, as imxrt-rt needs to do some special things
+    println!("cargo:rustc-link-arg-bins=-Timxrt-link.x");
+}
diff --git a/examples/mimxrt1062-evk/src/bin/blinky.rs b/examples/mimxrt1062-evk/src/bin/blinky.rs
new file mode 100644
index 000000000..b6d90d94d
--- /dev/null
+++ b/examples/mimxrt1062-evk/src/bin/blinky.rs
@@ -0,0 +1,25 @@
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_nxp::gpio::{Level, Output};
+use embassy_time::Timer;
+// Must include `embassy_imxrt1062_evk_examples` to ensure the FCB gets linked.
+use {defmt_rtt as _, embassy_imxrt1062_evk_examples as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+    let p = embassy_nxp::init(Default::default());
+    info!("Hello world!");
+
+    let led = p.GPIO_AD_B0_08;
+    let mut led = Output::new(led, Level::Low);
+
+    loop {
+        Timer::after_millis(500).await;
+
+        info!("Toggle");
+        led.toggle();
+    }
+}
diff --git a/examples/mimxrt1062-evk/src/bin/button.rs b/examples/mimxrt1062-evk/src/bin/button.rs
new file mode 100644
index 000000000..d60fa3dac
--- /dev/null
+++ b/examples/mimxrt1062-evk/src/bin/button.rs
@@ -0,0 +1,36 @@
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_nxp::gpio::{Input, Level, Output, Pull};
+use {defmt_rtt as _, embassy_imxrt1062_evk_examples as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+    let p = embassy_nxp::init(Default::default());
+    info!("Hello world!");
+
+    // User LED (D8)
+    let led = p.GPIO_AD_B0_08;
+    // User button (SW5)
+    let button = p.WAKEUP;
+    let mut button = Input::new(button, Pull::Up100K);
+    let mut led = Output::new(led, Level::Low);
+    led.set_high();
+
+    loop {
+        button.wait_for_falling_edge().await;
+
+        info!("Toggled");
+        led.toggle();
+
+        // Software debounce.
+        button.wait_for_rising_edge().await;
+
+        // Stabilization.
+        for _ in 0..100_000 {
+            cortex_m::asm::nop();
+        }
+    }
+}
diff --git a/examples/mimxrt1062-evk/src/lib.rs b/examples/mimxrt1062-evk/src/lib.rs
new file mode 100644
index 000000000..3f99f9db3
--- /dev/null
+++ b/examples/mimxrt1062-evk/src/lib.rs
@@ -0,0 +1,60 @@
+//! FlexSPI configuration block (FCB) for the iMXRT1060-EVK
+//!
+//! This uses IS25WP QuadSPI flash.
+
+#![no_std]
+
+use imxrt_boot_gen::flexspi::opcodes::sdr::*;
+use imxrt_boot_gen::flexspi::{self, FlashPadType, ReadSampleClockSource, SerialClockFrequency, SerialFlashRegion, *};
+use imxrt_boot_gen::serial_flash::*;
+pub use nor::ConfigurationBlock;
+
+const SEQ_READ: Sequence = SequenceBuilder::new()
+    .instr(Instr::new(CMD, Pads::One, 0xEB))
+    .instr(Instr::new(RADDR, Pads::Four, 0x18))
+    .instr(Instr::new(DUMMY, Pads::Four, 0x06))
+    .instr(Instr::new(READ, Pads::Four, 0x04))
+    .build();
+const SEQ_READ_STATUS: Sequence = SequenceBuilder::new()
+    .instr(Instr::new(CMD, Pads::One, 0x05))
+    .instr(Instr::new(READ, Pads::One, 0x04))
+    .build();
+const SEQ_WRITE_ENABLE: Sequence = SequenceBuilder::new().instr(Instr::new(CMD, Pads::One, 0x06)).build();
+const SEQ_ERASE_SECTOR: Sequence = SequenceBuilder::new()
+    .instr(Instr::new(CMD, Pads::One, 0x20))
+    .instr(Instr::new(RADDR, Pads::One, 0x18))
+    .build();
+const SEQ_PAGE_PROGRAM: Sequence = SequenceBuilder::new()
+    .instr(Instr::new(CMD, Pads::One, 0x02))
+    .instr(Instr::new(RADDR, Pads::One, 0x18))
+    .instr(Instr::new(WRITE, Pads::One, 0x04))
+    .build();
+const SEQ_CHIP_ERASE: Sequence = SequenceBuilder::new().instr(Instr::new(CMD, Pads::One, 0x60)).build();
+
+const LUT: LookupTable = LookupTable::new()
+    .command(Command::Read, SEQ_READ)
+    .command(Command::ReadStatus, SEQ_READ_STATUS)
+    .command(Command::WriteEnable, SEQ_WRITE_ENABLE)
+    .command(Command::EraseSector, SEQ_ERASE_SECTOR)
+    .command(Command::PageProgram, SEQ_PAGE_PROGRAM)
+    .command(Command::ChipErase, SEQ_CHIP_ERASE);
+
+const COMMON_CONFIGURATION_BLOCK: flexspi::ConfigurationBlock = flexspi::ConfigurationBlock::new(LUT)
+    .version(Version::new(1, 4, 0))
+    .read_sample_clk_src(ReadSampleClockSource::LoopbackFromDQSPad)
+    .cs_hold_time(3)
+    .cs_setup_time(3)
+    .controller_misc_options(0x10)
+    .serial_flash_pad_type(FlashPadType::Quad)
+    .serial_clk_freq(SerialClockFrequency::MHz133)
+    .flash_size(SerialFlashRegion::A1, 8 * 1024 * 1024);
+
+pub const SERIAL_NOR_CONFIGURATION_BLOCK: nor::ConfigurationBlock =
+    nor::ConfigurationBlock::new(COMMON_CONFIGURATION_BLOCK)
+        .page_size(256)
+        .sector_size(4096)
+        .ip_cmd_serial_clk_freq(nor::SerialClockFrequency::MHz30);
+
+#[no_mangle]
+#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".fcb")]
+pub static FLEXSPI_CONFIGURATION_BLOCK: nor::ConfigurationBlock = SERIAL_NOR_CONFIGURATION_BLOCK;
diff --git a/examples/mspm0g3507/.cargo/config.toml b/examples/mspm0g3507/.cargo/config.toml
index 34c720cdd..e711afaf2 100644
--- a/examples/mspm0g3507/.cargo/config.toml
+++ b/examples/mspm0g3507/.cargo/config.toml
@@ -6,4 +6,4 @@ runner = "probe-rs run --chip MSPM0G3507 --protocol=swd"
 target = "thumbv6m-none-eabi"
 
 [env]
-DEFMT_LOG = "debug"
+DEFMT_LOG = "trace"
diff --git a/examples/mspm0g3507/Cargo.toml b/examples/mspm0g3507/Cargo.toml
index b6621c9c5..cc40b3109 100644
--- a/examples/mspm0g3507/Cargo.toml
+++ b/examples/mspm0g3507/Cargo.toml
@@ -17,5 +17,7 @@ defmt-rtt = "1.0.0"
 panic-probe = { version = "1.0.0", features = ["print-defmt"] }
 panic-semihosting = "0.6.0"
 
+embedded-io-async = "0.6.1"
+
 [profile.release]
 debug = 2
diff --git a/examples/nrf-rtos-trace/Cargo.toml b/examples/nrf-rtos-trace/Cargo.toml
index d9e8ca2f9..f1c40192d 100644
--- a/examples/nrf-rtos-trace/Cargo.toml
+++ b/examples/nrf-rtos-trace/Cargo.toml
@@ -18,7 +18,7 @@ log = [
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync" }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "rtos-trace"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time" }
-embassy-nrf = { version = "0.3.1", path = "../../embassy-nrf", features = ["nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac"] }
+embassy-nrf = { version = "0.5.0", path = "../../embassy-nrf", features = ["nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac"] }
 
 cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
 cortex-m-rt = "0.7.0"
diff --git a/examples/nrf51/Cargo.toml b/examples/nrf51/Cargo.toml
index 91f78737f..a21d7f6ce 100644
--- a/examples/nrf51/Cargo.toml
+++ b/examples/nrf51/Cargo.toml
@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
 [dependencies]
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.3.1", path = "../../embassy-nrf", features = ["defmt", "nrf51", "gpiote", "time-driver-rtc1", "unstable-pac", "time", "rt"] }
+embassy-nrf = { version = "0.5.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "gpiote", "time-driver-rtc1", "unstable-pac", "time", "rt"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf52810/Cargo.toml b/examples/nrf52810/Cargo.toml
index 87da89efe..baa873f22 100644
--- a/examples/nrf52810/Cargo.toml
+++ b/examples/nrf52810/Cargo.toml
@@ -9,7 +9,7 @@ embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.3.1", path = "../../embassy-nrf", features = ["defmt", "nrf52810", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.5.0", path = "../../embassy-nrf", features = ["defmt", "nrf52810", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf52840-rtic/Cargo.toml b/examples/nrf52840-rtic/Cargo.toml
index afd269f72..3e499e9bc 100644
--- a/examples/nrf52840-rtic/Cargo.toml
+++ b/examples/nrf52840-rtic/Cargo.toml
@@ -11,7 +11,7 @@ embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = [ "defmt", "defmt-timestamp-uptime"] }
 embassy-time-queue-utils = { version = "0.1", path = "../../embassy-time-queue-utils", features = ["generic-queue-8"] }
-embassy-nrf = { version = "0.3.1", path = "../../embassy-nrf", features = [ "defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.5.0", path = "../../embassy-nrf", features = [ "defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf52840/Cargo.toml b/examples/nrf52840/Cargo.toml
index 4140e49d2..d2baebf8e 100644
--- a/examples/nrf52840/Cargo.toml
+++ b/examples/nrf52840/Cargo.toml
@@ -9,9 +9,9 @@ embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.3.1", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.5.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embedded-io = { version = "0.6.0", features = ["defmt-03"]  }
 embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
 embassy-net-esp-hosted = { version = "0.2.0", path = "../../embassy-net-esp-hosted", features = ["defmt"] }
diff --git a/examples/nrf52840/src/bin/self_spawn_current_executor.rs b/examples/nrf52840/src/bin/self_spawn_current_executor.rs
index ec9569a64..ddb40dc53 100644
--- a/examples/nrf52840/src/bin/self_spawn_current_executor.rs
+++ b/examples/nrf52840/src/bin/self_spawn_current_executor.rs
@@ -10,7 +10,8 @@ use {defmt_rtt as _, panic_probe as _};
 async fn my_task(n: u32) {
     Timer::after_secs(1).await;
     info!("Spawning self! {}", n);
-    unwrap!(Spawner::for_current_executor().await.spawn(my_task(n + 1)));
+    let spawner = unsafe { Spawner::for_current_executor().await };
+    unwrap!(spawner.spawn(my_task(n + 1)));
 }
 
 #[embassy_executor::main]
diff --git a/examples/nrf5340/Cargo.toml b/examples/nrf5340/Cargo.toml
index dc4fba4fd..bdebd5386 100644
--- a/examples/nrf5340/Cargo.toml
+++ b/examples/nrf5340/Cargo.toml
@@ -9,9 +9,9 @@ embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.3.1", path = "../../embassy-nrf", features = ["defmt", "nrf5340-app-s", "time-driver-rtc1", "gpiote", "unstable-pac"] }
+embassy-nrf = { version = "0.5.0", path = "../../embassy-nrf", features = ["defmt", "nrf5340-app-s", "time-driver-rtc1", "gpiote", "unstable-pac"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embedded-io-async = { version = "0.6.1" }
 
 defmt = "1.0.1"
diff --git a/examples/nrf54l15/Cargo.toml b/examples/nrf54l15/Cargo.toml
index 4b229d06d..27d5babee 100644
--- a/examples/nrf54l15/Cargo.toml
+++ b/examples/nrf54l15/Cargo.toml
@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
 [dependencies]
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.3.1", path = "../../embassy-nrf", features = ["defmt", "nrf54l15-app-s", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.5.0", path = "../../embassy-nrf", features = ["defmt", "nrf54l15-app-s", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf9151/ns/Cargo.toml b/examples/nrf9151/ns/Cargo.toml
index a083aa5e7..2a492b595 100644
--- a/examples/nrf9151/ns/Cargo.toml
+++ b/examples/nrf9151/ns/Cargo.toml
@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
 [dependencies]
 embassy-executor = { version = "0.7.0", path = "../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.3.1", path = "../../../embassy-nrf", features = ["defmt", "nrf9120-ns", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.5.0", path = "../../../embassy-nrf", features = ["defmt", "nrf9120-ns", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf9151/s/Cargo.toml b/examples/nrf9151/s/Cargo.toml
index ae98631ef..62ef3e4ce 100644
--- a/examples/nrf9151/s/Cargo.toml
+++ b/examples/nrf9151/s/Cargo.toml
@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
 [dependencies]
 embassy-executor = { version = "0.7.0", path = "../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.3.1", path = "../../../embassy-nrf", features = ["defmt", "nrf9120-s", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.5.0", path = "../../../embassy-nrf", features = ["defmt", "nrf9120-s", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/examples/nrf9160/Cargo.toml b/examples/nrf9160/Cargo.toml
index 25aedf624..c896afdbe 100644
--- a/examples/nrf9160/Cargo.toml
+++ b/examples/nrf9160/Cargo.toml
@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
 [dependencies]
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.3.1", path = "../../embassy-nrf", features = ["defmt", "nrf9160-s", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.5.0", path = "../../embassy-nrf", features = ["defmt", "nrf9160-s", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 embassy-net-nrf91 = { version = "0.1.0", path = "../../embassy-net-nrf91", features = ["defmt"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "proto-ipv4", "medium-ip"] }
 
diff --git a/examples/rp/Cargo.toml b/examples/rp/Cargo.toml
index c8a132a5e..eefd69315 100644
--- a/examples/rp/Cargo.toml
+++ b/examples/rp/Cargo.toml
@@ -6,18 +6,18 @@ license = "MIT OR Apache-2.0"
 
 
 [dependencies]
-embassy-embedded-hal = { version = "0.3.0", path = "../../embassy-embedded-hal", features = ["defmt"] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../embassy-embedded-hal", features = ["defmt"] }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-rp = { version = "0.4.0", path = "../../embassy-rp", features = ["defmt", "unstable-pac", "time-driver", "critical-section-impl", "rp2040"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-rp = { version = "0.6.0", path = "../../embassy-rp", features = ["defmt", "unstable-pac", "time-driver", "critical-section-impl", "rp2040"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "icmp", "tcp", "udp", "raw", "dhcpv4", "medium-ethernet", "dns", "proto-ipv4", "proto-ipv6", "multicast"] }
 embassy-net-wiznet = { version = "0.2.0", path = "../../embassy-net-wiznet", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
-embassy-usb-logger = { version = "0.4.0", path = "../../embassy-usb-logger" }
-cyw43 = { version = "0.3.0", path = "../../cyw43", features = ["defmt", "firmware-logs"] }
-cyw43-pio = { version = "0.4.0", path = "../../cyw43-pio", features = ["defmt"] }
+embassy-usb-logger = { version = "0.5.0", path = "../../embassy-usb-logger" }
+cyw43 = { version = "0.4.0", path = "../../cyw43", features = ["defmt", "firmware-logs"] }
+cyw43-pio = { version = "0.5.1", path = "../../cyw43-pio", features = ["defmt"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
@@ -58,11 +58,5 @@ rand = { version = "0.9.0", default-features = false }
 embedded-sdmmc = "0.7.0"
 
 [profile.release]
-debug = 2
-lto = true
-opt-level = 'z'
-
-[profile.dev]
-debug = 2
-lto = true
-opt-level = "z"
+# Enable generation of debug symbols even on release builds
+debug = true
diff --git a/examples/rp/src/bin/usb_raw_bulk.rs b/examples/rp/src/bin/usb_raw_bulk.rs
index 103269791..0747901d1 100644
--- a/examples/rp/src/bin/usb_raw_bulk.rs
+++ b/examples/rp/src/bin/usb_raw_bulk.rs
@@ -96,8 +96,8 @@ async fn main(_spawner: Spawner) {
     let mut function = builder.function(0xFF, 0, 0);
     let mut interface = function.interface();
     let mut alt = interface.alt_setting(0xFF, 0, 0, None);
-    let mut read_ep = alt.endpoint_bulk_out(64);
-    let mut write_ep = alt.endpoint_bulk_in(64);
+    let mut read_ep = alt.endpoint_bulk_out(None, 64);
+    let mut write_ep = alt.endpoint_bulk_in(None, 64);
     drop(function);
 
     // Build the builder.
diff --git a/examples/rp/src/bin/usb_webusb.rs b/examples/rp/src/bin/usb_webusb.rs
index a5dc94d5b..5cecb92f0 100644
--- a/examples/rp/src/bin/usb_webusb.rs
+++ b/examples/rp/src/bin/usb_webusb.rs
@@ -125,8 +125,8 @@ impl<'d, D: Driver<'d>> WebEndpoints<'d, D> {
         let mut iface = func.interface();
         let mut alt = iface.alt_setting(0xff, 0x00, 0x00, None);
 
-        let write_ep = alt.endpoint_bulk_in(config.max_packet_size);
-        let read_ep = alt.endpoint_bulk_out(config.max_packet_size);
+        let write_ep = alt.endpoint_bulk_in(None, config.max_packet_size);
+        let read_ep = alt.endpoint_bulk_out(None, config.max_packet_size);
 
         WebEndpoints { write_ep, read_ep }
     }
diff --git a/examples/rp235x/Cargo.toml b/examples/rp235x/Cargo.toml
index c81b79ae1..4d3dc77b5 100644
--- a/examples/rp235x/Cargo.toml
+++ b/examples/rp235x/Cargo.toml
@@ -6,18 +6,18 @@ license = "MIT OR Apache-2.0"
 
 
 [dependencies]
-embassy-embedded-hal = { version = "0.3.0", path = "../../embassy-embedded-hal", features = ["defmt"] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../embassy-embedded-hal", features = ["defmt"] }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-rp = { version = "0.4.0", path = "../../embassy-rp", features = ["defmt", "unstable-pac", "time-driver", "critical-section-impl", "rp235xa", "binary-info"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-rp = { version = "0.6.0", path = "../../embassy-rp", features = ["defmt", "unstable-pac", "time-driver", "critical-section-impl", "rp235xa", "binary-info"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "udp", "raw", "dhcpv4", "medium-ethernet", "dns"] }
 embassy-net-wiznet = { version = "0.2.0", path = "../../embassy-net-wiznet", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
-embassy-usb-logger = { version = "0.4.0", path = "../../embassy-usb-logger" }
-cyw43 = { version = "0.3.0", path = "../../cyw43", features = ["defmt", "firmware-logs"] }
-cyw43-pio = { version = "0.4.0", path = "../../cyw43-pio", features = ["defmt"] }
+embassy-usb-logger = { version = "0.5.0", path = "../../embassy-usb-logger" }
+cyw43 = { version = "0.4.0", path = "../../cyw43", features = ["defmt", "firmware-logs"] }
+cyw43-pio = { version = "0.5.1", path = "../../cyw43-pio", features = ["defmt"] }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
@@ -58,8 +58,5 @@ log = "0.4"
 embedded-sdmmc = "0.7.0"
 
 [profile.release]
-debug = 2
-
-[profile.dev]
-lto = true
-opt-level = "z"
+# Enable generation of debug symbols even on release builds
+debug = true
diff --git a/examples/rp235x/memory.x b/examples/rp235x/memory.x
index c803896f6..4382e2065 100644
--- a/examples/rp235x/memory.x
+++ b/examples/rp235x/memory.x
@@ -17,8 +17,8 @@ MEMORY {
      * of access times.
      * Example: Separate stacks for core0 and core1.
      */
-    SRAM4 : ORIGIN = 0x20080000, LENGTH = 4K
-    SRAM5 : ORIGIN = 0x20081000, LENGTH = 4K
+    SRAM8 : ORIGIN = 0x20080000, LENGTH = 4K
+    SRAM9 : ORIGIN = 0x20081000, LENGTH = 4K
 }
 
 SECTIONS {
diff --git a/examples/rp235x/src/bin/blinky_wifi.rs b/examples/rp235x/src/bin/blinky_wifi.rs
index 8c352ebc4..ef6057a1c 100644
--- a/examples/rp235x/src/bin/blinky_wifi.rs
+++ b/examples/rp235x/src/bin/blinky_wifi.rs
@@ -5,7 +5,7 @@
 #![no_std]
 #![no_main]
 
-use cyw43_pio::{PioSpi, DEFAULT_CLOCK_DIVIDER};
+use cyw43_pio::{PioSpi, RM2_CLOCK_DIVIDER};
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_rp::bind_interrupts;
@@ -58,7 +58,9 @@ async fn main(spawner: Spawner) {
     let spi = PioSpi::new(
         &mut pio.common,
         pio.sm0,
-        DEFAULT_CLOCK_DIVIDER,
+        // SPI communication won't work if the speed is too high, so we use a divider larger than `DEFAULT_CLOCK_DIVIDER`.
+        // See: https://github.com/embassy-rs/embassy/issues/3960.
+        RM2_CLOCK_DIVIDER,
         pio.irq0,
         cs,
         p.PIN_24,
diff --git a/examples/rp235x/src/bin/usb_webusb.rs b/examples/rp235x/src/bin/usb_webusb.rs
index 75d28c853..a68163b61 100644
--- a/examples/rp235x/src/bin/usb_webusb.rs
+++ b/examples/rp235x/src/bin/usb_webusb.rs
@@ -125,8 +125,8 @@ impl<'d, D: Driver<'d>> WebEndpoints<'d, D> {
         let mut iface = func.interface();
         let mut alt = iface.alt_setting(0xff, 0x00, 0x00, None);
 
-        let write_ep = alt.endpoint_bulk_in(config.max_packet_size);
-        let read_ep = alt.endpoint_bulk_out(config.max_packet_size);
+        let write_ep = alt.endpoint_bulk_in(None, config.max_packet_size);
+        let read_ep = alt.endpoint_bulk_out(None, config.max_packet_size);
 
         WebEndpoints { write_ep, read_ep }
     }
diff --git a/examples/stm32c0/Cargo.toml b/examples/stm32c0/Cargo.toml
index 4cf07cef4..70a7b0895 100644
--- a/examples/stm32c0/Cargo.toml
+++ b/examples/stm32c0/Cargo.toml
@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 # Change stm32c031c6 to your chip name, if necessary.
-embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32c031c6", "memory-x", "unstable-pac", "exti"]  }
+embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32c031c6", "memory-x", "unstable-pac", "exti", "chrono"]  }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
@@ -19,6 +19,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "1.0.0", features = ["print-defmt"] }
 heapless = { version = "0.8", default-features = false }
+chrono = { version = "^0.4", default-features = false}
 
 [profile.release]
 debug = 2
diff --git a/examples/stm32c0/src/bin/rtc.rs b/examples/stm32c0/src/bin/rtc.rs
new file mode 100644
index 000000000..82d8a37ba
--- /dev/null
+++ b/examples/stm32c0/src/bin/rtc.rs
@@ -0,0 +1,35 @@
+#![no_std]
+#![no_main]
+
+use chrono::{NaiveDate, NaiveDateTime};
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::rtc::{Rtc, RtcConfig};
+use embassy_stm32::Config;
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let config = Config::default();
+    let p = embassy_stm32::init(config);
+
+    info!("Hello World!");
+
+    let now = NaiveDate::from_ymd_opt(2020, 5, 15)
+        .unwrap()
+        .and_hms_opt(10, 30, 15)
+        .unwrap();
+
+    let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
+
+    rtc.set_datetime(now.into()).expect("datetime not set");
+
+    loop {
+        let now: NaiveDateTime = rtc.now().unwrap().into();
+
+        info!("{}", now.and_utc().timestamp());
+
+        Timer::after_millis(1000).await;
+    }
+}
diff --git a/examples/stm32f0/src/bin/adc-watchdog.rs b/examples/stm32f0/src/bin/adc-watchdog.rs
new file mode 100644
index 000000000..ff98aac8e
--- /dev/null
+++ b/examples/stm32f0/src/bin/adc-watchdog.rs
@@ -0,0 +1,34 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::adc::{self, Adc, WatchdogChannels};
+use embassy_stm32::bind_interrupts;
+use embassy_stm32::peripherals::ADC1;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    ADC1_COMP => adc::InterruptHandler<ADC1>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("ADC watchdog example");
+
+    let mut adc = Adc::new(p.ADC1, Irqs);
+    let pin = p.PC1;
+
+    loop {
+        // Wait for pin to go high
+        adc.init_watchdog(WatchdogChannels::from_channel(&pin), 0, 0x07F);
+        let v_high = adc.monitor_watchdog().await;
+        info!("ADC sample is high {}", v_high);
+
+        // Wait for pin to go low
+        adc.init_watchdog(WatchdogChannels::from_channel(&pin), 0x01f, 0xFFF);
+        let v_low = adc.monitor_watchdog().await;
+        info!("ADC sample is low {}", v_low);
+    }
+}
diff --git a/examples/stm32f1/Cargo.toml b/examples/stm32f1/Cargo.toml
index 261733305..01f4fd84a 100644
--- a/examples/stm32f1/Cargo.toml
+++ b/examples/stm32f1/Cargo.toml
@@ -10,7 +10,7 @@ embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = [
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32f1/src/bin/input_capture.rs b/examples/stm32f1/src/bin/input_capture.rs
index 6fe8e0b50..84811fb95 100644
--- a/examples/stm32f1/src/bin/input_capture.rs
+++ b/examples/stm32f1/src/bin/input_capture.rs
@@ -39,7 +39,7 @@ async fn main(spawner: Spawner) {
 
     unwrap!(spawner.spawn(blinky(p.PC13)));
 
-    let ch3 = CapturePin::new_ch3(p.PA2, Pull::None);
+    let ch3 = CapturePin::new(p.PA2, Pull::None);
     let mut ic = InputCapture::new(p.TIM2, None, None, Some(ch3), None, Irqs, khz(1000), Default::default());
 
     loop {
diff --git a/examples/stm32f1/src/bin/pwm_input.rs b/examples/stm32f1/src/bin/pwm_input.rs
index afbef3edb..aa6a11ff8 100644
--- a/examples/stm32f1/src/bin/pwm_input.rs
+++ b/examples/stm32f1/src/bin/pwm_input.rs
@@ -38,7 +38,7 @@ async fn main(spawner: Spawner) {
 
     unwrap!(spawner.spawn(blinky(p.PC13)));
 
-    let mut pwm_input = PwmInput::new(p.TIM2, p.PA0, Pull::None, khz(10));
+    let mut pwm_input = PwmInput::new_ch1(p.TIM2, p.PA0, Pull::None, khz(10));
     pwm_input.enable();
 
     loop {
diff --git a/examples/stm32f3/Cargo.toml b/examples/stm32f3/Cargo.toml
index f675b0be1..ab7d6b255 100644
--- a/examples/stm32f3/Cargo.toml
+++ b/examples/stm32f3/Cargo.toml
@@ -10,7 +10,7 @@ embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = [
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32f334/Cargo.toml b/examples/stm32f334/Cargo.toml
index b47a81e1b..6595804e1 100644
--- a/examples/stm32f334/Cargo.toml
+++ b/examples/stm32f334/Cargo.toml
@@ -9,7 +9,7 @@ embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["de
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = [ "defmt", "stm32f334r8", "unstable-pac", "memory-x", "time-driver-any", "exti"]  }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32f4/Cargo.toml b/examples/stm32f4/Cargo.toml
index edab9ea00..80c43f2ab 100644
--- a/examples/stm32f4/Cargo.toml
+++ b/examples/stm32f4/Cargo.toml
@@ -10,7 +10,7 @@ embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = ["
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt" ] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt" ] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", ] }
 embassy-net-wiznet = { version = "0.2.0", path = "../../embassy-net-wiznet", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
diff --git a/examples/stm32f4/src/bin/input_capture.rs b/examples/stm32f4/src/bin/input_capture.rs
index fe5e2bdfc..e15b4d26e 100644
--- a/examples/stm32f4/src/bin/input_capture.rs
+++ b/examples/stm32f4/src/bin/input_capture.rs
@@ -39,7 +39,7 @@ async fn main(spawner: Spawner) {
 
     unwrap!(spawner.spawn(blinky(p.PB2)));
 
-    let ch3 = CapturePin::new_ch3(p.PB10, Pull::None);
+    let ch3 = CapturePin::new(p.PB10, Pull::None);
     let mut ic = InputCapture::new(p.TIM2, None, None, Some(ch3), None, Irqs, khz(1000), Default::default());
 
     loop {
diff --git a/examples/stm32f4/src/bin/pwm.rs b/examples/stm32f4/src/bin/pwm.rs
index 04811162b..e385842f0 100644
--- a/examples/stm32f4/src/bin/pwm.rs
+++ b/examples/stm32f4/src/bin/pwm.rs
@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let ch1_pin = PwmPin::new_ch1(p.PE9, OutputType::PushPull);
+    let ch1_pin = PwmPin::new(p.PE9, OutputType::PushPull);
     let mut pwm = SimplePwm::new(p.TIM1, Some(ch1_pin), None, None, None, khz(10), Default::default());
     let mut ch1 = pwm.ch1();
     ch1.enable();
diff --git a/examples/stm32f4/src/bin/pwm_complementary.rs b/examples/stm32f4/src/bin/pwm_complementary.rs
index 161f43c48..c981f1a76 100644
--- a/examples/stm32f4/src/bin/pwm_complementary.rs
+++ b/examples/stm32f4/src/bin/pwm_complementary.rs
@@ -16,8 +16,8 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let ch1 = PwmPin::new_ch1(p.PE9, OutputType::PushPull);
-    let ch1n = ComplementaryPwmPin::new_ch1(p.PA7, OutputType::PushPull);
+    let ch1 = PwmPin::new(p.PE9, OutputType::PushPull);
+    let ch1n = ComplementaryPwmPin::new(p.PA7, OutputType::PushPull);
     let mut pwm = ComplementaryPwm::new(
         p.TIM1,
         Some(ch1),
diff --git a/examples/stm32f4/src/bin/pwm_input.rs b/examples/stm32f4/src/bin/pwm_input.rs
index 465cbe4f5..74167cbf2 100644
--- a/examples/stm32f4/src/bin/pwm_input.rs
+++ b/examples/stm32f4/src/bin/pwm_input.rs
@@ -38,7 +38,7 @@ async fn main(spawner: Spawner) {
 
     unwrap!(spawner.spawn(blinky(p.PB2)));
 
-    let mut pwm_input = PwmInput::new(p.TIM3, p.PA6, Pull::None, khz(10));
+    let mut pwm_input = PwmInput::new_ch1(p.TIM3, p.PA6, Pull::None, khz(10));
     pwm_input.enable();
 
     loop {
diff --git a/examples/stm32f4/src/bin/ws2812_pwm.rs b/examples/stm32f4/src/bin/ws2812_pwm.rs
index ca924e181..5153e1cfd 100644
--- a/examples/stm32f4/src/bin/ws2812_pwm.rs
+++ b/examples/stm32f4/src/bin/ws2812_pwm.rs
@@ -50,7 +50,7 @@ async fn main(_spawner: Spawner) {
 
     let mut ws2812_pwm = SimplePwm::new(
         dp.TIM3,
-        Some(PwmPin::new_ch1(dp.PB4, OutputType::PushPull)),
+        Some(PwmPin::new(dp.PB4, OutputType::PushPull)),
         None,
         None,
         None,
diff --git a/examples/stm32f7/Cargo.toml b/examples/stm32f7/Cargo.toml
index c5801ea90..5995211d2 100644
--- a/examples/stm32f7/Cargo.toml
+++ b/examples/stm32f7/Cargo.toml
@@ -12,7 +12,7 @@ embassy-executor = { version = "0.7.0", path = "../../embassy-executor", feature
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet"] }
 embedded-io-async = { version = "0.6.1" }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32f7/src/bin/cryp.rs b/examples/stm32f7/src/bin/cryp.rs
index 235853cb9..a31e9b4f2 100644
--- a/examples/stm32f7/src/bin/cryp.rs
+++ b/examples/stm32f7/src/bin/cryp.rs
@@ -68,7 +68,9 @@ async fn main(_spawner: Spawner) -> ! {
     );
 
     // Decrypt in software using AES-GCM 128-bit
-    let _ = cipher.decrypt_in_place(&iv.into(), aad.into(), &mut payload_vec);
+    cipher
+        .decrypt_in_place(&iv.into(), aad.into(), &mut payload_vec)
+        .unwrap();
 
     let sw_end_time = Instant::now();
     let sw_execution_time = sw_end_time - sw_start_time;
diff --git a/examples/stm32f7/src/bin/qspi.rs b/examples/stm32f7/src/bin/qspi.rs
index bd3287964..ab29ddeff 100644
--- a/examples/stm32f7/src/bin/qspi.rs
+++ b/examples/stm32f7/src/bin/qspi.rs
@@ -279,6 +279,7 @@ async fn main(_spawner: Spawner) -> ! {
         prescaler: 16,
         cs_high_time: ChipSelectHighTime::_1Cycle,
         fifo_threshold: FIFOThresholdLevel::_16Bytes,
+        sample_shifting: SampleShifting::None,
     };
     let driver = Qspi::new_bank1(
         p.QUADSPI, p.PF8, p.PF9, p.PE2, p.PF6, p.PF10, p.PB10, p.DMA2_CH7, config,
diff --git a/examples/stm32g0/Cargo.toml b/examples/stm32g0/Cargo.toml
index bf1e7250e..1c290fcfa 100644
--- a/examples/stm32g0/Cargo.toml
+++ b/examples/stm32g0/Cargo.toml
@@ -10,7 +10,7 @@ embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = [
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", default-features = false, features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", default-features = false, features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32g0/src/bin/hf_timer.rs b/examples/stm32g0/src/bin/hf_timer.rs
index dfb6e0edc..705905f01 100644
--- a/examples/stm32g0/src/bin/hf_timer.rs
+++ b/examples/stm32g0/src/bin/hf_timer.rs
@@ -37,8 +37,8 @@ async fn main(_spawner: Spawner) {
     }
     let p = embassy_stm32::init(config);
 
-    let ch1 = PwmPin::new_ch1(p.PA8, OutputType::PushPull);
-    let ch1n = ComplementaryPwmPin::new_ch1(p.PA7, OutputType::PushPull);
+    let ch1 = PwmPin::new(p.PA8, OutputType::PushPull);
+    let ch1n = ComplementaryPwmPin::new(p.PA7, OutputType::PushPull);
 
     let mut pwm = ComplementaryPwm::new(
         p.TIM1,
diff --git a/examples/stm32g0/src/bin/input_capture.rs b/examples/stm32g0/src/bin/input_capture.rs
index 08df4e043..df339d541 100644
--- a/examples/stm32g0/src/bin/input_capture.rs
+++ b/examples/stm32g0/src/bin/input_capture.rs
@@ -47,12 +47,12 @@ async fn main(spawner: Spawner) {
     unwrap!(spawner.spawn(blinky(p.PB1)));
 
     // Connect PB1 and PA8 with a 1k Ohm resistor
-    let ch1_pin = PwmPin::new_ch1(p.PA8, OutputType::PushPull);
+    let ch1_pin = PwmPin::new(p.PA8, OutputType::PushPull);
     let mut pwm = SimplePwm::new(p.TIM1, Some(ch1_pin), None, None, None, khz(1), Default::default());
     pwm.ch1().enable();
     pwm.ch1().set_duty_cycle(50);
 
-    let ch1 = CapturePin::new_ch1(p.PA0, Pull::None);
+    let ch1 = CapturePin::new(p.PA0, Pull::None);
     let mut ic = InputCapture::new(p.TIM2, Some(ch1), None, None, None, Irqs, khz(1000), Default::default());
 
     let mut old_capture = 0;
diff --git a/examples/stm32g0/src/bin/pwm_complementary.rs b/examples/stm32g0/src/bin/pwm_complementary.rs
index 97b163c40..dbd9194c9 100644
--- a/examples/stm32g0/src/bin/pwm_complementary.rs
+++ b/examples/stm32g0/src/bin/pwm_complementary.rs
@@ -26,10 +26,10 @@ use {defmt_rtt as _, panic_probe as _};
 async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
 
-    let ch1 = PwmPin::new_ch1(p.PA8, OutputType::PushPull);
-    let ch1n = ComplementaryPwmPin::new_ch1(p.PA7, OutputType::PushPull);
-    let ch2 = PwmPin::new_ch2(p.PB3, OutputType::PushPull);
-    let ch2n = ComplementaryPwmPin::new_ch2(p.PB0, OutputType::PushPull);
+    let ch1 = PwmPin::new(p.PA8, OutputType::PushPull);
+    let ch1n = ComplementaryPwmPin::new(p.PA7, OutputType::PushPull);
+    let ch2 = PwmPin::new(p.PB3, OutputType::PushPull);
+    let ch2n = ComplementaryPwmPin::new(p.PB0, OutputType::PushPull);
 
     let mut pwm = ComplementaryPwm::new(
         p.TIM1,
diff --git a/examples/stm32g0/src/bin/pwm_input.rs b/examples/stm32g0/src/bin/pwm_input.rs
index 9d6b5fe97..fd4f53f1e 100644
--- a/examples/stm32g0/src/bin/pwm_input.rs
+++ b/examples/stm32g0/src/bin/pwm_input.rs
@@ -42,12 +42,12 @@ async fn main(spawner: Spawner) {
 
     unwrap!(spawner.spawn(blinky(p.PB1)));
     // Connect PA8 and PA6 with a 1k Ohm resistor
-    let ch1_pin = PwmPin::new_ch1(p.PA8, OutputType::PushPull);
+    let ch1_pin = PwmPin::new(p.PA8, OutputType::PushPull);
     let mut pwm = SimplePwm::new(p.TIM1, Some(ch1_pin), None, None, None, khz(1), Default::default());
     pwm.ch1().set_duty_cycle_fraction(1, 4);
     pwm.ch1().enable();
 
-    let mut pwm_input = PwmInput::new(p.TIM2, p.PA0, Pull::None, khz(1000));
+    let mut pwm_input = PwmInput::new_ch1(p.TIM2, p.PA0, Pull::None, khz(1000));
     pwm_input.enable();
 
     loop {
diff --git a/examples/stm32g4/Cargo.toml b/examples/stm32g4/Cargo.toml
index 3d2c2aa7d..a503420e5 100644
--- a/examples/stm32g4/Cargo.toml
+++ b/examples/stm32g4/Cargo.toml
@@ -10,7 +10,7 @@ embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = [
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 usbd-hid = "0.8.1"
 
diff --git a/examples/stm32g4/src/bin/i2c_slave.rs b/examples/stm32g4/src/bin/i2c_slave.rs
new file mode 100644
index 000000000..a723a0e18
--- /dev/null
+++ b/examples/stm32g4/src/bin/i2c_slave.rs
@@ -0,0 +1,149 @@
+//! This example shows how to use an stm32 as both a master and a slave.
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::i2c::{Address, OwnAddresses, SlaveCommandKind};
+use embassy_stm32::mode::Async;
+use embassy_stm32::time::Hertz;
+use embassy_stm32::{bind_interrupts, i2c, peripherals};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    I2C1_ER => i2c::ErrorInterruptHandler<peripherals::I2C1>;
+    I2C1_EV => i2c::EventInterruptHandler<peripherals::I2C1>;
+    I2C2_ER => i2c::ErrorInterruptHandler<peripherals::I2C2>;
+    I2C2_EV => i2c::EventInterruptHandler<peripherals::I2C2>;
+});
+
+const DEV_ADDR: u8 = 0x42;
+
+#[embassy_executor::task]
+async fn device_task(mut dev: i2c::I2c<'static, Async, i2c::MultiMaster>) -> ! {
+    info!("Device start");
+
+    let mut state = 0;
+
+    loop {
+        let mut buf = [0u8; 128];
+        match dev.listen().await {
+            Ok(i2c::SlaveCommand {
+                kind: SlaveCommandKind::Read,
+                address: Address::SevenBit(DEV_ADDR),
+            }) => match dev.respond_to_read(&[state]).await {
+                Ok(i2c::SendStatus::LeftoverBytes(x)) => info!("tried to write {} extra bytes", x),
+                Ok(i2c::SendStatus::Done) => {}
+                Err(e) => error!("error while responding {}", e),
+            },
+            Ok(i2c::SlaveCommand {
+                kind: SlaveCommandKind::Write,
+                address: Address::SevenBit(DEV_ADDR),
+            }) => match dev.respond_to_write(&mut buf).await {
+                Ok(len) => {
+                    info!("Device received write: {}", buf[..len]);
+
+                    if match buf[0] {
+                        // Set the state
+                        0xC2 => {
+                            state = buf[1];
+                            true
+                        }
+                        // Reset State
+                        0xC8 => {
+                            state = 0;
+                            true
+                        }
+                        x => {
+                            error!("Invalid Write Read {:x}", x);
+                            false
+                        }
+                    } {
+                        match dev.respond_to_read(&[state]).await {
+                            Ok(read_status) => info!(
+                                "This read is part of a write/read transaction. The response read status {}",
+                                read_status
+                            ),
+                            Err(i2c::Error::Timeout) => {
+                                info!("The device only performed a write and it not also do a read")
+                            }
+                            Err(e) => error!("error while responding {}", e),
+                        }
+                    }
+                }
+                Err(e) => error!("error while receiving {}", e),
+            },
+            Ok(i2c::SlaveCommand { address, .. }) => {
+                defmt::unreachable!(
+                    "The slave matched address: {}, which it was not configured for",
+                    address
+                );
+            }
+            Err(e) => error!("{}", e),
+        }
+    }
+}
+
+#[embassy_executor::task]
+async fn controller_task(mut con: i2c::I2c<'static, Async, i2c::Master>) {
+    info!("Controller start");
+
+    loop {
+        let mut resp_buff = [0u8; 1];
+        for i in 0..10 {
+            match con.write_read(DEV_ADDR, &[0xC2, i], &mut resp_buff).await {
+                Ok(_) => {
+                    info!("write_read response: {}", resp_buff);
+                    defmt::assert_eq!(resp_buff[0], i);
+                }
+                Err(e) => error!("Error writing {}", e),
+            }
+
+            Timer::after_millis(100).await;
+        }
+        match con.read(DEV_ADDR, &mut resp_buff).await {
+            Ok(_) => {
+                info!("read response: {}", resp_buff);
+                // assert that the state is the last index that was written
+                defmt::assert_eq!(resp_buff[0], 9);
+            }
+            Err(e) => error!("Error writing {}", e),
+        }
+        match con.write_read(DEV_ADDR, &[0xC8], &mut resp_buff).await {
+            Ok(_) => {
+                info!("write_read response: {}", resp_buff);
+                // assert that the state has been reset
+                defmt::assert_eq!(resp_buff[0], 0);
+            }
+            Err(e) => error!("Error writing {}", e),
+        }
+        Timer::after_millis(100).await;
+    }
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Hello World!");
+
+    let speed = Hertz::khz(400);
+    let config = i2c::Config::default();
+
+    let d_addr_config = i2c::SlaveAddrConfig {
+        addr: OwnAddresses::OA1(Address::SevenBit(DEV_ADDR)),
+        general_call: false,
+    };
+    let d_sda = p.PA8;
+    let d_scl = p.PA9;
+    let device = i2c::I2c::new(p.I2C2, d_scl, d_sda, Irqs, p.DMA1_CH1, p.DMA1_CH2, speed, config)
+        .into_slave_multimaster(d_addr_config);
+
+    unwrap!(spawner.spawn(device_task(device)));
+
+    let c_sda = p.PB8;
+    let c_scl = p.PB7;
+    let controller = i2c::I2c::new(p.I2C1, c_sda, c_scl, Irqs, p.DMA1_CH3, p.DMA1_CH4, speed, config);
+
+    unwrap!(spawner.spawn(controller_task(controller)));
+}
diff --git a/examples/stm32g4/src/bin/pwm.rs b/examples/stm32g4/src/bin/pwm.rs
index 6c965012c..5b4194927 100644
--- a/examples/stm32g4/src/bin/pwm.rs
+++ b/examples/stm32g4/src/bin/pwm.rs
@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let ch1_pin = PwmPin::new_ch1(p.PC0, OutputType::PushPull);
+    let ch1_pin = PwmPin::new(p.PC0, OutputType::PushPull);
     let mut pwm = SimplePwm::new(p.TIM1, Some(ch1_pin), None, None, None, khz(10), Default::default());
     let mut ch1 = pwm.ch1();
     ch1.enable();
diff --git a/examples/stm32h5/Cargo.toml b/examples/stm32h5/Cargo.toml
index f3fda7ff3..0ac9016d4 100644
--- a/examples/stm32h5/Cargo.toml
+++ b/examples/stm32h5/Cargo.toml
@@ -11,7 +11,7 @@ embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["de
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32h7/Cargo.toml b/examples/stm32h7/Cargo.toml
index 27c59d980..9053289ea 100644
--- a/examples/stm32h7/Cargo.toml
+++ b/examples/stm32h7/Cargo.toml
@@ -8,11 +8,11 @@ license = "MIT OR Apache-2.0"
 # Change stm32h743bi to your chip name, if necessary.
 embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = ["defmt", "stm32h743bi", "time-driver-tim2", "exti", "memory-x", "unstable-pac", "chrono"] }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../embassy-embedded-hal" }
+embassy-embedded-hal = { version = "0.3.1", path = "../../embassy-embedded-hal" }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6", "dns"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32h7/src/bin/i2c_shared.rs b/examples/stm32h7/src/bin/i2c_shared.rs
index 136b91eeb..655ff901f 100644
--- a/examples/stm32h7/src/bin/i2c_shared.rs
+++ b/examples/stm32h7/src/bin/i2c_shared.rs
@@ -25,7 +25,7 @@ const SHTC3_WAKEUP: [u8; 2] = [0x35, 0x17];
 const SHTC3_MEASURE_RH_FIRST: [u8; 2] = [0x5c, 0x24];
 const SHTC3_SLEEP: [u8; 2] = [0xb0, 0x98];
 
-static I2C_BUS: StaticCell<NoopMutex<RefCell<I2c<'static, Async>>>> = StaticCell::new();
+static I2C_BUS: StaticCell<NoopMutex<RefCell<I2c<'static, Async, i2c::Master>>>> = StaticCell::new();
 
 bind_interrupts!(struct Irqs {
     I2C1_EV => i2c::EventInterruptHandler<peripherals::I2C1>;
@@ -33,7 +33,7 @@ bind_interrupts!(struct Irqs {
 });
 
 #[embassy_executor::task]
-async fn temperature(mut i2c: I2cDevice<'static, NoopRawMutex, I2c<'static, Async>>) {
+async fn temperature(mut i2c: I2cDevice<'static, NoopRawMutex, I2c<'static, Async, i2c::Master>>) {
     let mut data = [0u8; 2];
 
     loop {
@@ -50,7 +50,7 @@ async fn temperature(mut i2c: I2cDevice<'static, NoopRawMutex, I2c<'static, Asyn
 }
 
 #[embassy_executor::task]
-async fn humidity(mut i2c: I2cDevice<'static, NoopRawMutex, I2c<'static, Async>>) {
+async fn humidity(mut i2c: I2cDevice<'static, NoopRawMutex, I2c<'static, Async, i2c::Master>>) {
     let mut data = [0u8; 6];
 
     loop {
diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs
index 8de31ea5b..12abb8693 100644
--- a/examples/stm32h7/src/bin/low_level_timer_api.rs
+++ b/examples/stm32h7/src/bin/low_level_timer_api.rs
@@ -6,7 +6,7 @@ use embassy_executor::Spawner;
 use embassy_stm32::gpio::{AfType, Flex, OutputType, Speed};
 use embassy_stm32::time::{khz, Hertz};
 use embassy_stm32::timer::low_level::{OutputCompareMode, Timer as LLTimer};
-use embassy_stm32::timer::{Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin, GeneralInstance32bit4Channel};
+use embassy_stm32::timer::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance32bit4Channel, TimerPin};
 use embassy_stm32::{Config, Peri};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
@@ -67,10 +67,10 @@ pub struct SimplePwm32<'d, T: GeneralInstance32bit4Channel> {
 impl<'d, T: GeneralInstance32bit4Channel> SimplePwm32<'d, T> {
     pub fn new(
         tim: Peri<'d, T>,
-        ch1: Peri<'d, impl Channel1Pin<T>>,
-        ch2: Peri<'d, impl Channel2Pin<T>>,
-        ch3: Peri<'d, impl Channel3Pin<T>>,
-        ch4: Peri<'d, impl Channel4Pin<T>>,
+        ch1: Peri<'d, impl TimerPin<T, Ch1>>,
+        ch2: Peri<'d, impl TimerPin<T, Ch2>>,
+        ch3: Peri<'d, impl TimerPin<T, Ch3>>,
+        ch4: Peri<'d, impl TimerPin<T, Ch4>>,
         freq: Hertz,
     ) -> Self {
         let af1 = ch1.af_num();
diff --git a/examples/stm32h7/src/bin/pwm.rs b/examples/stm32h7/src/bin/pwm.rs
index a1c53fc3f..73b43be69 100644
--- a/examples/stm32h7/src/bin/pwm.rs
+++ b/examples/stm32h7/src/bin/pwm.rs
@@ -36,7 +36,7 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(config);
     info!("Hello World!");
 
-    let ch1_pin = PwmPin::new_ch1(p.PA6, OutputType::PushPull);
+    let ch1_pin = PwmPin::new(p.PA6, OutputType::PushPull);
     let mut pwm = SimplePwm::new(p.TIM3, Some(ch1_pin), None, None, None, khz(10), Default::default());
     let mut ch1 = pwm.ch1();
     ch1.enable();
diff --git a/examples/stm32h723/src/bin/spdifrx.rs b/examples/stm32h723/src/bin/spdifrx.rs
index a04d7cb34..6d29e8a4d 100644
--- a/examples/stm32h723/src/bin/spdifrx.rs
+++ b/examples/stm32h723/src/bin/spdifrx.rs
@@ -7,9 +7,9 @@
 
 use defmt::{info, trace};
 use embassy_executor::Spawner;
-use embassy_futures::select::{self, select, Either};
+use embassy_futures::select::{select, Either};
 use embassy_stm32::spdifrx::{self, Spdifrx};
-use embassy_stm32::{bind_interrupts, peripherals, sai};
+use embassy_stm32::{bind_interrupts, peripherals, sai, Peri};
 use grounded::uninit::GroundedArrayCell;
 use hal::sai::*;
 use {defmt_rtt as _, embassy_stm32 as hal, panic_probe as _};
@@ -25,10 +25,10 @@ const DMA_BUFFER_LENGTH: usize = HALF_DMA_BUFFER_LENGTH * 2; //  2 half-blocks
 
 // DMA buffers must be in special regions. Refer https://embassy.dev/book/#_stm32_bdma_only_working_out_of_some_ram_regions
 #[unsafe(link_section = ".sram1")]
-static mut SPDIFRX_BUFFER: GroundedArrayCell<u32, DMA_BUFFER_LENGTH> = GroundedArrayCell::uninit();
+static SPDIFRX_BUFFER: GroundedArrayCell<u32, DMA_BUFFER_LENGTH> = GroundedArrayCell::uninit();
 
 #[unsafe(link_section = ".sram4")]
-static mut SAI_BUFFER: GroundedArrayCell<u32, DMA_BUFFER_LENGTH> = GroundedArrayCell::uninit();
+static SAI_BUFFER: GroundedArrayCell<u32, DMA_BUFFER_LENGTH> = GroundedArrayCell::uninit();
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
@@ -144,9 +144,9 @@ async fn main(_spawner: Spawner) {
 ///
 /// Used (again) after dropping the SPDIFRX instance, in case of errors (e.g. source disconnect).
 fn new_spdif_receiver<'d>(
-    spdifrx: &'d mut peripherals::SPDIFRX1,
-    input_pin: &'d mut peripherals::PD7,
-    dma: &'d mut peripherals::DMA2_CH7,
+    spdifrx: Peri<'d, peripherals::SPDIFRX1>,
+    input_pin: Peri<'d, peripherals::PD7>,
+    dma: Peri<'d, peripherals::DMA2_CH7>,
     buf: &'d mut [u32],
 ) -> Spdifrx<'d, peripherals::SPDIFRX1> {
     Spdifrx::new(spdifrx, Irqs, spdifrx::Config::default(), input_pin, dma, buf)
@@ -156,11 +156,11 @@ fn new_spdif_receiver<'d>(
 ///
 /// Used (again) after dropping the SAI4 instance, in case of errors (e.g. buffer overrun).
 fn new_sai_transmitter<'d>(
-    sai: &'d mut peripherals::SAI4,
-    sck: &'d mut peripherals::PD13,
-    sd: &'d mut peripherals::PC1,
-    fs: &'d mut peripherals::PD12,
-    dma: &'d mut peripherals::BDMA_CH0,
+    sai: Peri<'d, peripherals::SAI4>,
+    sck: Peri<'d, peripherals::PD13>,
+    sd: Peri<'d, peripherals::PC1>,
+    fs: Peri<'d, peripherals::PD12>,
+    dma: Peri<'d, peripherals::BDMA_CH0>,
     buf: &'d mut [u32],
 ) -> Sai<'d, peripherals::SAI4, u32> {
     let mut sai_config = hal::sai::Config::default();
diff --git a/examples/stm32h735/Cargo.toml b/examples/stm32h735/Cargo.toml
index 8d23c346a..e4938e15b 100644
--- a/examples/stm32h735/Cargo.toml
+++ b/examples/stm32h735/Cargo.toml
@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
 [dependencies]
 embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = ["defmt", "stm32h735ig", "time-driver-tim2", "exti", "memory-x", "unstable-pac", "chrono"] }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../embassy-embedded-hal" }
+embassy-embedded-hal = { version = "0.3.1", path = "../../embassy-embedded-hal" }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
diff --git a/examples/stm32h742/Cargo.toml b/examples/stm32h742/Cargo.toml
index 31eff4379..efa71e144 100644
--- a/examples/stm32h742/Cargo.toml
+++ b/examples/stm32h742/Cargo.toml
@@ -34,7 +34,7 @@ embassy-net = { version = "0.7.0", path = "../../embassy-net", features = [
     "medium-ethernet",
 ] }
 embedded-io-async = { version = "0.6.1" }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = [
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = [
     "defmt",
 ] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
diff --git a/examples/stm32h742/src/bin/qspi.rs b/examples/stm32h742/src/bin/qspi.rs
index aee07f3f2..50e37ec52 100644
--- a/examples/stm32h742/src/bin/qspi.rs
+++ b/examples/stm32h742/src/bin/qspi.rs
@@ -272,6 +272,7 @@ async fn main(_spawner: Spawner) -> ! {
         prescaler: 16,
         cs_high_time: ChipSelectHighTime::_1Cycle,
         fifo_threshold: FIFOThresholdLevel::_16Bytes,
+        sample_shifting: SampleShifting::None,
     };
     let driver = Qspi::new_blocking_bank1(p.QUADSPI, p.PD11, p.PD12, p.PE2, p.PD13, p.PB2, p.PB10, config);
     let mut flash = FlashMemory::new(driver);
diff --git a/examples/stm32h755cm4/Cargo.toml b/examples/stm32h755cm4/Cargo.toml
index 71bd50d60..eaaeb1ac0 100644
--- a/examples/stm32h755cm4/Cargo.toml
+++ b/examples/stm32h755cm4/Cargo.toml
@@ -8,11 +8,11 @@ license = "MIT OR Apache-2.0"
 # Change stm32h755zi-cm4 to your chip name, if necessary.
 embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = ["defmt", "stm32h755zi-cm4", "time-driver-tim2", "exti", "memory-x", "unstable-pac", "chrono"] }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../embassy-embedded-hal" }
+embassy-embedded-hal = { version = "0.3.1", path = "../../embassy-embedded-hal" }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6", "dns"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32h755cm7/Cargo.toml b/examples/stm32h755cm7/Cargo.toml
index 8e960932a..e7fc05948 100644
--- a/examples/stm32h755cm7/Cargo.toml
+++ b/examples/stm32h755cm7/Cargo.toml
@@ -8,11 +8,11 @@ license = "MIT OR Apache-2.0"
 # Change stm32h743bi to your chip name, if necessary.
 embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = ["defmt", "stm32h755zi-cm7", "time-driver-tim3", "exti", "memory-x", "unstable-pac", "chrono"] }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../embassy-embedded-hal" }
+embassy-embedded-hal = { version = "0.3.1", path = "../../embassy-embedded-hal" }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6", "dns"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32h7b0/Cargo.toml b/examples/stm32h7b0/Cargo.toml
index 72f86e0cf..bfa7f9202 100644
--- a/examples/stm32h7b0/Cargo.toml
+++ b/examples/stm32h7b0/Cargo.toml
@@ -7,11 +7,11 @@ license = "MIT OR Apache-2.0"
 [dependencies]
 embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = ["defmt", "stm32h7b0vb", "time-driver-tim2", "exti", "memory-x", "unstable-pac", "chrono"] }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../embassy-embedded-hal" }
+embassy-embedded-hal = { version = "0.3.1", path = "../../embassy-embedded-hal" }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6", "dns"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32h7rs/Cargo.toml b/examples/stm32h7rs/Cargo.toml
index 5f1ce8dfc..9794c6dbd 100644
--- a/examples/stm32h7rs/Cargo.toml
+++ b/examples/stm32h7rs/Cargo.toml
@@ -11,7 +11,7 @@ embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["de
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "udp", "medium-ethernet", "medium-ip", "proto-ipv4"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs b/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs
index 88d914180..59045ca2e 100644
--- a/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs
+++ b/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs
@@ -3,7 +3,8 @@
 
 //! For Nucleo STM32H7S3L8 MB1737, has MX25UW25645GXDI00
 //!
-//! TODO: Currently this only uses single SPI, pending flash chip documentation for octo SPI.
+
+use core::cmp::min;
 
 use defmt::info;
 use embassy_executor::Spawner;
@@ -52,14 +53,16 @@ async fn main(_spawner: Spawner) {
         fifo_threshold: FIFOThresholdLevel::_4Bytes,
         memory_type: MemoryType::Macronix,
         delay_hold_quarter_cycle: true,
-        // memory_type: MemoryType::Micron,
-        // delay_hold_quarter_cycle: false,
         device_size: MemorySize::_32MiB,
         chip_select_high_time: ChipSelectHighTime::_2Cycle,
         free_running_clock: false,
         clock_mode: false,
         wrap_size: WrapSize::None,
-        // 300mhz / (4+1) = 60mhz. Unsure the limit, need to find a MX25UW25645GXDI00 datasheet.
+        // 300 MHz clock / (3 + 1) = 75 MHz. This is above the max for READ instructions so the
+        // FAST READ must be used. The nucleo board's flash  can run at up to 133 MHz in SPI mode
+        // and 200 MHz in OPI mode. This clock prescaler must be even otherwise the clock will not
+        // have symmetric high and low times.
+        // The clock can also be fed by one of the PLLs to allow for more flexible clock rates.
         clock_prescaler: 3,
         sample_shifting: false,
         chip_select_boundary: 0,
@@ -71,28 +74,41 @@ async fn main(_spawner: Spawner) {
 
     // Not necessary, but recommended if using XIP
     cor.SCB.enable_icache();
+    // Note: Enabling data cache can cause issues with DMA transfers.
     cor.SCB.enable_dcache(&mut cor.CPUID);
 
     let xspi = embassy_stm32::xspi::Xspi::new_blocking_xspi(
         p.XSPI2, p.PN6, p.PN2, p.PN3, p.PN4, p.PN5, p.PN8, p.PN9, p.PN10, p.PN11, p.PN1, spi_config,
     );
 
-    let mut flash = FlashMemory::new(xspi).await;
+    let mut flash = SpiFlashMemory::new(xspi);
 
     let flash_id = flash.read_id();
     info!("FLASH ID: {=[u8]:x}", flash_id);
 
-    let mut wr_buf = [0u8; 8];
-    for i in 0..8 {
-        wr_buf[i] = 0x90 + i as u8;
-    }
-    let mut rd_buf = [0u8; 8];
-    flash.erase_sector(0).await;
-    flash.write_memory(0, &wr_buf, true).await;
-    flash.read_memory(0, &mut rd_buf, true);
-    info!("WRITE BUF: {=[u8]:#X}", wr_buf);
-    info!("READ BUF: {=[u8]:#X}", rd_buf);
-    flash.enable_mm().await;
+    // Erase the first sector
+    flash.erase_sector(0);
+
+    // Write some data into the flash. This writes more than one page to test that functionality.
+    let mut wr_buf = [0u8; 512];
+    let base_number: u8 = 0x90;
+    for i in 0..512 {
+        wr_buf[i] = base_number.wrapping_add(i as u8);
+    }
+    flash.write_memory(0, &wr_buf);
+
+    // Read the data back and verify it.
+    let mut rd_buf = [0u8; 512];
+    let start_time = embassy_time::Instant::now();
+    flash.read_memory(0, &mut rd_buf);
+    let elapsed = start_time.elapsed();
+    info!("Read 512 bytes in {} us in SPI mode", elapsed.as_micros());
+    info!("WRITE BUF: {=[u8]:#X}", wr_buf[0..32]);
+    info!("READ BUF: {=[u8]:#X}", rd_buf[0..32]);
+
+    assert_eq!(wr_buf, rd_buf, "Read buffer does not match write buffer");
+
+    flash.enable_mm();
     info!("Enabled memory mapped mode");
 
     let first_u32 = unsafe { *(0x70000000 as *const u32) };
@@ -103,10 +119,53 @@ async fn main(_spawner: Spawner) {
     assert_eq!(second_u32, 0x97969594);
     info!("second_u32 {:08x}", first_u32);
 
-    flash.disable_mm().await;
+    flash.disable_mm();
     info!("Disabled memory mapped mode");
 
+    let flash_id = flash.read_id();
+    info!("FLASH ID: {=[u8]:x}", flash_id);
+
+    let mut flash = flash.into_octo();
+
+    Timer::after_millis(100).await;
+
+    let flash_id = flash.read_id();
+    info!("FLASH ID in OPI mode: {=[u8]:x}", flash_id);
+
+    flash.erase_sector(0);
+
+    let mut rd_buf = [0u8; 512];
+    flash.read_memory(0, &mut rd_buf);
+    info!("READ BUF after erase: {=[u8]:#X}", rd_buf[0..32]);
+
+    assert_eq!(rd_buf, [0xFF; 512], "Read buffer is not all 0xFF after erase");
+
+    flash.write_memory(0, &wr_buf);
+    let start = embassy_time::Instant::now();
+    flash.read_memory(0, &mut rd_buf);
+    let elapsed = start.elapsed();
+    info!("Read 512 bytes in {} us in OPI mode", elapsed.as_micros());
+    info!("READ BUF after write: {=[u8]:#X}", rd_buf[0..32]);
+    assert_eq!(wr_buf, rd_buf, "Read buffer does not match write buffer in OPI mode");
+
+    flash.enable_mm();
+    info!("Enabled memory mapped mode in OPI mode");
+    let first_u32 = unsafe { *(0x70000000 as *const u32) };
+    assert_eq!(first_u32, 0x93929190);
+    info!("first_u32 {:08x}", first_u32);
+    let second_u32 = unsafe { *(0x70000004 as *const u32) };
+    assert_eq!(second_u32, 0x97969594);
+    info!("second_u32 {:08x}", first_u32);
+    flash.disable_mm();
+    info!("Disabled memory mapped mode in OPI mode");
+
+    // Reset back to SPI mode
+    let mut flash = flash.into_spi();
+    let flash_id = flash.read_id();
+    info!("FLASH ID back in SPI mode: {=[u8]:x}", flash_id);
+
     info!("DONE");
+
     // Output pin PE3
     let mut led = Output::new(p.PE3, Level::Low, Speed::Low);
 
@@ -116,80 +175,268 @@ async fn main(_spawner: Spawner) {
     }
 }
 
-const MEMORY_PAGE_SIZE: usize = 8;
-
-const CMD_READ: u8 = 0x0B;
-const _CMD_QUAD_READ: u8 = 0x6B;
-
-const CMD_WRITE_PG: u8 = 0x02;
-const _CMD_QUAD_WRITE_PG: u8 = 0x32;
-
-const CMD_READ_ID: u8 = 0x9F;
-const CMD_READ_ID_OCTO: u16 = 0x9F60;
+const MEMORY_PAGE_SIZE: usize = 256;
 
-const CMD_ENABLE_RESET: u8 = 0x66;
-const CMD_RESET: u8 = 0x99;
-
-const CMD_WRITE_ENABLE: u8 = 0x06;
-
-const CMD_CHIP_ERASE: u8 = 0xC7;
-const CMD_SECTOR_ERASE: u8 = 0x20;
-const CMD_BLOCK_ERASE_32K: u8 = 0x52;
-const CMD_BLOCK_ERASE_64K: u8 = 0xD8;
-
-const CMD_READ_SR: u8 = 0x05;
-const CMD_READ_CR: u8 = 0x35;
-
-const CMD_WRITE_SR: u8 = 0x01;
-const CMD_WRITE_CR: u8 = 0x31;
+/// Implementation of access to flash chip using SPI.
+///
+/// Chip commands are hardcoded as it depends on used chip.
+/// This targets a MX25UW25645GXDI00.
+pub struct SpiFlashMemory<I: Instance> {
+    xspi: Xspi<'static, I, Blocking>,
+}
 
-/// Implementation of access to flash chip.
+/// Implementation of access to flash chip using Octo SPI.
 ///
 /// Chip commands are hardcoded as it depends on used chip.
 /// This targets a MX25UW25645GXDI00.
-pub struct FlashMemory<I: Instance> {
+pub struct OpiFlashMemory<I: Instance> {
     xspi: Xspi<'static, I, Blocking>,
 }
 
-impl<I: Instance> FlashMemory<I> {
-    pub async fn new(xspi: Xspi<'static, I, Blocking>) -> Self {
-        let mut memory = Self { xspi };
+/// SPI mode commands for MX25UW25645G flash memory
+#[allow(dead_code)]
+#[repr(u8)]
+enum SpiCommand {
+    // Array access commands
+    /// Read data bytes using 3-byte address (up to 50 MHz)
+    Read3B = 0x03,
+    /// Fast read data bytes using 3-byte address with 8 dummy cycles (up to 133 MHz)
+    FastRead3B = 0x0B,
+    /// Program 1-256 bytes of data using 3-byte address
+    PageProgram3B = 0x02,
+    /// Erase 4KB sector using 3-byte address
+    SectorErase3B = 0x20,
+    /// Erase 64KB block using 3-byte address
+    BlockErase3B = 0xD8,
+    /// Read data bytes using 4-byte address (up to 50 MHz)
+    Read4B = 0x13,
+    /// Fast read data bytes using 4-byte address with 8 dummy cycles (up to 133 MHz)
+    FastRead4B = 0x0C,
+    /// Program 1-256 bytes of data using 4-byte address
+    PageProgram4B = 0x12,
+    /// Erase 4KB sector using 4-byte address
+    SectorErase4B = 0x21,
+    /// Erase 64KB block using 4-byte address
+    BlockErase4B = 0xDC,
+    /// Erase entire chip (only if no blocks are protected)
+    ChipErase = 0x60,
+
+    // Write Buffer Access commands
+    /// Read data from the 256-byte page buffer
+    ReadBuffer = 0x25,
+    /// Initialize write-to-buffer sequence, clears buffer and writes initial data
+    WriteBufferInitial = 0x22,
+    /// Continue writing data to buffer (used between WRBI and WRCF)
+    WriteBufferContinue = 0x24,
+    /// Confirm write operation, programs buffer contents to flash array
+    WriteBufferConfirm = 0x31,
+
+    // Device operation commands
+    /// Set Write Enable Latch (WEL) bit, required before write/program/erase operations
+    WriteEnable = 0x06,
+    /// Clear Write Enable Latch (WEL) bit
+    WriteDisable = 0x04,
+    /// Select write protection mode (BP mode or Advanced Sector Protection)
+    WriteProtectSelection = 0x68,
+    /// Suspend ongoing program or erase operation to allow read access
+    ProgramEraseSuspend = 0xB0,
+    /// Resume suspended program or erase operation
+    ProgramEraseResume = 0x30,
+    /// Enter deep power-down mode for minimum power consumption
+    DeepPowerDown = 0xB9,
+    /// Exit deep power-down mode and return to standby
+    ReleaseFromDeepPowerDown = 0xAB,
+    /// No operation, can terminate Reset Enable command
+    NoOperation = 0x00,
+    /// Enable reset operation (must precede Reset Memory command)
+    ResetEnable = 0x66,
+    /// Reset device to power-on state (requires prior Reset Enable)
+    ResetMemory = 0x99,
+    /// Protect all sectors using Dynamic Protection Bits (DPB)
+    GangBlockLock = 0x7E,
+    /// Unprotect all sectors by clearing Dynamic Protection Bits (DPB)
+    GangBlockUnlock = 0x98,
+
+    // Register Access commands
+    /// Read 3-byte device identification (manufacturer ID + device ID)
+    ReadIdentification = 0x9F,
+    /// Read Serial Flash Discoverable Parameters (SFDP) table
+    ReadSFDP = 0x5A,
+    /// Read 8-bit Status Register (WIP, WEL, BP bits, etc.)
+    ReadStatusRegister = 0x05,
+    /// Read 8-bit Configuration Register (ODS, TB, PBE bits)
+    ReadConfigurationRegister = 0x15,
+    /// Write Status and/or Configuration Register (1-2 bytes)
+    WriteStatusConfigurationRegister = 0x01,
+    /// Read Configuration Register 2 from specified 4-byte address
+    ReadConfigurationRegister2 = 0x71,
+    /// Write Configuration Register 2 to specified 4-byte address
+    WriteConfigurationRegister2 = 0x72,
+    /// Read 8-bit Security Register (protection status, suspend bits)
+    ReadSecurityRegister = 0x2B,
+    /// Write Security Register to set customer lock-down bit
+    WriteSecurityRegister = 0x2F,
+    /// Read 32-bit Fast Boot Register (boot address and configuration)
+    ReadFastBootRegister = 0x16,
+    /// Write 32-bit Fast Boot Register
+    WriteFastBootRegister = 0x17,
+    /// Erase Fast Boot Register (disable fast boot feature)
+    EraseFastBootRegister = 0x18,
+    /// Set burst/wrap length for read operations (16/32/64 bytes)
+    SetBurstLength = 0xC0,
+    /// Enter 8K-bit secured OTP mode for programming unique identifiers
+    EnterSecuredOTP = 0xB1,
+    /// Exit secured OTP mode and return to main array access
+    ExitSecuredOTP = 0xC1,
+    /// Write Lock Register to control SPB protection mode
+    WriteLockRegister = 0x2C,
+    /// Read Lock Register status
+    ReadLockRegister = 0x2D,
+    /// Program Solid Protection Bit (SPB) for specified sector/block
+    WriteSPB = 0xE3,
+    /// Erase all Solid Protection Bits (SPB)
+    EraseSPB = 0xE4,
+    /// Read Solid Protection Bit (SPB) status for specified sector/block
+    ReadSPB = 0xE2,
+    /// Write Dynamic Protection Bit (DPB) for specified sector
+    WriteDPB = 0xE1,
+    /// Read Dynamic Protection Bit (DPB) status for specified sector
+    ReadDPB = 0xE0,
+    /// Read 64-bit password register (only in Solid Protection mode)
+    ReadPassword = 0x27,
+    /// Write 64-bit password register
+    WritePassword = 0x28,
+    /// Unlock SPB operations using 64-bit password
+    PasswordUnlock = 0x29,
+}
 
-        memory.reset_memory().await;
-        memory.enable_octo();
-        memory
-    }
+/// OPI mode commands for MX25UW25645G flash memory
+#[allow(dead_code)]
+#[repr(u16)]
+enum OpiCommand {
+    // Array access commands
+    /// Read data using 8 I/O lines in STR mode with configurable dummy cycles (up to 200 MHz)
+    OctaRead = 0xEC13,
+    /// Read data using 8 I/O lines in DTR mode with configurable dummy cycles (up to 200 MHz)
+    OctaDTRRead = 0xEE11,
+    /// Program 1-256 bytes using 4-byte address and 8 I/O lines
+    PageProgram4B = 0x12ED,
+    /// Erase 4KB sector using 4-byte address
+    SectorErase4B = 0x21DE,
+    /// Erase 64KB block using 4-byte address
+    BlockErase4B = 0xDC23,
+    /// Erase entire chip (only if no blocks are protected)
+    ChipErase = 0x609F,
+
+    // Write Buffer Access commands
+    /// Read data from the 256-byte page buffer using 4-byte address
+    ReadBuffer = 0x25DA,
+    /// Initialize interruptible write-to-buffer sequence with 4-byte address
+    WriteBufferInitial = 0x22DD,
+    /// Continue writing data to buffer during interruptible sequence
+    WriteBufferContinue = 0x24DB,
+    /// Confirm and execute write operation from buffer to flash array
+    WriteBufferConfirm = 0x31CE,
+
+    // Device operation commands
+    /// Set Write Enable Latch (WEL) bit, required before write/program/erase operations
+    WriteEnable = 0x06F9,
+    /// Clear Write Enable Latch (WEL) bit, aborts write-to-buffer sequence
+    WriteDisable = 0x04FB,
+    /// Select write protection mode (BP mode or Advanced Sector Protection) - OTP bit
+    WriteProtectSelection = 0x6897,
+    /// Suspend ongoing program or erase operation to allow read from other banks
+    ProgramEraseSuspend = 0xB04F,
+    /// Resume suspended program or erase operation
+    ProgramEraseResume = 0x30CF,
+    /// Enter deep power-down mode for minimum power consumption
+    DeepPowerDown = 0xB946,
+    /// Exit deep power-down mode and return to standby
+    ReleaseFromDeepPowerDown = 0xAB54,
+    /// No operation, can terminate Reset Enable command
+    NoOperation = 0x00FF,
+    /// Enable reset operation (must precede Reset Memory command)
+    ResetEnable = 0x6699,
+    /// Reset device to power-on state, clears volatile settings
+    ResetMemory = 0x9966,
+    /// Protect all sectors using Dynamic Protection Bits (DPB)
+    GangBlockLock = 0x7E81,
+    /// Unprotect all sectors by clearing Dynamic Protection Bits (DPB)
+    GangBlockUnlock = 0x9867,
+
+    // Register Access commands
+    /// Read 3-byte device identification with 4-byte dummy address
+    ReadIdentification = 0x9F60,
+    /// Read Serial Flash Discoverable Parameters (SFDP) table with 4-byte address
+    ReadSFDP = 0x5AA5,
+    /// Read 8-bit Status Register with 4-byte dummy address
+    ReadStatusRegister = 0x05FA,
+    /// Read 8-bit Configuration Register with specific address (00000001h)
+    ReadConfigurationRegister = 0x15EA,
+    /// Write 8-bit Status Register with specific address (00000000h) or Configuration Register with address (00000001h)
+    WriteStatusConfigurationRegister = 0x01FE,
+    /// Read Configuration Register 2 from specified 4-byte address
+    ReadConfigurationRegister2 = 0x718E,
+    /// Write Configuration Register 2 to specified 4-byte address
+    WriteConfigurationRegister2 = 0x728D,
+    /// Read 8-bit Security Register with 4-byte dummy address
+    ReadSecurityRegister = 0x2BD4,
+    /// Write Security Register to set customer lock-down bit
+    WriteSecurityRegister = 0x2FD0,
+    /// Set burst/wrap length for read operations with 4-byte dummy address
+    SetBurstLength = 0xC03F,
+    /// Read 32-bit Fast Boot Register with 4-byte dummy address
+    ReadFastBootRegister = 0x16E9,
+    /// Write 32-bit Fast Boot Register with 4-byte dummy address
+    WriteFastBootRegister = 0x17E8,
+    /// Erase Fast Boot Register (disable fast boot feature)
+    EraseFastBootRegister = 0x18E7,
+    /// Enter 8K-bit secured OTP mode for programming unique identifiers
+    EnterSecuredOTP = 0xB14E,
+    /// Exit secured OTP mode and return to main array access
+    ExitSecuredOTP = 0xC13E,
+    /// Write Lock Register to control SPB protection mode with 4-byte dummy address
+    WriteLockRegister = 0x2CD3,
+    /// Read Lock Register status with 4-byte dummy address
+    ReadLockRegister = 0x2DD2,
+    /// Program Solid Protection Bit (SPB) for specified 4-byte address
+    WriteSPB = 0xE31C,
+    /// Erase all Solid Protection Bits (SPB)
+    EraseSPB = 0xE41B,
+    /// Read Solid Protection Bit (SPB) status for specified 4-byte address
+    ReadSPB = 0xE21D,
+    /// Write Dynamic Protection Bit (DPB) for specified 4-byte address
+    WriteDPB = 0xE11E,
+    /// Read Dynamic Protection Bit (DPB) status for specified 4-byte address
+    ReadDPB = 0xE01F,
+    /// Read 64-bit password register with 4-byte dummy address and 20 dummy cycles
+    ReadPassword = 0x27D8,
+    /// Write 64-bit password register with 4-byte dummy address
+    WritePassword = 0x28D7,
+    /// Unlock SPB operations using 64-bit password with 4-byte dummy address
+    PasswordUnlock = 0x29D6,
+}
 
-    async fn qpi_mode(&mut self) {
-        // Enter qpi mode
-        self.exec_command(0x38).await;
+impl<I: Instance> SpiFlashMemory<I> {
+    pub fn new(xspi: Xspi<'static, I, Blocking>) -> Self {
+        let mut memory = Self { xspi };
 
-        // Set read param
-        let transaction = TransferConfig {
-            iwidth: XspiWidth::QUAD,
-            dwidth: XspiWidth::QUAD,
-            instruction: Some(0xC0),
-            ..Default::default()
-        };
-        self.enable_write().await;
-        self.xspi.blocking_write(&[0x30_u8], transaction).unwrap();
-        self.wait_write_finish();
+        memory.reset_memory();
+        memory
     }
 
-    pub async fn disable_mm(&mut self) {
+    pub fn disable_mm(&mut self) {
         self.xspi.disable_memory_mapped_mode();
     }
 
-    pub async fn enable_mm(&mut self) {
-        self.qpi_mode().await;
-
+    pub fn enable_mm(&mut self) {
         let read_config = TransferConfig {
             iwidth: XspiWidth::SING,
             isize: AddressSize::_8bit,
             adwidth: XspiWidth::SING,
-            adsize: AddressSize::_24bit,
+            adsize: AddressSize::_32bit,
             dwidth: XspiWidth::SING,
-            instruction: Some(CMD_READ as u32),
+            instruction: Some(SpiCommand::FastRead4B as u32),
             dummy: DummyCycles::_8,
             ..Default::default()
         };
@@ -198,42 +445,28 @@ impl<I: Instance> FlashMemory<I> {
             iwidth: XspiWidth::SING,
             isize: AddressSize::_8bit,
             adwidth: XspiWidth::SING,
-            adsize: AddressSize::_24bit,
+            adsize: AddressSize::_32bit,
             dwidth: XspiWidth::SING,
-            instruction: Some(CMD_WRITE_PG as u32),
+            instruction: Some(SpiCommand::PageProgram4B as u32),
             dummy: DummyCycles::_0,
             ..Default::default()
         };
         self.xspi.enable_memory_mapped_mode(read_config, write_config).unwrap();
     }
 
-    fn enable_octo(&mut self) {
-        let cr = self.read_cr();
-        // info!("Read cr: {:x}", cr);
-        self.write_cr(cr | 0x02);
-        // info!("Read cr after writing: {:x}", cr);
+    fn into_octo(mut self) -> OpiFlashMemory<I> {
+        self.enable_opi_mode();
+        OpiFlashMemory { xspi: self.xspi }
     }
 
-    pub fn disable_octo(&mut self) {
-        let cr = self.read_cr();
-        self.write_cr(cr & (!(0x02)));
-    }
-
-    async fn exec_command_4(&mut self, cmd: u8) {
-        let transaction = TransferConfig {
-            iwidth: XspiWidth::QUAD,
-            adwidth: XspiWidth::NONE,
-            // adsize: AddressSize::_24bit,
-            dwidth: XspiWidth::NONE,
-            instruction: Some(cmd as u32),
-            address: None,
-            dummy: DummyCycles::_0,
-            ..Default::default()
-        };
-        self.xspi.blocking_command(&transaction).unwrap();
+    fn enable_opi_mode(&mut self) {
+        let cr2_0 = self.read_cr2(0);
+        info!("Read CR2 at 0x0: {:x}", cr2_0);
+        self.enable_write();
+        self.write_cr2(0, cr2_0 | 0x01); // Set bit 0 to enable octo SPI in STR
     }
 
-    async fn exec_command(&mut self, cmd: u8) {
+    fn exec_command(&mut self, cmd: u8) {
         let transaction = TransferConfig {
             iwidth: XspiWidth::SING,
             adwidth: XspiWidth::NONE,
@@ -248,16 +481,14 @@ impl<I: Instance> FlashMemory<I> {
         self.xspi.blocking_command(&transaction).unwrap();
     }
 
-    pub async fn reset_memory(&mut self) {
-        self.exec_command_4(CMD_ENABLE_RESET).await;
-        self.exec_command_4(CMD_RESET).await;
-        self.exec_command(CMD_ENABLE_RESET).await;
-        self.exec_command(CMD_RESET).await;
+    pub fn reset_memory(&mut self) {
+        self.exec_command(SpiCommand::ResetEnable as u8);
+        self.exec_command(SpiCommand::ResetMemory as u8);
         self.wait_write_finish();
     }
 
-    pub async fn enable_write(&mut self) {
-        self.exec_command(CMD_WRITE_ENABLE).await;
+    pub fn enable_write(&mut self) {
+        self.exec_command(SpiCommand::WriteEnable as u8);
     }
 
     pub fn read_id(&mut self) -> [u8; 3] {
@@ -266,92 +497,64 @@ impl<I: Instance> FlashMemory<I> {
             iwidth: XspiWidth::SING,
             isize: AddressSize::_8bit,
             adwidth: XspiWidth::NONE,
-            // adsize: AddressSize::_24bit,
             dwidth: XspiWidth::SING,
-            instruction: Some(CMD_READ_ID as u32),
+            instruction: Some(SpiCommand::ReadIdentification as u32),
             ..Default::default()
         };
-        // info!("Reading id: 0x{:X}", transaction.instruction);
         self.xspi.blocking_read(&mut buffer, transaction).unwrap();
         buffer
     }
 
-    pub fn read_id_8(&mut self) -> [u8; 3] {
-        let mut buffer = [0; 3];
-        let transaction: TransferConfig = TransferConfig {
-            iwidth: XspiWidth::OCTO,
-            isize: AddressSize::_16bit,
-            adwidth: XspiWidth::OCTO,
-            address: Some(0),
-            adsize: AddressSize::_32bit,
-            dwidth: XspiWidth::OCTO,
-            instruction: Some(CMD_READ_ID_OCTO as u32),
-            dummy: DummyCycles::_4,
-            ..Default::default()
-        };
-        info!("Reading id: {:#X}", transaction.instruction);
-        self.xspi.blocking_read(&mut buffer, transaction).unwrap();
-        buffer
-    }
-
-    pub fn read_memory(&mut self, addr: u32, buffer: &mut [u8], use_dma: bool) {
+    pub fn read_memory(&mut self, addr: u32, buffer: &mut [u8]) {
         let transaction = TransferConfig {
             iwidth: XspiWidth::SING,
             adwidth: XspiWidth::SING,
-            adsize: AddressSize::_24bit,
+            adsize: AddressSize::_32bit,
             dwidth: XspiWidth::SING,
-            instruction: Some(CMD_READ as u32),
+            instruction: Some(SpiCommand::FastRead4B as u32),
             dummy: DummyCycles::_8,
-            // dwidth: XspiWidth::QUAD,
-            // instruction: Some(CMD_QUAD_READ as u32),
-            // dummy: DummyCycles::_8,
             address: Some(addr),
             ..Default::default()
         };
-        if use_dma {
-            self.xspi.blocking_read(buffer, transaction).unwrap();
-        } else {
-            self.xspi.blocking_read(buffer, transaction).unwrap();
-        }
+
+        self.xspi.blocking_read(buffer, transaction).unwrap();
     }
 
     fn wait_write_finish(&mut self) {
         while (self.read_sr() & 0x01) != 0 {}
     }
 
-    async fn perform_erase(&mut self, addr: u32, cmd: u8) {
+    fn perform_erase(&mut self, addr: u32, cmd: u8) {
         let transaction = TransferConfig {
             iwidth: XspiWidth::SING,
             adwidth: XspiWidth::SING,
-            adsize: AddressSize::_24bit,
+            adsize: AddressSize::_32bit,
             dwidth: XspiWidth::NONE,
             instruction: Some(cmd as u32),
             address: Some(addr),
             dummy: DummyCycles::_0,
             ..Default::default()
         };
-        self.enable_write().await;
+        self.enable_write();
         self.xspi.blocking_command(&transaction).unwrap();
         self.wait_write_finish();
     }
 
-    pub async fn erase_sector(&mut self, addr: u32) {
-        self.perform_erase(addr, CMD_SECTOR_ERASE).await;
+    pub fn erase_sector(&mut self, addr: u32) {
+        self.perform_erase(addr, SpiCommand::SectorErase4B as u8);
     }
 
-    pub async fn erase_block_32k(&mut self, addr: u32) {
-        self.perform_erase(addr, CMD_BLOCK_ERASE_32K).await;
+    pub fn erase_block_64k(&mut self, addr: u32) {
+        self.perform_erase(addr, SpiCommand::BlockErase4B as u8);
     }
 
-    pub async fn erase_block_64k(&mut self, addr: u32) {
-        self.perform_erase(addr, CMD_BLOCK_ERASE_64K).await;
-    }
-
-    pub async fn erase_chip(&mut self) {
-        self.exec_command(CMD_CHIP_ERASE).await;
+    pub fn erase_chip(&mut self) {
+        self.enable_write();
+        self.exec_command(SpiCommand::ChipErase as u8);
+        self.wait_write_finish();
     }
 
-    async fn write_page(&mut self, addr: u32, buffer: &[u8], len: usize, use_dma: bool) {
+    fn write_page(&mut self, addr: u32, buffer: &[u8], len: usize) {
         assert!(
             (len as u32 + (addr & 0x000000ff)) <= MEMORY_PAGE_SIZE as u32,
             "write_page(): page write length exceeds page boundary (len = {}, addr = {:X}",
@@ -361,48 +564,43 @@ impl<I: Instance> FlashMemory<I> {
 
         let transaction = TransferConfig {
             iwidth: XspiWidth::SING,
-            adsize: AddressSize::_24bit,
+            adsize: AddressSize::_32bit,
             adwidth: XspiWidth::SING,
             dwidth: XspiWidth::SING,
-            instruction: Some(CMD_WRITE_PG as u32),
-            // dwidth: XspiWidth::QUAD,
-            // instruction: Some(CMD_QUAD_WRITE_PG as u32),
+            instruction: Some(SpiCommand::PageProgram4B as u32),
             address: Some(addr),
             dummy: DummyCycles::_0,
             ..Default::default()
         };
-        self.enable_write().await;
-        if use_dma {
-            self.xspi.blocking_write(buffer, transaction).unwrap();
-        } else {
-            self.xspi.blocking_write(buffer, transaction).unwrap();
-        }
+        self.enable_write();
+        self.xspi.blocking_write(buffer, transaction).unwrap();
         self.wait_write_finish();
     }
 
-    pub async fn write_memory(&mut self, addr: u32, buffer: &[u8], use_dma: bool) {
+    pub fn write_memory(&mut self, addr: u32, buffer: &[u8]) {
         let mut left = buffer.len();
         let mut place = addr;
         let mut chunk_start = 0;
 
         while left > 0 {
             let max_chunk_size = MEMORY_PAGE_SIZE - (place & 0x000000ff) as usize;
-            let chunk_size = if left >= max_chunk_size { max_chunk_size } else { left };
+            let chunk_size = min(max_chunk_size, left);
             let chunk = &buffer[chunk_start..(chunk_start + chunk_size)];
-            self.write_page(place, chunk, chunk_size, use_dma).await;
+            self.write_page(place, chunk, chunk_size);
             place += chunk_size as u32;
             left -= chunk_size;
             chunk_start += chunk_size;
         }
     }
 
+    // Note: read_register cannot be used to read the configuration register 2 since there is an
+    // address required for that read.
     fn read_register(&mut self, cmd: u8) -> u8 {
         let mut buffer = [0; 1];
         let transaction: TransferConfig = TransferConfig {
             iwidth: XspiWidth::SING,
             isize: AddressSize::_8bit,
             adwidth: XspiWidth::NONE,
-            adsize: AddressSize::_24bit,
             dwidth: XspiWidth::SING,
             instruction: Some(cmd as u32),
             address: None,
@@ -410,39 +608,345 @@ impl<I: Instance> FlashMemory<I> {
             ..Default::default()
         };
         self.xspi.blocking_read(&mut buffer, transaction).unwrap();
-        // info!("Read w25q64 register: 0x{:x}", buffer[0]);
         buffer[0]
     }
 
-    fn write_register(&mut self, cmd: u8, value: u8) {
-        let buffer = [value; 1];
+    pub fn read_sr(&mut self) -> u8 {
+        self.read_register(SpiCommand::ReadStatusRegister as u8)
+    }
+
+    pub fn read_cr(&mut self) -> u8 {
+        self.read_register(SpiCommand::ReadConfigurationRegister as u8)
+    }
+
+    pub fn write_sr_cr(&mut self, sr: u8, cr: u8) {
+        let buffer = [sr, cr];
         let transaction: TransferConfig = TransferConfig {
             iwidth: XspiWidth::SING,
             isize: AddressSize::_8bit,
-            instruction: Some(cmd as u32),
-            adsize: AddressSize::_24bit,
+            instruction: Some(SpiCommand::WriteStatusConfigurationRegister as u32),
             adwidth: XspiWidth::NONE,
             dwidth: XspiWidth::SING,
             address: None,
             dummy: DummyCycles::_0,
             ..Default::default()
         };
+        self.enable_write();
+        self.xspi.blocking_write(&buffer, transaction).unwrap();
+        self.wait_write_finish();
+    }
+
+    pub fn read_cr2(&mut self, address: u32) -> u8 {
+        let mut buffer = [0; 1];
+        let transaction: TransferConfig = TransferConfig {
+            iwidth: XspiWidth::SING,
+            isize: AddressSize::_8bit,
+            instruction: Some(SpiCommand::ReadConfigurationRegister2 as u32),
+            adsize: AddressSize::_32bit,
+            adwidth: XspiWidth::SING,
+            dwidth: XspiWidth::SING,
+            address: Some(address),
+            dummy: DummyCycles::_0,
+            ..Default::default()
+        };
+        self.xspi.blocking_read(&mut buffer, transaction).unwrap();
+        buffer[0]
+    }
+
+    pub fn write_cr2(&mut self, address: u32, value: u8) {
+        let buffer = [value; 1];
+        let transaction: TransferConfig = TransferConfig {
+            iwidth: XspiWidth::SING,
+            isize: AddressSize::_8bit,
+            instruction: Some(SpiCommand::WriteConfigurationRegister2 as u32),
+            adsize: AddressSize::_32bit,
+            adwidth: XspiWidth::SING,
+            dwidth: XspiWidth::SING,
+            address: Some(address),
+            dummy: DummyCycles::_0,
+            ..Default::default()
+        };
         self.xspi.blocking_write(&buffer, transaction).unwrap();
+        self.wait_write_finish();
+    }
+}
+
+impl<I: Instance> OpiFlashMemory<I> {
+    pub fn into_spi(mut self) -> SpiFlashMemory<I> {
+        self.disable_opi_mode();
+        SpiFlashMemory { xspi: self.xspi }
+    }
+
+    /// Disable OPI mode and return to SPI
+    pub fn disable_opi_mode(&mut self) {
+        // Clear SOPI and DOPI bits in CR2 volatile register
+        let cr2_0 = self.read_cr2(0x00000000);
+        self.write_cr2(0x00000000, cr2_0 & 0xFC); // Clear bits 0 and 1
+    }
+
+    /// Enable memory-mapped mode for OPI
+    pub fn enable_mm(&mut self) {
+        let read_config = TransferConfig {
+            iwidth: XspiWidth::OCTO,
+            isize: AddressSize::_16bit, // 2-byte command for OPI
+            adwidth: XspiWidth::OCTO,
+            adsize: AddressSize::_32bit,
+            dwidth: XspiWidth::OCTO,
+            instruction: Some(OpiCommand::OctaRead as u32),
+            dummy: DummyCycles::_20, // Default dummy cycles for OPI
+            ..Default::default()
+        };
+
+        let write_config = TransferConfig {
+            iwidth: XspiWidth::OCTO,
+            isize: AddressSize::_16bit,
+            adwidth: XspiWidth::OCTO,
+            adsize: AddressSize::_32bit,
+            dwidth: XspiWidth::OCTO,
+            instruction: Some(OpiCommand::PageProgram4B as u32),
+            dummy: DummyCycles::_0,
+            ..Default::default()
+        };
+
+        self.xspi.enable_memory_mapped_mode(read_config, write_config).unwrap();
+    }
+
+    pub fn disable_mm(&mut self) {
+        self.xspi.disable_memory_mapped_mode();
+    }
+
+    /// Execute OPI command (2-byte command)
+    fn exec_command(&mut self, cmd: OpiCommand) {
+        let transaction = TransferConfig {
+            iwidth: XspiWidth::OCTO,
+            isize: AddressSize::_16bit, // 2-byte command
+            adwidth: XspiWidth::NONE,
+            dwidth: XspiWidth::NONE,
+            instruction: Some(cmd as u32),
+            address: None,
+            dummy: DummyCycles::_0,
+            ..Default::default()
+        };
+        self.xspi.blocking_command(&transaction).unwrap();
+    }
+
+    /// Reset memory using OPI commands
+    pub fn reset_memory(&mut self) {
+        self.exec_command(OpiCommand::ResetEnable);
+        self.exec_command(OpiCommand::ResetMemory);
+        self.wait_write_finish();
     }
 
+    /// Enable write using OPI command
+    pub fn enable_write(&mut self) {
+        self.exec_command(OpiCommand::WriteEnable);
+    }
+
+    /// Read device ID in OPI mode
+    pub fn read_id(&mut self) -> [u8; 3] {
+        let mut buffer = [0; 3];
+        let transaction = TransferConfig {
+            iwidth: XspiWidth::OCTO,
+            isize: AddressSize::_16bit,
+            adwidth: XspiWidth::OCTO,
+            adsize: AddressSize::_32bit,
+            dwidth: XspiWidth::OCTO,
+            instruction: Some(OpiCommand::ReadIdentification as u32),
+            address: Some(0x00000000), // Dummy address required
+            dummy: DummyCycles::_4,
+            ..Default::default()
+        };
+        self.xspi.blocking_read(&mut buffer, transaction).unwrap();
+        buffer
+    }
+
+    /// Read memory using OPI mode
+    pub fn read_memory(&mut self, addr: u32, buffer: &mut [u8]) {
+        let transaction = TransferConfig {
+            iwidth: XspiWidth::OCTO,
+            isize: AddressSize::_16bit,
+            adwidth: XspiWidth::OCTO,
+            adsize: AddressSize::_32bit,
+            dwidth: XspiWidth::OCTO,
+            instruction: Some(OpiCommand::OctaRead as u32),
+            address: Some(addr),
+            dummy: DummyCycles::_20, // Default for 200MHz operation
+            ..Default::default()
+        };
+        self.xspi.blocking_read(buffer, transaction).unwrap();
+    }
+
+    /// Wait for write completion using OPI status read
+    fn wait_write_finish(&mut self) {
+        while (self.read_sr() & 0x01) != 0 {}
+    }
+
+    /// Perform erase operation using OPI command
+    fn perform_erase(&mut self, addr: u32, cmd: OpiCommand) {
+        let transaction = TransferConfig {
+            iwidth: XspiWidth::OCTO,
+            isize: AddressSize::_16bit,
+            adwidth: XspiWidth::OCTO,
+            adsize: AddressSize::_32bit,
+            dwidth: XspiWidth::NONE,
+            instruction: Some(cmd as u32),
+            address: Some(addr),
+            dummy: DummyCycles::_0,
+            ..Default::default()
+        };
+        self.enable_write();
+        self.xspi.blocking_command(&transaction).unwrap();
+        self.wait_write_finish();
+    }
+
+    /// Erase 4KB sector using OPI
+    pub fn erase_sector(&mut self, addr: u32) {
+        self.perform_erase(addr, OpiCommand::SectorErase4B);
+    }
+
+    /// Erase 64KB block using OPI
+    pub fn erase_block_64k(&mut self, addr: u32) {
+        self.perform_erase(addr, OpiCommand::BlockErase4B);
+    }
+
+    /// Erase entire chip using OPI
+    pub fn erase_chip(&mut self) {
+        self.enable_write();
+        self.exec_command(OpiCommand::ChipErase);
+        self.wait_write_finish();
+    }
+
+    /// Write single page using OPI
+    fn write_page(&mut self, addr: u32, buffer: &[u8], len: usize) {
+        assert!(
+            (len as u32 + (addr & 0x000000ff)) <= MEMORY_PAGE_SIZE as u32,
+            "write_page(): page write length exceeds page boundary (len = {}, addr = {:X})",
+            len,
+            addr
+        );
+
+        let transaction = TransferConfig {
+            iwidth: XspiWidth::OCTO,
+            isize: AddressSize::_16bit,
+            adwidth: XspiWidth::OCTO,
+            adsize: AddressSize::_32bit,
+            dwidth: XspiWidth::OCTO,
+            instruction: Some(OpiCommand::PageProgram4B as u32),
+            address: Some(addr),
+            dummy: DummyCycles::_0,
+            ..Default::default()
+        };
+        self.enable_write();
+        self.xspi.blocking_write(buffer, transaction).unwrap();
+        self.wait_write_finish();
+    }
+
+    /// Write memory using OPI (handles page boundaries)
+    pub fn write_memory(&mut self, addr: u32, buffer: &[u8]) {
+        let mut left = buffer.len();
+        let mut place = addr;
+        let mut chunk_start = 0;
+
+        while left > 0 {
+            let max_chunk_size = MEMORY_PAGE_SIZE - (place & 0x000000ff) as usize;
+            let chunk_size = min(max_chunk_size, left);
+            let chunk = &buffer[chunk_start..(chunk_start + chunk_size)];
+            self.write_page(place, chunk, chunk_size);
+            place += chunk_size as u32;
+            left -= chunk_size;
+            chunk_start += chunk_size;
+        }
+    }
+
+    /// Read register using OPI mode
+    fn read_register(&mut self, cmd: OpiCommand, dummy_addr: u32, dummy_cycles: DummyCycles) -> u8 {
+        let mut buffer = [0; 1];
+        let transaction = TransferConfig {
+            iwidth: XspiWidth::OCTO,
+            isize: AddressSize::_16bit,
+            adwidth: XspiWidth::OCTO,
+            adsize: AddressSize::_32bit,
+            dwidth: XspiWidth::OCTO,
+            instruction: Some(cmd as u32),
+            address: Some(dummy_addr),
+            dummy: dummy_cycles,
+            ..Default::default()
+        };
+        self.xspi.blocking_read(&mut buffer, transaction).unwrap();
+        buffer[0]
+    }
+
+    /// Read Status Register using OPI
     pub fn read_sr(&mut self) -> u8 {
-        self.read_register(CMD_READ_SR)
+        self.read_register(
+            OpiCommand::ReadStatusRegister,
+            0x00000000, // Dummy address
+            DummyCycles::_4,
+        )
     }
 
+    /// Read Configuration Register using OPI
     pub fn read_cr(&mut self) -> u8 {
-        self.read_register(CMD_READ_CR)
+        self.read_register(
+            OpiCommand::ReadConfigurationRegister,
+            0x00000001, // Address for CR
+            DummyCycles::_4,
+        )
     }
 
-    pub fn write_sr(&mut self, value: u8) {
-        self.write_register(CMD_WRITE_SR, value);
+    /// Write Status/Configuration Register using OPI
+    pub fn write_sr_cr(&mut self, sr: u8, cr: u8) {
+        let transaction = TransferConfig {
+            iwidth: XspiWidth::OCTO,
+            isize: AddressSize::_16bit,
+            adwidth: XspiWidth::OCTO,
+            adsize: AddressSize::_32bit,
+            dwidth: XspiWidth::OCTO,
+            instruction: Some(OpiCommand::WriteStatusConfigurationRegister as u32),
+            address: Some(0x00000000),
+            dummy: DummyCycles::_0,
+            ..Default::default()
+        };
+
+        self.enable_write();
+        self.xspi.blocking_write(&[sr, cr], transaction).unwrap();
+        self.wait_write_finish();
+    }
+
+    /// Read Configuration Register 2 using OPI
+    pub fn read_cr2(&mut self, address: u32) -> u8 {
+        let mut buffer = [0; 1];
+        let transaction = TransferConfig {
+            iwidth: XspiWidth::OCTO,
+            isize: AddressSize::_16bit,
+            adwidth: XspiWidth::OCTO,
+            adsize: AddressSize::_32bit,
+            dwidth: XspiWidth::OCTO,
+            instruction: Some(OpiCommand::ReadConfigurationRegister2 as u32),
+            address: Some(address),
+            dummy: DummyCycles::_4,
+            ..Default::default()
+        };
+        self.xspi.blocking_read(&mut buffer, transaction).unwrap();
+        buffer[0]
     }
 
-    pub fn write_cr(&mut self, value: u8) {
-        self.write_register(CMD_WRITE_CR, value);
+    /// Write Configuration Register 2 using OPI
+    pub fn write_cr2(&mut self, address: u32, value: u8) {
+        let transaction = TransferConfig {
+            iwidth: XspiWidth::OCTO,
+            isize: AddressSize::_16bit,
+            adwidth: XspiWidth::OCTO,
+            adsize: AddressSize::_32bit,
+            dwidth: XspiWidth::OCTO,
+            instruction: Some(OpiCommand::WriteConfigurationRegister2 as u32),
+            address: Some(address),
+            dummy: DummyCycles::_0,
+            ..Default::default()
+        };
+
+        self.enable_write();
+        self.xspi.blocking_write(&[value], transaction).unwrap();
+        self.wait_write_finish();
     }
 }
diff --git a/examples/stm32l0/src/bin/dds.rs b/examples/stm32l0/src/bin/dds.rs
index a54b28a93..eaa7a61a8 100644
--- a/examples/stm32l0/src/bin/dds.rs
+++ b/examples/stm32l0/src/bin/dds.rs
@@ -11,7 +11,7 @@ use embassy_stm32::rcc::*;
 use embassy_stm32::time::hz;
 use embassy_stm32::timer::low_level::{Timer as LLTimer, *};
 use embassy_stm32::timer::simple_pwm::PwmPin;
-use embassy_stm32::timer::Channel;
+use embassy_stm32::timer::{Ch3, Channel};
 use embassy_stm32::{interrupt, pac, Config};
 use panic_probe as _;
 
@@ -70,7 +70,7 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(config);
 
     // setup PWM pin in AF mode
-    let _ch3 = PwmPin::new_ch3(p.PA2, OutputType::PushPull);
+    let _ch3 = PwmPin::<_, Ch3>::new(p.PA2, OutputType::PushPull);
 
     // initialize timer
     // we cannot use SimplePWM here because the Time is privately encapsulated
diff --git a/examples/stm32l1/Cargo.toml b/examples/stm32l1/Cargo.toml
index a0a7916a7..5d5d401f6 100644
--- a/examples/stm32l1/Cargo.toml
+++ b/examples/stm32l1/Cargo.toml
@@ -9,7 +9,7 @@ embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["de
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = [ "defmt", "stm32l151cb-a", "time-driver-any", "memory-x"]  }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32l4/Cargo.toml b/examples/stm32l4/Cargo.toml
index 7da09e5b0..a6b4efcf8 100644
--- a/examples/stm32l4/Cargo.toml
+++ b/examples/stm32l4/Cargo.toml
@@ -10,8 +10,8 @@ embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = [
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768", ] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../embassy-embedded-hal" }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-embedded-hal = { version = "0.3.1", path = "../../embassy-embedded-hal" }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-net-adin1110 = { version = "0.3.0", path = "../../embassy-net-adin1110" }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt",  "udp", "tcp", "dhcpv4", "medium-ethernet"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
diff --git a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
index 354ac90b2..dc90a3b85 100644
--- a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
+++ b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
@@ -59,7 +59,7 @@ pub type SpeSpiCs = ExclusiveDevice<SpeSpi, Output<'static>, Delay>;
 pub type SpeInt = exti::ExtiInput<'static>;
 pub type SpeRst = Output<'static>;
 pub type Adin1110T = ADIN1110<SpeSpiCs>;
-pub type TempSensI2c = I2c<'static, Async>;
+pub type TempSensI2c = I2c<'static, Async, i2c::Master>;
 
 static TEMP: AtomicI32 = AtomicI32::new(0);
 
diff --git a/examples/stm32l432/src/bin/qspi_mmap.rs b/examples/stm32l432/src/bin/qspi_mmap.rs
index 86a20eb3d..075458fe5 100644
--- a/examples/stm32l432/src/bin/qspi_mmap.rs
+++ b/examples/stm32l432/src/bin/qspi_mmap.rs
@@ -7,7 +7,7 @@
 use defmt::info;
 use embassy_stm32::mode;
 use embassy_stm32::qspi::enums::{
-    AddressSize, ChipSelectHighTime, DummyCycles, FIFOThresholdLevel, MemorySize, QspiWidth,
+    AddressSize, ChipSelectHighTime, DummyCycles, FIFOThresholdLevel, MemorySize, QspiWidth, SampleShifting,
 };
 use embassy_stm32::qspi::{self, Instance, TransferConfig};
 pub struct FlashMemory<I: Instance> {
@@ -252,6 +252,7 @@ async fn main(_spawner: Spawner) {
         prescaler: 200,
         cs_high_time: ChipSelectHighTime::_1Cycle,
         fifo_threshold: FIFOThresholdLevel::_16Bytes,
+        sample_shifting: SampleShifting::None,
     };
     let driver = qspi::Qspi::new_bank1(p.QUADSPI, p.PB1, p.PB0, p.PA7, p.PA6, p.PA3, p.PA2, p.DMA2_CH7, config);
     let mut flash = FlashMemory::new(driver);
diff --git a/examples/stm32l5/Cargo.toml b/examples/stm32l5/Cargo.toml
index 3ea3bcd5c..1379d963c 100644
--- a/examples/stm32l5/Cargo.toml
+++ b/examples/stm32l5/Cargo.toml
@@ -10,7 +10,7 @@ embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = [
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt",  "tcp", "dhcpv4", "medium-ethernet"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 usbd-hid = "0.8.1"
diff --git a/examples/stm32u0/Cargo.toml b/examples/stm32u0/Cargo.toml
index 3aa45dc79..612d12ac2 100644
--- a/examples/stm32u0/Cargo.toml
+++ b/examples/stm32u0/Cargo.toml
@@ -10,7 +10,7 @@ embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = [
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", default-features = false, features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", default-features = false, features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32u5/Cargo.toml b/examples/stm32u5/Cargo.toml
index 777d3ed4c..f92e85852 100644
--- a/examples/stm32u5/Cargo.toml
+++ b/examples/stm32u5/Cargo.toml
@@ -10,7 +10,7 @@ embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = ["
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] }
+embassy-usb = { version = "0.5.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 
 defmt = "1.0.1"
diff --git a/examples/stm32wb/src/bin/gatt_server.rs b/examples/stm32wb/src/bin/gatt_server.rs
index 041dc0cf5..9864fa026 100644
--- a/examples/stm32wb/src/bin/gatt_server.rs
+++ b/examples/stm32wb/src/bin/gatt_server.rs
@@ -27,6 +27,7 @@ use embassy_stm32_wpan::hci::vendor::event::{self, AttributeHandle, VendorEvent}
 use embassy_stm32_wpan::hci::{BdAddr, Event};
 use embassy_stm32_wpan::lhci::LhciC1DeviceInformationCcrp;
 use embassy_stm32_wpan::sub::ble::Ble;
+use embassy_stm32_wpan::sub::mm;
 use embassy_stm32_wpan::TlMbox;
 use {defmt_rtt as _, panic_probe as _};
 
@@ -38,7 +39,7 @@ bind_interrupts!(struct Irqs{
 const BLE_GAP_DEVICE_NAME_LENGTH: u8 = 7;
 
 #[embassy_executor::main]
-async fn main(_spawner: Spawner) {
+async fn main(spawner: Spawner) {
     /*
         How to make this work:
 
@@ -70,6 +71,7 @@ async fn main(_spawner: Spawner) {
     let config = Config::default();
     let mut mbox = TlMbox::init(p.IPCC, Irqs, config);
 
+    spawner.spawn(run_mm_queue(mbox.mm_subsystem)).unwrap();
     let sys_event = mbox.sys_subsystem.read().await;
     info!("sys event: {}", sys_event.payload());
 
@@ -221,6 +223,11 @@ async fn main(_spawner: Spawner) {
     }
 }
 
+#[embassy_executor::task]
+async fn run_mm_queue(memory_manager: mm::MemoryManager) {
+    memory_manager.run_queue().await;
+}
+
 fn get_bd_addr() -> BdAddr {
     let mut bytes = [0u8; 6];
 
diff --git a/examples/stm32wba/src/bin/adc.rs b/examples/stm32wba/src/bin/adc.rs
new file mode 100644
index 000000000..a9651d57e
--- /dev/null
+++ b/examples/stm32wba/src/bin/adc.rs
@@ -0,0 +1,49 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_stm32::adc::{adc4, AdcChannel};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: embassy_executor::Spawner) {
+    let config = embassy_stm32::Config::default();
+
+    let mut p = embassy_stm32::init(config);
+
+    // **** ADC4 init ****
+    let mut adc4 = adc4::Adc4::new(p.ADC4);
+    let mut adc4_pin1 = p.PA0; // A4
+    let mut adc4_pin2 = p.PA1; // A5
+    adc4.set_resolution(adc4::Resolution::BITS12);
+    adc4.set_averaging(adc4::Averaging::Samples256);
+    adc4.set_sample_time(adc4::SampleTime::CYCLES1_5);
+    let max4 = adc4::resolution_to_max_count(adc4::Resolution::BITS12);
+
+    // **** ADC4 blocking read ****
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin1);
+    let volt: f32 = 3.0 * raw as f32 / max4 as f32;
+    info!("Read adc4 pin 1 {}", volt);
+
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin2);
+    let volt: f32 = 3.3 * raw as f32 / max4 as f32;
+    info!("Read adc4 pin 2 {}", volt);
+
+    // **** ADC4 async read ****
+    let mut degraded41 = adc4_pin1.degrade_adc();
+    let mut degraded42 = adc4_pin2.degrade_adc();
+    let mut measurements = [0u16; 2];
+
+    // The channels must be in ascending order and can't repeat for ADC4
+    adc4.read(
+        p.GPDMA1_CH1.reborrow(),
+        [&mut degraded42, &mut degraded41].into_iter(),
+        &mut measurements,
+    )
+    .await
+    .unwrap();
+    let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32;
+    let volt1: f32 = 3.0 * measurements[1] as f32 / max4 as f32;
+    info!("Async read 4 pin 1 {}", volt1);
+    info!("Async read 4 pin 2 {}", volt2);
+}
diff --git a/examples/stm32wl/Cargo.toml b/examples/stm32wl/Cargo.toml
index 5ecd77443..1c5d9c07a 100644
--- a/examples/stm32wl/Cargo.toml
+++ b/examples/stm32wl/Cargo.toml
@@ -10,7 +10,7 @@ embassy-stm32 = { version = "0.2.0", path = "../../embassy-stm32", features = ["
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../embassy-embedded-hal" }
+embassy-embedded-hal = { version = "0.3.1", path = "../../embassy-embedded-hal" }
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
diff --git a/release/bump-dependency.sh b/release/bump-dependency.sh
index 07511d229..97f73cddc 100755
--- a/release/bump-dependency.sh
+++ b/release/bump-dependency.sh
@@ -8,4 +8,4 @@
 #
 CRATE=$1
 TARGET_VER=$2
-find . -name "Cargo.toml" | xargs sed -rie "s/($CRATE = \{.*version = \")[0-9]+.[0-9]+.?[0-9]*(\".*)/\1$TARGET_VER\2/g"
+find . -name "Cargo.toml" | xargs sed -ri "s/($CRATE = \{.*version = \")[0-9]+.[0-9]+.?[0-9]*(\".*)/\1$TARGET_VER\2/g"
diff --git a/rust-toolchain-nightly.toml b/rust-toolchain-nightly.toml
index e75ea40cc..411cc6946 100644
--- a/rust-toolchain-nightly.toml
+++ b/rust-toolchain-nightly.toml
@@ -1,5 +1,5 @@
 [toolchain]
-channel = "nightly-2025-03-12"
+channel = "nightly-2025-06-29"
 components = [ "rust-src", "rustfmt", "llvm-tools", "miri" ]
 targets = [
     "thumbv7em-none-eabi",
diff --git a/rust-toolchain.toml b/rust-toolchain.toml
index 870904c3a..e24864037 100644
--- a/rust-toolchain.toml
+++ b/rust-toolchain.toml
@@ -1,5 +1,5 @@
 [toolchain]
-channel = "1.85"
+channel = "1.88"
 components = [ "rust-src", "rustfmt", "llvm-tools" ]
 targets = [
     "thumbv7em-none-eabi",
diff --git a/tests/mspm0/Cargo.toml b/tests/mspm0/Cargo.toml
index 298522d09..5ba3e586b 100644
--- a/tests/mspm0/Cargo.toml
+++ b/tests/mspm0/Cargo.toml
@@ -6,15 +6,17 @@ license = "MIT OR Apache-2.0"
 
 [features]
 mspm0g3507 = [ "embassy-mspm0/mspm0g3507pm" ]
+mspm0g3519 = [ "embassy-mspm0/mspm0g3519pz" ]
 
 [dependencies]
 teleprobe-meta = "1.1"
 
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = [ "defmt" ] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = [ "arch-cortex-m", "executor-thread", "defmt" ] }
+embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = [ "defmt" ] }
 embassy-mspm0 = { version = "0.1.0", path = "../../embassy-mspm0", features = [ "rt", "defmt", "unstable-pac", "time-driver-any" ]  }
-embassy-embedded-hal = { version = "0.3.0", path = "../../embassy-embedded-hal/"}
+embassy-embedded-hal = { version = "0.3.1", path = "../../embassy-embedded-hal/"}
 
 defmt = "1.0.1"
 defmt-rtt = "1.0.0"
@@ -23,6 +25,8 @@ cortex-m = { version = "0.7.6", features = [ "inline-asm", "critical-section-sin
 cortex-m-rt = "0.7.0"
 embedded-hal = { package = "embedded-hal", version = "1.0" }
 embedded-hal-async = { version = "1.0" }
+embedded-io = { version = "0.6.1", features = ["defmt-03"] }
+embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
 panic-probe = { version = "1.0.0", features = ["print-defmt"] }
 static_cell = "2"
 portable-atomic = { version = "1.5", features = ["critical-section"] }
diff --git a/tests/mspm0/build.rs b/tests/mspm0/build.rs
index 0b58fb9e9..43a9ac04f 100644
--- a/tests/mspm0/build.rs
+++ b/tests/mspm0/build.rs
@@ -8,6 +8,9 @@ fn main() -> Result<(), Box<dyn Error>> {
     #[cfg(feature = "mspm0g3507")]
     let memory_x = include_bytes!("memory_g3507.x");
 
+    #[cfg(feature = "mspm0g3519")]
+    let memory_x = include_bytes!("memory_g3519.x");
+
     fs::write(out.join("memory.x"), memory_x).unwrap();
 
     println!("cargo:rustc-link-search={}", out.display());
diff --git a/tests/mspm0/memory_g3519.x b/tests/mspm0/memory_g3519.x
new file mode 100644
index 000000000..d62f10360
--- /dev/null
+++ b/tests/mspm0/memory_g3519.x
@@ -0,0 +1,6 @@
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 128K
+  /* Select non-parity range of SRAM due to SRAM_ERR_01 errata in SLAZ758 */
+  RAM   : ORIGIN = 0x20200000, LENGTH = 64K
+}
diff --git a/tests/mspm0/src/bin/dma.rs b/tests/mspm0/src/bin/dma.rs
new file mode 100644
index 000000000..6fd973a18
--- /dev/null
+++ b/tests/mspm0/src/bin/dma.rs
@@ -0,0 +1,503 @@
+#![no_std]
+#![no_main]
+
+#[cfg(feature = "mspm0g3507")]
+teleprobe_meta::target!(b"lp-mspm0g3507");
+
+#[cfg(feature = "mspm0g3519")]
+teleprobe_meta::target!(b"lp-mspm0g3519");
+
+use core::slice;
+
+use defmt::{assert, assert_eq, *};
+use embassy_executor::Spawner;
+use embassy_mspm0::dma::{Channel, Transfer, TransferMode, TransferOptions, Word};
+use embassy_mspm0::Peri;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut p = embassy_mspm0::init(Default::default());
+    info!("Hello World!");
+
+    {
+        info!("Single u8 read (blocking)");
+        single_read(p.DMA_CH0.reborrow(), 0x41_u8);
+
+        info!("Single u16 read (blocking)");
+        single_read(p.DMA_CH0.reborrow(), 0xFF41_u16);
+
+        info!("Single u32 read (blocking)");
+        single_read(p.DMA_CH0.reborrow(), 0xFFEE_FF41_u32);
+
+        info!("Single u64 read (blocking)");
+        single_read(p.DMA_CH0.reborrow(), 0x0011_2233_FFEE_FF41_u64);
+    }
+
+    // Widening transfers
+    {
+        info!("Single u8 read to u16");
+        widening_single_read::<u8, u16>(p.DMA_CH0.reborrow(), 0x41);
+
+        info!("Single u8 read to u32");
+        widening_single_read::<u8, u32>(p.DMA_CH0.reborrow(), 0x43);
+
+        info!("Single u8 read to u64");
+        widening_single_read::<u8, u64>(p.DMA_CH0.reborrow(), 0x47);
+
+        info!("Single u16 read to u32");
+        widening_single_read::<u16, u32>(p.DMA_CH0.reborrow(), 0xAE43);
+
+        info!("Single u16 read to u64");
+        widening_single_read::<u16, u64>(p.DMA_CH0.reborrow(), 0xAF47);
+
+        info!("Single u32 read to u64");
+        widening_single_read::<u32, u64>(p.DMA_CH0.reborrow(), 0xDEAD_AF47);
+    }
+
+    // Narrowing transfers.
+    {
+        info!("Single u16 read to u8");
+        narrowing_single_read::<u16, u8>(p.DMA_CH0.reborrow(), 0x4142);
+
+        info!("Single u32 read to u8");
+        narrowing_single_read::<u32, u8>(p.DMA_CH0.reborrow(), 0x4142_2414);
+
+        info!("Single u64 read to u8");
+        narrowing_single_read::<u64, u8>(p.DMA_CH0.reborrow(), 0x4142_2414_5153_7776);
+
+        info!("Single u32 read to u16");
+        narrowing_single_read::<u32, u16>(p.DMA_CH0.reborrow(), 0x4142_2414);
+
+        info!("Single u64 read to u16");
+        narrowing_single_read::<u64, u16>(p.DMA_CH0.reborrow(), 0x4142_2414_5153_7776);
+
+        info!("Single u64 read to u32");
+        narrowing_single_read::<u64, u32>(p.DMA_CH0.reborrow(), 0x4142_2414_5153_7776);
+    }
+
+    {
+        info!("Single u8 read (async)");
+        async_single_read(p.DMA_CH0.reborrow(), 0x42_u8).await;
+
+        info!("Single u16 read (async)");
+        async_single_read(p.DMA_CH0.reborrow(), 0xAE42_u16).await;
+
+        info!("Single u32 read (async)");
+        async_single_read(p.DMA_CH0.reborrow(), 0xFE44_1500_u32).await;
+
+        info!("Single u64 read (async)");
+        async_single_read(p.DMA_CH0.reborrow(), 0x8F7F_6F5F_4F3F_2F1F_u64).await;
+    }
+
+    {
+        info!("Multiple u8 reads (blocking)");
+        block_read::<_, 16>(p.DMA_CH0.reborrow(), 0x98_u8);
+
+        info!("Multiple u16 reads (blocking)");
+        block_read::<_, 2>(p.DMA_CH0.reborrow(), 0x9801_u16);
+
+        info!("Multiple u32 reads (blocking)");
+        block_read::<_, 4>(p.DMA_CH0.reborrow(), 0x9821_9801_u32);
+
+        info!("Multiple u64 reads (blocking)");
+        block_read::<_, 4>(p.DMA_CH0.reborrow(), 0xABCD_EF01_2345_6789_u64);
+    }
+
+    {
+        info!("Multiple u8 reads (async)");
+        async_block_read::<_, 8>(p.DMA_CH0.reborrow(), 0x86_u8).await;
+
+        info!("Multiple u16 reads (async)");
+        async_block_read::<_, 6>(p.DMA_CH0.reborrow(), 0x7777_u16).await;
+
+        info!("Multiple u32 reads (async)");
+        async_block_read::<_, 3>(p.DMA_CH0.reborrow(), 0xA5A5_A5A5_u32).await;
+
+        info!("Multiple u64 reads (async)");
+        async_block_read::<_, 14>(p.DMA_CH0.reborrow(), 0x5A5A_5A5A_A5A5_A5A5_u64).await;
+    }
+
+    // Intentionally skip testing multiple reads in single transfer mode.
+    //
+    // If the destination length is greater than 1 and single transfer mode is used then two transfers
+    // are performed in a trigger. Similarly with any other length of destination above 2, only 2 transfers
+    // are performed. Issuing another trigger (resume) results in no further progress. More than likely
+    // the test does not work due to some combination of a hardware bug and the datasheet being unclear
+    // regarding what ends a software trigger.
+    //
+    // However this case works fine with a hardware trigger (such as the ADC hardware trigger).
+
+    {
+        info!("Single u8 write (blocking)");
+        single_write(p.DMA_CH0.reborrow(), 0x41_u8);
+
+        info!("Single u16 write (blocking)");
+        single_write(p.DMA_CH0.reborrow(), 0x4142_u16);
+
+        info!("Single u32 write (blocking)");
+        single_write(p.DMA_CH0.reborrow(), 0x4142_4344_u32);
+
+        info!("Single u64 write (blocking)");
+        single_write(p.DMA_CH0.reborrow(), 0x4142_4344_4546_4748_u64);
+    }
+
+    {
+        info!("Single u8 write (async)");
+        async_single_write(p.DMA_CH0.reborrow(), 0xAA_u8).await;
+
+        info!("Single u16 write (async)");
+        async_single_write(p.DMA_CH0.reborrow(), 0xBBBB_u16).await;
+
+        info!("Single u32 write (async)");
+        async_single_write(p.DMA_CH0.reborrow(), 0xCCCC_CCCC_u32).await;
+
+        info!("Single u64 write (async)");
+        async_single_write(p.DMA_CH0.reborrow(), 0xDDDD_DDDD_DDDD_DDDD_u64).await;
+    }
+
+    {
+        info!("Multiple u8 writes (blocking)");
+        block_write(p.DMA_CH0.reborrow(), &[0xFF_u8, 0x7F, 0x3F, 0x1F]);
+
+        info!("Multiple u16 writes (blocking)");
+        block_write(p.DMA_CH0.reborrow(), &[0xFFFF_u16, 0xFF7F, 0xFF3F, 0xFF1F]);
+
+        info!("Multiple u32 writes (blocking)");
+        block_write(
+            p.DMA_CH0.reborrow(),
+            &[0xFF00_00FF_u32, 0xFF00_007F, 0x0000_FF3F, 0xFF1F_0000],
+        );
+
+        info!("Multiple u64 writes (blocking)");
+        block_write(
+            p.DMA_CH0.reborrow(),
+            &[
+                0xFF00_0000_0000_00FF_u64,
+                0x0000_FF00_007F_0000,
+                0x0000_FF3F_0000_0000,
+                0xFF1F_0000_1111_837A,
+            ],
+        );
+    }
+
+    {
+        info!("Multiple u8 writes (async)");
+        async_block_write(p.DMA_CH0.reborrow(), &[0u8, 1, 2, 3]).await;
+
+        info!("Multiple u16 writes (async)");
+        async_block_write(p.DMA_CH0.reborrow(), &[0x9801u16, 0x9802, 0x9803, 0x9800, 0x9000]).await;
+
+        info!("Multiple u32 writes (async)");
+        async_block_write(p.DMA_CH0.reborrow(), &[0x9801_ABCDu32, 0xFFAC_9802, 0xDEAD_9803]).await;
+
+        info!("Multiple u64 writes (async)");
+        async_block_write(
+            p.DMA_CH0.reborrow(),
+            &[
+                0xA55A_1111_3333_5555_u64,
+                0x1111_A55A_3333_5555,
+                0x5555_A55A_3333_1111,
+                0x01234_5678_89AB_CDEF,
+            ],
+        )
+        .await;
+    }
+
+    // TODO: Mixed byte and word transfers.
+
+    info!("Test OK");
+    cortex_m::asm::bkpt();
+}
+
+fn single_read<W: Word + Copy + Default + Eq + defmt::Format>(mut channel: Peri<'_, impl Channel>, mut src: W) {
+    let options = TransferOptions::default();
+    let mut dst = W::default();
+
+    // SAFETY: src and dst outlive the transfer.
+    let transfer = unsafe {
+        unwrap!(Transfer::new_read(
+            channel.reborrow(),
+            Transfer::SOFTWARE_TRIGGER,
+            &mut src,
+            slice::from_mut(&mut dst),
+            options,
+        ))
+    };
+    transfer.blocking_wait();
+
+    assert_eq!(src, dst);
+}
+
+async fn async_single_read<W: Word + Copy + Default + Eq + defmt::Format>(
+    mut channel: Peri<'_, impl Channel>,
+    mut src: W,
+) {
+    let options = TransferOptions::default();
+    let mut dst = W::default();
+
+    // SAFETY: src and dst outlive the transfer.
+    let transfer = unsafe {
+        unwrap!(Transfer::new_read(
+            channel.reborrow(),
+            Transfer::SOFTWARE_TRIGGER,
+            &mut src,
+            slice::from_mut(&mut dst),
+            options,
+        ))
+    };
+    transfer.await;
+
+    assert_eq!(src, dst);
+}
+
+fn block_read<W: Word + Copy + Default + Eq + defmt::Format, const N: usize>(
+    mut channel: Peri<'_, impl Channel>,
+    mut src: W,
+) {
+    let mut options = TransferOptions::default();
+    // Complete the entire transfer.
+    options.mode = TransferMode::Block;
+
+    let mut dst = [W::default(); N];
+
+    // SAFETY: src and dst outlive the transfer.
+    let transfer = unsafe {
+        unwrap!(Transfer::new_read(
+            channel.reborrow(),
+            Transfer::SOFTWARE_TRIGGER,
+            &mut src,
+            &mut dst[..],
+            options,
+        ))
+    };
+    transfer.blocking_wait();
+
+    assert_eq!(dst, [src; N]);
+}
+
+async fn async_block_read<W: Word + Copy + Default + Eq + defmt::Format, const N: usize>(
+    mut channel: Peri<'_, impl Channel>,
+    mut src: W,
+) {
+    let mut options = TransferOptions::default();
+    // Complete the entire transfer.
+    options.mode = TransferMode::Block;
+
+    let mut dst = [W::default(); N];
+
+    // SAFETY: src and dst outlive the transfer.
+    let transfer = unsafe {
+        unwrap!(Transfer::new_read(
+            channel.reborrow(),
+            Transfer::SOFTWARE_TRIGGER,
+            &mut src,
+            &mut dst[..],
+            options,
+        ))
+    };
+    transfer.await;
+
+    assert_eq!(dst, [src; N]);
+}
+
+fn single_write<W: Word + Default + Eq + defmt::Format>(mut channel: Peri<'_, impl Channel>, src: W) {
+    let options = TransferOptions::default();
+    let mut dst = W::default();
+
+    // SAFETY: src and dst outlive the transfer.
+    let transfer = unsafe {
+        unwrap!(Transfer::new_write(
+            channel.reborrow(),
+            Transfer::SOFTWARE_TRIGGER,
+            slice::from_ref(&src),
+            &mut dst,
+            options,
+        ))
+    };
+    transfer.blocking_wait();
+
+    assert_eq!(src, dst);
+}
+
+async fn async_single_write<W: Word + Default + Eq + defmt::Format>(mut channel: Peri<'_, impl Channel>, src: W) {
+    let options = TransferOptions::default();
+    let mut dst = W::default();
+
+    // SAFETY: src and dst outlive the transfer.
+    let transfer = unsafe {
+        unwrap!(Transfer::new_write(
+            channel.reborrow(),
+            Transfer::SOFTWARE_TRIGGER,
+            slice::from_ref(&src),
+            &mut dst,
+            options,
+        ))
+    };
+    transfer.await;
+
+    assert_eq!(src, dst);
+}
+
+fn block_write<W: Word + Default + Eq + defmt::Format>(mut channel: Peri<'_, impl Channel>, src: &[W]) {
+    let mut options = TransferOptions::default();
+    // Complete the entire transfer.
+    options.mode = TransferMode::Block;
+
+    let mut dst = W::default();
+
+    // Starting from 1 because a zero length transfer does nothing.
+    for i in 1..src.len() {
+        info!("-> {} write(s)", i);
+
+        // SAFETY: src and dst outlive the transfer.
+        let transfer = unsafe {
+            unwrap!(Transfer::new_write(
+                channel.reborrow(),
+                Transfer::SOFTWARE_TRIGGER,
+                &src[..i],
+                &mut dst,
+                options,
+            ))
+        };
+        transfer.blocking_wait();
+
+        // The result will be the last value written.
+        assert_eq!(dst, src[i - 1]);
+    }
+}
+
+async fn async_block_write<W: Word + Default + Eq + defmt::Format>(mut channel: Peri<'_, impl Channel>, src: &[W]) {
+    let mut options = TransferOptions::default();
+    // Complete the entire transfer.
+    options.mode = TransferMode::Block;
+
+    let mut dst = W::default();
+
+    // Starting from 1 because a zero length transfer does nothing.
+    for i in 1..src.len() {
+        info!("-> {} write(s)", i);
+        // SAFETY: src and dst outlive the transfer.
+        let transfer = unsafe {
+            unwrap!(Transfer::new_write(
+                channel.reborrow(),
+                Transfer::SOFTWARE_TRIGGER,
+                &src[..i],
+                &mut dst,
+                options,
+            ))
+        };
+        transfer.await;
+
+        // The result will be the last value written.
+        assert_eq!(dst, src[i - 1]);
+    }
+}
+
+/// [`single_read`], but testing when the destination is wider than the source.
+///
+/// The MSPM0 DMA states that the upper bytes when the destination is longer than the source are zeroed.
+/// This matches the behavior in Rust for all unsigned integer types.
+fn widening_single_read<SW, DW>(mut channel: Peri<'_, impl Channel>, mut src: SW)
+where
+    SW: Word + Copy + Default + Eq + defmt::Format,
+    DW: Word + Copy + Default + Eq + defmt::Format + From<SW>,
+{
+    assert!(
+        DW::size() > SW::size(),
+        "This test only works when the destination is larger than the source"
+    );
+
+    let options = TransferOptions::default();
+    let mut dst = DW::default();
+
+    // SAFETY: src and dst outlive the transfer.
+    let transfer = unsafe {
+        unwrap!(Transfer::new_read(
+            channel.reborrow(),
+            Transfer::SOFTWARE_TRIGGER,
+            &mut src,
+            slice::from_mut(&mut dst),
+            options,
+        ))
+    };
+    transfer.blocking_wait();
+
+    assert_eq!(DW::from(src), dst);
+}
+
+/// [`single_read`], but testing when the destination is narrower than the source.
+///
+/// The MSPM0 DMA states that the upper bytes when the source is longer than the destination are dropped.
+/// This matches the behavior in Rust for all unsigned integer types.
+fn narrowing_single_read<SW, DW>(mut channel: Peri<'_, impl Channel>, mut src: SW)
+where
+    SW: Word + Copy + Default + Eq + defmt::Format + From<DW>,
+    DW: Word + Copy + Default + Eq + defmt::Format + Narrow<SW>,
+{
+    assert!(
+        SW::size() > DW::size(),
+        "This test only works when the source is larger than the destination"
+    );
+
+    let options = TransferOptions::default();
+    let mut dst = DW::default();
+
+    // SAFETY: src and dst outlive the transfer.
+    let transfer = unsafe {
+        unwrap!(Transfer::new_read(
+            channel.reborrow(),
+            Transfer::SOFTWARE_TRIGGER,
+            &mut src,
+            slice::from_mut(&mut dst),
+            options,
+        ))
+    };
+    transfer.blocking_wait();
+
+    // The expected value is the source value masked by the maximum destination value.
+    // This is effectively `src as DW as SW` to drop the upper byte(s).
+    let expect = SW::from(DW::narrow(src));
+    assert_eq!(expect, dst.into());
+}
+
+/// A pseudo `as` trait to allow downcasting integer types (TryFrom could fail).
+trait Narrow<T> {
+    fn narrow(value: T) -> Self;
+}
+
+impl Narrow<u16> for u8 {
+    fn narrow(value: u16) -> Self {
+        value as u8
+    }
+}
+
+impl Narrow<u32> for u8 {
+    fn narrow(value: u32) -> Self {
+        value as u8
+    }
+}
+
+impl Narrow<u64> for u8 {
+    fn narrow(value: u64) -> Self {
+        value as u8
+    }
+}
+
+impl Narrow<u32> for u16 {
+    fn narrow(value: u32) -> Self {
+        value as u16
+    }
+}
+
+impl Narrow<u64> for u16 {
+    fn narrow(value: u64) -> Self {
+        value as u16
+    }
+}
+
+impl Narrow<u64> for u32 {
+    fn narrow(value: u64) -> Self {
+        value as u32
+    }
+}
diff --git a/tests/mspm0/src/bin/uart.rs b/tests/mspm0/src/bin/uart.rs
index 458129d44..916ce0d4b 100644
--- a/tests/mspm0/src/bin/uart.rs
+++ b/tests/mspm0/src/bin/uart.rs
@@ -4,6 +4,9 @@
 #[cfg(feature = "mspm0g3507")]
 teleprobe_meta::target!(b"lp-mspm0g3507");
 
+#[cfg(feature = "mspm0g3519")]
+teleprobe_meta::target!(b"lp-mspm0g3519");
+
 use defmt::{assert_eq, unwrap, *};
 use embassy_executor::Spawner;
 use embassy_mspm0::mode::Blocking;
@@ -23,7 +26,7 @@ async fn main(_spawner: Spawner) {
 
     // TODO: Allow creating a looped-back UART (so pins are not needed).
     // Do not select default UART since the virtual COM port is attached to UART0.
-    #[cfg(feature = "mspm0g3507")]
+    #[cfg(any(feature = "mspm0g3507", feature = "mspm0g3519"))]
     let (mut tx, mut rx, mut uart) = (p.PA8, p.PA9, p.UART1);
 
     const MFCLK_BUAD_RATES: &[u32] = &[1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200];
diff --git a/tests/mspm0/src/bin/uart_buffered.rs b/tests/mspm0/src/bin/uart_buffered.rs
new file mode 100644
index 000000000..135ac1287
--- /dev/null
+++ b/tests/mspm0/src/bin/uart_buffered.rs
@@ -0,0 +1,115 @@
+#![no_std]
+#![no_main]
+
+#[cfg(feature = "mspm0g3507")]
+teleprobe_meta::target!(b"lp-mspm0g3507");
+
+use defmt::{assert_eq, unwrap, *};
+use embassy_executor::Spawner;
+use embassy_mspm0::uart::{BufferedInterruptHandler, BufferedUart, Config};
+use embassy_mspm0::{bind_interrupts, peripherals};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    UART1 => BufferedInterruptHandler<peripherals::UART1>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_mspm0::init(Default::default());
+    info!("Hello World!");
+
+    // TODO: Allow creating a looped-back UART (so pins are not needed).
+    // Do not select default UART since the virtual COM port is attached to UART0.
+    #[cfg(any(feature = "mspm0g3507"))]
+    let (mut tx, mut rx, mut uart) = (p.PA8, p.PA9, p.UART1);
+
+    {
+        use embedded_io_async::{Read, Write};
+
+        let mut config = Config::default();
+        config.loop_back_enable = true;
+        config.fifo_enable = false;
+
+        let tx_buf = &mut [0u8; 16];
+        let rx_buf = &mut [0u8; 16];
+        let mut uart = unwrap!(BufferedUart::new(
+            uart.reborrow(),
+            tx.reborrow(),
+            rx.reborrow(),
+            Irqs,
+            tx_buf,
+            rx_buf,
+            config
+        ));
+
+        let mut buf = [0; 16];
+        for (j, b) in buf.iter_mut().enumerate() {
+            *b = j as u8;
+        }
+
+        unwrap!(uart.write_all(&buf).await);
+        unwrap!(uart.flush().await);
+
+        unwrap!(uart.read_exact(&mut buf).await);
+        for (j, b) in buf.iter().enumerate() {
+            assert_eq!(*b, j as u8);
+        }
+
+        // Buffer is unclogged, should be able to write again.
+        unwrap!(uart.write_all(&buf).await);
+        unwrap!(uart.flush().await);
+
+        unwrap!(uart.read_exact(&mut buf).await);
+        for (j, b) in buf.iter().enumerate() {
+            assert_eq!(*b, j as u8);
+        }
+    }
+
+    info!("Blocking buffered");
+    {
+        use embedded_io::{Read, Write};
+
+        let mut config = Config::default();
+        config.loop_back_enable = true;
+        config.fifo_enable = false;
+
+        let tx_buf = &mut [0u8; 16];
+        let rx_buf = &mut [0u8; 16];
+        let mut uart = unwrap!(BufferedUart::new(
+            uart.reborrow(),
+            tx.reborrow(),
+            rx.reborrow(),
+            Irqs,
+            tx_buf,
+            rx_buf,
+            config
+        ));
+
+        let mut buf = [0; 16];
+
+        for (j, b) in buf.iter_mut().enumerate() {
+            *b = j as u8;
+        }
+
+        unwrap!(uart.write_all(&buf));
+        unwrap!(uart.blocking_flush());
+        unwrap!(uart.read_exact(&mut buf));
+
+        for (j, b) in buf.iter().enumerate() {
+            assert_eq!(*b, j as u8);
+        }
+
+        // Buffer is unclogged, should be able to write again.
+        unwrap!(uart.write_all(&buf));
+        unwrap!(uart.blocking_flush());
+        unwrap!(uart.read_exact(&mut buf));
+
+        for (j, b) in buf.iter().enumerate() {
+            assert_eq!(*b, j as u8, "at {}", j);
+        }
+    }
+
+    info!("Test OK");
+    cortex_m::asm::bkpt();
+}
diff --git a/tests/nrf/Cargo.toml b/tests/nrf/Cargo.toml
index 30c4223b7..b167c589e 100644
--- a/tests/nrf/Cargo.toml
+++ b/tests/nrf/Cargo.toml
@@ -11,7 +11,7 @@ embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt", ] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt",  "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.3.1", path = "../../embassy-nrf", features = ["defmt",  "time-driver-rtc1", "gpiote", "unstable-pac"] }
+embassy-nrf = { version = "0.5.0", path = "../../embassy-nrf", features = ["defmt",  "time-driver-rtc1", "gpiote", "unstable-pac"] }
 embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", ] }
 embassy-net-esp-hosted = { version = "0.2.0", path = "../../embassy-net-esp-hosted", features = ["defmt"] }
diff --git a/tests/rp/Cargo.toml b/tests/rp/Cargo.toml
index 2be37f525..298955fe3 100644
--- a/tests/rp/Cargo.toml
+++ b/tests/rp/Cargo.toml
@@ -15,11 +15,11 @@ teleprobe-meta = "1.1"
 embassy-sync = { version = "0.7.0", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.7.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.4.0", path = "../../embassy-time", features = ["defmt", ] }
-embassy-rp = { version = "0.4.0", path = "../../embassy-rp", features = [ "defmt", "unstable-pac", "time-driver", "critical-section-impl", "intrinsics", "rom-v2-intrinsics", "run-from-ram"]  }
+embassy-rp = { version = "0.6.0", path = "../../embassy-rp", features = [ "defmt", "unstable-pac", "time-driver", "critical-section-impl", "intrinsics", "rom-v2-intrinsics", "run-from-ram"]  }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defmt",  "tcp", "udp", "dhcpv4", "medium-ethernet"] }
 embassy-net-wiznet = { version = "0.2.0", path = "../../embassy-net-wiznet", features = ["defmt"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../../embassy-embedded-hal/"}
+embassy-embedded-hal = { version = "0.3.1", path = "../../embassy-embedded-hal/"}
 cyw43 = { path = "../../cyw43", features = ["defmt", "firmware-logs"] }
 cyw43-pio = { path = "../../cyw43-pio", features = ["defmt"] }
 perf-client = { path = "../perf-client" }
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index 8d10f6593..7c32c0ce1 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -7,6 +7,7 @@ autobins = false
 
 [features]
 stm32c031c6 = ["embassy-stm32/stm32c031c6", "cm0", "not-gpdma"]
+stm32c071rb = ["embassy-stm32/stm32c071rb", "cm0", "not-gpdma"]
 stm32f103c8 = ["embassy-stm32/stm32f103c8", "spi-v1", "not-gpdma"]
 stm32f207zg = ["embassy-stm32/stm32f207zg", "spi-v1", "chrono", "not-gpdma", "eth", "rng"]
 stm32f303ze = ["embassy-stm32/stm32f303ze", "chrono", "not-gpdma"]
diff --git a/tests/stm32/build.rs b/tests/stm32/build.rs
index 722671bf1..556d77a20 100644
--- a/tests/stm32/build.rs
+++ b/tests/stm32/build.rs
@@ -12,6 +12,7 @@ fn main() -> Result<(), Box<dyn Error>> {
         // too little RAM to run from RAM.
         feature = "stm32f103c8", // 20 kb
         feature = "stm32c031c6", // 6 kb
+        feature = "stm32c071rb", // 24 kb
         feature = "stm32l073rz", // 20 kb
         feature = "stm32h503rb", // 32 kb
         // no VTOR, so interrupts can't work when running from RAM
diff --git a/tests/stm32/src/bin/cryp.rs b/tests/stm32/src/bin/cryp.rs
index 028775ac8..f54c99cc3 100644
--- a/tests/stm32/src/bin/cryp.rs
+++ b/tests/stm32/src/bin/cryp.rs
@@ -72,7 +72,7 @@ async fn main(_spawner: Spawner) {
     defmt::assert!(encrypt_tag == payload_vec[ciphertext.len()..ciphertext.len() + encrypt_tag.len()]);
 
     // Decrypt in software using AES-GCM 128-bit
-    let _ = cipher.decrypt_in_place(&iv.into(), &aad, &mut payload_vec);
+    cipher.decrypt_in_place(&iv.into(), &aad, &mut payload_vec).unwrap();
 
     info!("Test OK");
     cortex_m::asm::bkpt();
diff --git a/tests/stm32/src/bin/sdmmc.rs b/tests/stm32/src/bin/sdmmc.rs
index 34a53a725..9f9c526e1 100644
--- a/tests/stm32/src/bin/sdmmc.rs
+++ b/tests/stm32/src/bin/sdmmc.rs
@@ -95,6 +95,9 @@ async fn main(_spawner: Spawner) {
 
     drop(s);
 
+    // FIXME: this hangs on Rust 1.86 and higher.
+    // I haven't been able to figure out why.
+    /*
     // ======== Try 1bit. ==============
     info!("initializing in 1-bit mode...");
     let mut s = Sdmmc::new_1bit(
@@ -151,6 +154,7 @@ async fn main(_spawner: Spawner) {
     assert_eq!(&blocks, &patterns);
 
     drop(s);
+    */
 
     info!("Test OK");
     cortex_m::asm::bkpt();
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 829f2cff0..a4d8048ce 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -34,6 +34,8 @@ teleprobe_meta::target!(b"nucleo-stm32u5a5zj");
 teleprobe_meta::target!(b"nucleo-stm32h563zi");
 #[cfg(feature = "stm32c031c6")]
 teleprobe_meta::target!(b"nucleo-stm32c031c6");
+#[cfg(feature = "stm32c071rb")]
+teleprobe_meta::target!(b"nucleo-stm32c071rb");
 #[cfg(feature = "stm32l073rz")]
 teleprobe_meta::target!(b"nucleo-stm32l073rz");
 #[cfg(feature = "stm32l152re")]
@@ -186,6 +188,12 @@ define_peris!(
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
     @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
 );
+#[cfg(feature = "stm32c071rb")]
+define_peris!(
+    UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
+    SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
+    @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
+);
 #[cfg(feature = "stm32l496zg")]
 define_peris!(
     UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
@@ -271,7 +279,7 @@ pub fn config() -> Config {
     #[allow(unused_mut)]
     let mut config = Config::default();
 
-    #[cfg(feature = "stm32c031c6")]
+    #[cfg(any(feature = "stm32c031c6", feature = "stm32c071rb"))]
     {
         config.rcc.hsi = Some(Hsi {
             sys_div: HsiSysDiv::DIV1, // 48Mhz