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authorSiarhei B <[email protected]>2025-07-24 11:39:30 +0200
committerSiarhei B <[email protected]>2025-08-04 10:19:14 +0200
commitdc52ead73231ee963d1a492e70e49013df7e7127 (patch)
treec7048531b8f321b1bef1028a1e2f44c2255d9cc5
parent917a509c1a899d7054f1a9cf2a21369dc143f46b (diff)
mspm0-I2C: remove SYSOSC init, make ClockDiv::Into private
-rw-r--r--embassy-mspm0/src/i2c.rs4
-rw-r--r--embassy-mspm0/src/lib.rs4
2 files changed, 1 insertions, 7 deletions
diff --git a/embassy-mspm0/src/i2c.rs b/embassy-mspm0/src/i2c.rs
index d093a7e21..3406623fb 100644
--- a/embassy-mspm0/src/i2c.rs
+++ b/embassy-mspm0/src/i2c.rs
@@ -56,7 +56,7 @@ pub enum ClockDiv {
56 DivBy8, 56 DivBy8,
57} 57}
58 58
59impl Into<vals::Ratio> for ClockDiv { 59impl ClockDiv {
60 fn into(self) -> vals::Ratio { 60 fn into(self) -> vals::Ratio {
61 match self { 61 match self {
62 Self::DivBy1 => vals::Ratio::DIV_BY_1, 62 Self::DivBy1 => vals::Ratio::DIV_BY_1,
@@ -69,9 +69,7 @@ impl Into<vals::Ratio> for ClockDiv {
69 Self::DivBy8 => vals::Ratio::DIV_BY_8, 69 Self::DivBy8 => vals::Ratio::DIV_BY_8,
70 } 70 }
71 } 71 }
72}
73 72
74impl ClockDiv {
75 fn divider(self) -> u32 { 73 fn divider(self) -> u32 {
76 match self { 74 match self {
77 Self::DivBy1 => 1, 75 Self::DivBy1 => 1,
diff --git a/embassy-mspm0/src/lib.rs b/embassy-mspm0/src/lib.rs
index fd8450daf..55aef79b1 100644
--- a/embassy-mspm0/src/lib.rs
+++ b/embassy-mspm0/src/lib.rs
@@ -181,10 +181,6 @@ pub fn init(config: Config) -> Peripherals {
181 w.set_mfpclken(true); 181 w.set_mfpclken(true);
182 }); 182 });
183 183
184 pac::SYSCTL.sysosccfg().modify(|w| {
185 w.set_freq(pac::sysctl::vals::SysosccfgFreq::SYSOSCBASE);
186 });
187
188 pac::SYSCTL.borthreshold().modify(|w| { 184 pac::SYSCTL.borthreshold().modify(|w| {
189 w.set_level(0); 185 w.set_level(0);
190 }); 186 });