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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2023-02-09 11:39:52 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-02-09 11:39:52 +0000 |
| commit | e1a0df7d46419962b92c36d8efd8c4840eef7349 (patch) | |
| tree | d3a3b6c909aaa0ba58ccd309a4bfd667b305810d | |
| parent | 26474ce6eb759e5add1c137f3417845e0797df3a (diff) | |
| parent | 2b6654541d2d195636cf7a9c5ef3fdced0583e21 (diff) | |
Merge #1205
1205: stm32/rng Fix rng generation lock-up r=Dirbaio a=lucasgranberg
This PR fixes a problem where the device gets locked in case of rng errors.
The PR also includes a hack for stm32wl based devices where the more complicated RNG peripheral can get stuck on seed errors.
Co-authored-by: Lucas Granberg <[email protected]>
| -rw-r--r-- | embassy-stm32/src/rng.rs | 11 | ||||
| m--------- | stm32-data | 0 |
2 files changed, 9 insertions, 2 deletions
diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs index 10fc4a75e..1e16b8478 100644 --- a/embassy-stm32/src/rng.rs +++ b/embassy-stm32/src/rng.rs | |||
| @@ -32,6 +32,11 @@ impl<'d, T: Instance> Rng<'d, T> { | |||
| 32 | } | 32 | } |
| 33 | 33 | ||
| 34 | pub fn reset(&mut self) { | 34 | pub fn reset(&mut self) { |
| 35 | // rng_v2 locks up on seed error, needs reset | ||
| 36 | #[cfg(rng_v2)] | ||
| 37 | if unsafe { T::regs().sr().read().seis() } { | ||
| 38 | T::reset(); | ||
| 39 | } | ||
| 35 | unsafe { | 40 | unsafe { |
| 36 | T::regs().cr().modify(|reg| { | 41 | T::regs().cr().modify(|reg| { |
| 37 | reg.set_rngen(true); | 42 | reg.set_rngen(true); |
| @@ -90,8 +95,10 @@ impl<'d, T: Instance> Rng<'d, T> { | |||
| 90 | impl<'d, T: Instance> RngCore for Rng<'d, T> { | 95 | impl<'d, T: Instance> RngCore for Rng<'d, T> { |
| 91 | fn next_u32(&mut self) -> u32 { | 96 | fn next_u32(&mut self) -> u32 { |
| 92 | loop { | 97 | loop { |
| 93 | let bits = unsafe { T::regs().sr().read() }; | 98 | let sr = unsafe { T::regs().sr().read() }; |
| 94 | if bits.drdy() { | 99 | if sr.seis() | sr.ceis() { |
| 100 | self.reset(); | ||
| 101 | } else if sr.drdy() { | ||
| 95 | return unsafe { T::regs().dr().read() }; | 102 | return unsafe { T::regs().dr().read() }; |
| 96 | } | 103 | } |
| 97 | } | 104 | } |
diff --git a/stm32-data b/stm32-data | |||
| Subproject cc93f9d10395077770bebefb6b9488e06b0e581 | Subproject 66252982939014e94fc4a1b7423c30c3d108ae0 | ||
