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authorBob McWhirter <[email protected]>2021-08-24 14:44:31 -0400
committerBob McWhirter <[email protected]>2021-08-24 14:44:47 -0400
commite36ae76e4518465953cf1adfb5c40f8cd91667d6 (patch)
tree2e9aff7a5e7e94e361df0793ac4ce75791798081
parent548593ea415c79472bd2cf2d0c59aadfcf5f715c (diff)
Fix blocking-write for SPI.
-rw-r--r--embassy-stm32/src/spi/v3.rs30
1 files changed, 27 insertions, 3 deletions
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs
index cfee54dac..dd8c1c2fd 100644
--- a/embassy-stm32/src/spi/v3.rs
+++ b/embassy-stm32/src/spi/v3.rs
@@ -171,6 +171,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
171 w.set_dsize(word_size.dsize()); 171 w.set_dsize(word_size.dsize());
172 }); 172 });
173 T::regs().cr1().modify(|w| { 173 T::regs().cr1().modify(|w| {
174 w.set_csusp(false);
174 w.set_spe(true); 175 w.set_spe(true);
175 }); 176 });
176 } 177 }
@@ -375,10 +376,21 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDm
375 } 376 }
376 if !sr.txp() { 377 if !sr.txp() {
377 // loop waiting for TXE 378 // loop waiting for TXE
379 continue;
378 } 380 }
381 break;
382 }
383 unsafe {
384 let rxdr = regs.rxdr().ptr() as *const u8;
385 // discard read to prevent pverrun.
386 let _ = ptr::read_volatile(rxdr);
379 } 387 }
380 } 388 }
381 389
390 while unsafe { !regs.sr().read().txc() } {
391 // spin
392 }
393
382 Ok(()) 394 Ok(())
383 } 395 }
384} 396}
@@ -469,8 +481,20 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoD
469 } 481 }
470 if !sr.txp() { 482 if !sr.txp() {
471 // loop waiting for TXE 483 // loop waiting for TXE
484 continue;
472 } 485 }
486 break;
473 } 487 }
488
489 unsafe {
490 let rxdr = regs.rxdr().ptr() as *const u8;
491 // discard read to prevent pverrun.
492 let _ = ptr::read_volatile(rxdr);
493 }
494 }
495
496 while unsafe { !regs.sr().read().txc() } {
497 // spin
474 } 498 }
475 499
476 Ok(()) 500 Ok(())
@@ -537,7 +561,7 @@ impl<'d, T: Instance, Tx, Rx> traits::Spi<u8> for Spi<'d, T, Tx, Rx> {
537 561
538impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx> traits::Write<u8> for Spi<'d, T, Tx, Rx> { 562impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx> traits::Write<u8> for Spi<'d, T, Tx, Rx> {
539 #[rustfmt::skip] 563 #[rustfmt::skip]
540 type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a; 564 type WriteFuture<'a> where Self: 'a = impl Future<Output=Result<(), Self::Error>> + 'a;
541 565
542 fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> { 566 fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
543 self.write_dma_u8(data) 567 self.write_dma_u8(data)
@@ -548,7 +572,7 @@ impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::Read<u8>
548 for Spi<'d, T, Tx, Rx> 572 for Spi<'d, T, Tx, Rx>
549{ 573{
550 #[rustfmt::skip] 574 #[rustfmt::skip]
551 type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a; 575 type ReadFuture<'a> where Self: 'a = impl Future<Output=Result<(), Self::Error>> + 'a;
552 576
553 fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> { 577 fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
554 self.read_dma_u8(data) 578 self.read_dma_u8(data)
@@ -559,7 +583,7 @@ impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::FullDupl
559 for Spi<'d, T, Tx, Rx> 583 for Spi<'d, T, Tx, Rx>
560{ 584{
561 #[rustfmt::skip] 585 #[rustfmt::skip]
562 type WriteReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a; 586 type WriteReadFuture<'a> where Self: 'a = impl Future<Output=Result<(), Self::Error>> + 'a;
563 587
564 fn read_write<'a>( 588 fn read_write<'a>(
565 &'a mut self, 589 &'a mut self,