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authorxoviat <[email protected]>2023-08-23 20:01:35 -0500
committerxoviat <[email protected]>2023-08-23 20:01:35 -0500
commite987259716c56f9854cc4730620d7b5a8be9962d (patch)
tree5ecbcd04ad85cdeeccaf65d6655f0bf96e6b4eab
parentfc04d2a33caa300bce38f7d0a46f1a0c814bb613 (diff)
rtc: cleanup
-rw-r--r--embassy-stm32/src/rtc/v2.rs41
1 files changed, 4 insertions, 37 deletions
diff --git a/embassy-stm32/src/rtc/v2.rs b/embassy-stm32/src/rtc/v2.rs
index 1d4f4df30..bcb127ecb 100644
--- a/embassy-stm32/src/rtc/v2.rs
+++ b/embassy-stm32/src/rtc/v2.rs
@@ -1,4 +1,3 @@
1use defmt::Format;
2use stm32_metapac::rtc::vals::{Init, Osel, Pol}; 1use stm32_metapac::rtc::vals::{Init, Osel, Pol};
3 2
4use super::{sealed, RtcClockSource, RtcConfig}; 3use super::{sealed, RtcClockSource, RtcConfig};
@@ -45,25 +44,15 @@ impl core::ops::Sub for RtcInstant {
45 fn sub(self, rhs: Self) -> Self::Output { 44 fn sub(self, rhs: Self) -> Self::Output {
46 use embassy_time::{Duration, TICK_HZ}; 45 use embassy_time::{Duration, TICK_HZ};
47 46
48 trace!("self st: {}", self.st);
49 trace!("other st: {}", rhs.st);
50
51 trace!("self ssr: {}", self.ssr);
52 trace!("other ssr: {}", rhs.ssr);
53
54 let st = if self.st < rhs.st { self.st + 60 } else { self.st }; 47 let st = if self.st < rhs.st { self.st + 60 } else { self.st };
55 48
56 trace!("self st: {}", st); 49 // TODO: read prescaler
57 50
58 let self_ticks = st as u32 * 256 + (255 - self.ssr as u32); 51 let self_ticks = st as u32 * 256 + (255 - self.ssr as u32);
59 let other_ticks = rhs.st as u32 * 256 + (255 - rhs.ssr as u32); 52 let other_ticks = rhs.st as u32 * 256 + (255 - rhs.ssr as u32);
60 let rtc_ticks = self_ticks - other_ticks; 53 let rtc_ticks = self_ticks - other_ticks;
61 54
62 trace!("self ticks: {}", self_ticks); 55 trace!("self, other, rtc ticks: {}, {}, {}", self_ticks, other_ticks, rtc_ticks);
63 trace!("other ticks: {}", other_ticks);
64 trace!("rtc ticks: {}", rtc_ticks);
65
66 // TODO: read prescaler
67 56
68 Duration::from_ticks( 57 Duration::from_ticks(
69 ((((st as u32 * 256 + (255u32 - self.ssr as u32)) - (rhs.st as u32 * 256 + (255u32 - rhs.ssr as u32))) 58 ((((st as u32 * 256 + (255u32 - self.ssr as u32)) - (rhs.st as u32 * 256 + (255u32 - rhs.ssr as u32)))
@@ -74,7 +63,7 @@ impl core::ops::Sub for RtcInstant {
74} 63}
75 64
76#[allow(dead_code)] 65#[allow(dead_code)]
77#[derive(Clone, Copy, Debug, Format)] 66#[derive(Clone, Copy, Debug)]
78pub(crate) enum WakeupPrescaler { 67pub(crate) enum WakeupPrescaler {
79 Div2, 68 Div2,
80 Div4, 69 Div4,
@@ -186,40 +175,18 @@ impl super::Rtc {
186 ); 175 );
187 176
188 trace!("set wakeup timer for {} ms", duration.as_millis()); 177 trace!("set wakeup timer for {} ms", duration.as_millis());
189 trace!("set wakeup timer for {} ticks with pre {}", rtc_ticks, prescaler);
190 178
191 self.write(false, |regs| { 179 self.write(false, |regs| {
192 regs.cr().modify(|w| w.set_wutie(true)); 180 regs.cr().modify(|w| w.set_wutie(true));
193 181
194 trace!("clear wute");
195 regs.cr().modify(|w| w.set_wute(false)); 182 regs.cr().modify(|w| w.set_wute(false));
196 regs.isr().modify(|w| w.set_wutf(false)); 183 regs.isr().modify(|w| w.set_wutf(false));
197
198 trace!("wait for wutwf...");
199 while !regs.isr().read().wutwf() {} 184 while !regs.isr().read().wutwf() {}
200 trace!("wait for wutwf...done");
201
202 regs.cr().modify(|w| {
203 w.set_wucksel(prescaler.into());
204
205 w.set_wutie(true);
206 });
207 185
186 regs.cr().modify(|w| w.set_wucksel(prescaler.into()));
208 regs.cr().modify(|w| w.set_wute(true)); 187 regs.cr().modify(|w| w.set_wute(true));
209 }); 188 });
210 189
211 if !RTC::regs().cr().read().wute() {
212 trace!("wakeup timer not enabled");
213 } else {
214 trace!("wakeup timer enabled");
215 }
216
217 if !RTC::regs().cr().read().wutie() {
218 trace!("wakeup timer interrupt not enabled");
219 } else {
220 trace!("wakeup timer interrupt enabled");
221 }
222
223 RtcInstant::now() 190 RtcInstant::now()
224 } 191 }
225 192