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authorArdelean Calin <[email protected]>2022-11-23 14:16:18 +0200
committerArdelean Calin <[email protected]>2022-11-23 14:16:18 +0200
commiteae67d0be888d12e71bc3340279bab85666c05ae (patch)
treeb47415947af4f14c90e1ec02667a3877b4a08508
parent4f2f3757773fb30700c3c6ee7ab98cd6e38406a3 (diff)
Review comments. Corrected unused fields.
-rw-r--r--embassy-nrf/src/gpiote.rs38
1 files changed, 19 insertions, 19 deletions
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index 4d5fa62b0..7f7468a20 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -148,14 +148,14 @@ impl Iterator for BitIter {
148 148
149/// GPIOTE channel driver in input mode 149/// GPIOTE channel driver in input mode
150pub struct InputChannel<'d, C: Channel, T: GpioPin> { 150pub struct InputChannel<'d, C: Channel, T: GpioPin> {
151 _ch: PeripheralRef<'d, C>, 151 ch: PeripheralRef<'d, C>,
152 _pin: Input<'d, T>, 152 pin: Input<'d, T>,
153} 153}
154 154
155impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> { 155impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> {
156 fn drop(&mut self) { 156 fn drop(&mut self) {
157 let g = regs(); 157 let g = regs();
158 let num = self._ch.number(); 158 let num = self.ch.number();
159 g.config[num].write(|w| w.mode().disabled()); 159 g.config[num].write(|w| w.mode().disabled());
160 g.intenclr.write(|w| unsafe { w.bits(1 << num) }); 160 g.intenclr.write(|w| unsafe { w.bits(1 << num) });
161 } 161 }
@@ -185,12 +185,12 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
185 185
186 g.events_in[num].reset(); 186 g.events_in[num].reset();
187 187
188 InputChannel { _ch: ch, _pin: pin } 188 InputChannel { ch, pin }
189 } 189 }
190 190
191 pub async fn wait(&self) { 191 pub async fn wait(&self) {
192 let g = regs(); 192 let g = regs();
193 let num = self._ch.number(); 193 let num = self.ch.number();
194 194
195 // Enable interrupt 195 // Enable interrupt
196 g.events_in[num].reset(); 196 g.events_in[num].reset();
@@ -211,20 +211,20 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
211 /// Returns the IN event, for use with PPI. 211 /// Returns the IN event, for use with PPI.
212 pub fn event_in(&self) -> Event { 212 pub fn event_in(&self) -> Event {
213 let g = regs(); 213 let g = regs();
214 Event::from_reg(&g.events_in[self._ch.number()]) 214 Event::from_reg(&g.events_in[self.ch.number()])
215 } 215 }
216} 216}
217 217
218/// GPIOTE channel driver in output mode 218/// GPIOTE channel driver in output mode
219pub struct OutputChannel<'d, C: Channel, T: GpioPin> { 219pub struct OutputChannel<'d, C: Channel, T: GpioPin> {
220 _ch: PeripheralRef<'d, C>, 220 ch: PeripheralRef<'d, C>,
221 _pin: Output<'d, T>, 221 _pin: Output<'d, T>,
222} 222}
223 223
224impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> { 224impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> {
225 fn drop(&mut self) { 225 fn drop(&mut self) {
226 let g = regs(); 226 let g = regs();
227 let num = self._ch.number(); 227 let num = self.ch.number();
228 g.config[num].write(|w| w.mode().disabled()); 228 g.config[num].write(|w| w.mode().disabled());
229 g.intenclr.write(|w| unsafe { w.bits(1 << num) }); 229 g.intenclr.write(|w| unsafe { w.bits(1 << num) });
230 } 230 }
@@ -255,47 +255,47 @@ impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> {
255 unsafe { w.psel().bits(pin.pin.pin.pin()) } 255 unsafe { w.psel().bits(pin.pin.pin.pin()) }
256 }); 256 });
257 257
258 OutputChannel { _ch: ch, _pin: pin } 258 OutputChannel { ch, _pin: pin }
259 } 259 }
260 260
261 /// Triggers `task out` (as configured with task_out_polarity, defaults to Toggle). 261 /// Triggers `task out` (as configured with task_out_polarity, defaults to Toggle).
262 pub fn out(&self) { 262 pub fn out(&self) {
263 let g = regs(); 263 let g = regs();
264 g.tasks_out[self._ch.number()].write(|w| unsafe { w.bits(1) }); 264 g.tasks_out[self.ch.number()].write(|w| unsafe { w.bits(1) });
265 } 265 }
266 266
267 /// Triggers `task set` (set associated pin high). 267 /// Triggers `task set` (set associated pin high).
268 #[cfg(not(feature = "nrf51"))] 268 #[cfg(not(feature = "nrf51"))]
269 pub fn set(&self) { 269 pub fn set(&self) {
270 let g = regs(); 270 let g = regs();
271 g.tasks_set[self._ch.number()].write(|w| unsafe { w.bits(1) }); 271 g.tasks_set[self.ch.number()].write(|w| unsafe { w.bits(1) });
272 } 272 }
273 273
274 /// Triggers `task clear` (set associated pin low). 274 /// Triggers `task clear` (set associated pin low).
275 #[cfg(not(feature = "nrf51"))] 275 #[cfg(not(feature = "nrf51"))]
276 pub fn clear(&self) { 276 pub fn clear(&self) {
277 let g = regs(); 277 let g = regs();
278 g.tasks_clr[self._ch.number()].write(|w| unsafe { w.bits(1) }); 278 g.tasks_clr[self.ch.number()].write(|w| unsafe { w.bits(1) });
279 } 279 }
280 280
281 /// Returns the OUT task, for use with PPI. 281 /// Returns the OUT task, for use with PPI.
282 pub fn task_out(&self) -> Task { 282 pub fn task_out(&self) -> Task {
283 let g = regs(); 283 let g = regs();
284 Task::from_reg(&g.tasks_out[self._ch.number()]) 284 Task::from_reg(&g.tasks_out[self.ch.number()])
285 } 285 }
286 286
287 /// Returns the CLR task, for use with PPI. 287 /// Returns the CLR task, for use with PPI.
288 #[cfg(not(feature = "nrf51"))] 288 #[cfg(not(feature = "nrf51"))]
289 pub fn task_clr(&self) -> Task { 289 pub fn task_clr(&self) -> Task {
290 let g = regs(); 290 let g = regs();
291 Task::from_reg(&g.tasks_clr[self._ch.number()]) 291 Task::from_reg(&g.tasks_clr[self.ch.number()])
292 } 292 }
293 293
294 /// Returns the SET task, for use with PPI. 294 /// Returns the SET task, for use with PPI.
295 #[cfg(not(feature = "nrf51"))] 295 #[cfg(not(feature = "nrf51"))]
296 pub fn task_set(&self) -> Task { 296 pub fn task_set(&self) -> Task {
297 let g = regs(); 297 let g = regs();
298 Task::from_reg(&g.tasks_set[self._ch.number()]) 298 Task::from_reg(&g.tasks_set[self.ch.number()])
299 } 299 }
300} 300}
301 301
@@ -443,11 +443,11 @@ mod eh02 {
443 type Error = Infallible; 443 type Error = Infallible;
444 444
445 fn is_high(&self) -> Result<bool, Self::Error> { 445 fn is_high(&self) -> Result<bool, Self::Error> {
446 Ok(self._pin.is_high()) 446 Ok(self.pin.is_high())
447 } 447 }
448 448
449 fn is_low(&self) -> Result<bool, Self::Error> { 449 fn is_low(&self) -> Result<bool, Self::Error> {
450 Ok(self._pin.is_low()) 450 Ok(self.pin.is_low())
451 } 451 }
452 } 452 }
453} 453}
@@ -462,11 +462,11 @@ mod eh1 {
462 462
463 impl<'d, C: Channel, T: GpioPin> embedded_hal_1::digital::InputPin for InputChannel<'d, C, T> { 463 impl<'d, C: Channel, T: GpioPin> embedded_hal_1::digital::InputPin for InputChannel<'d, C, T> {
464 fn is_high(&self) -> Result<bool, Self::Error> { 464 fn is_high(&self) -> Result<bool, Self::Error> {
465 Ok(self._pin.is_high()) 465 Ok(self.pin.is_high())
466 } 466 }
467 467
468 fn is_low(&self) -> Result<bool, Self::Error> { 468 fn is_low(&self) -> Result<bool, Self::Error> {
469 Ok(self._pin.is_low()) 469 Ok(self.pin.is_low())
470 } 470 }
471 } 471 }
472} 472}