aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAnton Pöhl <[email protected]>2025-03-13 11:33:11 +0100
committerAnton Pöhl <[email protected]>2025-04-11 20:58:03 +0200
commiteb73cc7cfe85921ab2d6605addc12edfaa93cef4 (patch)
tree504756541a5401585898a27904d192dd85d009a9
parenta544726be4ef66574419e95ee508f2062e9a3da2 (diff)
Format
-rw-r--r--embassy-stm32/src/usart/buffered.rs4
-rw-r--r--embassy-stm32/src/usart/mod.rs24
2 files changed, 5 insertions, 23 deletions
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 57551ff56..19dab75a0 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -13,8 +13,8 @@ use embassy_sync::waitqueue::AtomicWaker;
13use super::DePin; 13use super::DePin;
14use super::{ 14use super::{
15 clear_interrupt_flags, configure, half_duplex_set_rx_tx_before_write, rdr, reconfigure, send_break, set_baudrate, 15 clear_interrupt_flags, configure, half_duplex_set_rx_tx_before_write, rdr, reconfigure, send_break, set_baudrate,
16 sr, tdr, Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexReadback, Info, Instance, Regs, 16 sr, tdr, Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexReadback, Info, Instance, Regs, RtsPin, RxPin,
17 RtsPin, RxPin, TxPin, 17 TxPin,
18}; 18};
19use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _}; 19use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _};
20use crate::interrupt::{self, InterruptExt}; 20use crate::interrupt::{self, InterruptExt};
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index a6bafc5a7..6c5d3422b 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -450,13 +450,7 @@ impl<'d> UartTx<'d, Async> {
450 tx_dma: Peri<'d, impl TxDma<T>>, 450 tx_dma: Peri<'d, impl TxDma<T>>,
451 config: Config, 451 config: Config,
452 ) -> Result<Self, ConfigError> { 452 ) -> Result<Self, ConfigError> {
453 Self::new_inner( 453 Self::new_inner(peri, new_pin!(tx, config.tx_af()), None, new_dma!(tx_dma), config)
454 peri,
455 new_pin!(tx, config.tx_af()),
456 None,
457 new_dma!(tx_dma),
458 config,
459 )
460 } 454 }
461 455
462 /// Create a new tx-only UART with a clear-to-send pin 456 /// Create a new tx-only UART with a clear-to-send pin
@@ -508,13 +502,7 @@ impl<'d> UartTx<'d, Blocking> {
508 tx: Peri<'d, impl TxPin<T>>, 502 tx: Peri<'d, impl TxPin<T>>,
509 config: Config, 503 config: Config,
510 ) -> Result<Self, ConfigError> { 504 ) -> Result<Self, ConfigError> {
511 Self::new_inner( 505 Self::new_inner(peri, new_pin!(tx, config.tx_af()), None, None, config)
512 peri,
513 new_pin!(tx, config.tx_af()),
514 None,
515 None,
516 config,
517 )
518 } 506 }
519 507
520 /// Create a new blocking tx-only UART with a clear-to-send pin 508 /// Create a new blocking tx-only UART with a clear-to-send pin
@@ -682,13 +670,7 @@ impl<'d> UartRx<'d, Async> {
682 rx_dma: Peri<'d, impl RxDma<T>>, 670 rx_dma: Peri<'d, impl RxDma<T>>,
683 config: Config, 671 config: Config,
684 ) -> Result<Self, ConfigError> { 672 ) -> Result<Self, ConfigError> {
685 Self::new_inner( 673 Self::new_inner(peri, new_pin!(rx, config.rx_af()), None, new_dma!(rx_dma), config)
686 peri,
687 new_pin!(rx, config.rx_af()),
688 None,
689 new_dma!(rx_dma),
690 config,
691 )
692 } 674 }
693 675
694 /// Create a new rx-only UART with a request-to-send pin 676 /// Create a new rx-only UART with a request-to-send pin