diff options
| author | Guillaume MICHEL <[email protected]> | 2022-10-27 11:03:37 +0200 |
|---|---|---|
| committer | Guillaume MICHEL <[email protected]> | 2022-10-28 09:04:36 +0200 |
| commit | f053bf742c2e6e5e5e18e36bb773bc1e84010a2a (patch) | |
| tree | 9e81e62ea9193a8e03cae43498be164e9c823c5c | |
| parent | 9423987ac52b0e4f7a176e70114016acd3752592 (diff) | |
embassy-stm32: Add support for hardware flow control for BufferedUart
| -rw-r--r-- | embassy-stm32/src/usart/buffered.rs | 47 |
1 files changed, 44 insertions, 3 deletions
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs index 3be0677bd..59c7a8cca 100644 --- a/embassy-stm32/src/usart/buffered.rs +++ b/embassy-stm32/src/usart/buffered.rs | |||
| @@ -46,7 +46,7 @@ impl<'d, T: BasicInstance> Unpin for BufferedUart<'d, T> {} | |||
| 46 | impl<'d, T: BasicInstance> BufferedUart<'d, T> { | 46 | impl<'d, T: BasicInstance> BufferedUart<'d, T> { |
| 47 | pub fn new( | 47 | pub fn new( |
| 48 | state: &'d mut State<'d, T>, | 48 | state: &'d mut State<'d, T>, |
| 49 | _peri: impl Peripheral<P = T> + 'd, | 49 | peri: impl Peripheral<P = T> + 'd, |
| 50 | rx: impl Peripheral<P = impl RxPin<T>> + 'd, | 50 | rx: impl Peripheral<P = impl RxPin<T>> + 'd, |
| 51 | tx: impl Peripheral<P = impl TxPin<T>> + 'd, | 51 | tx: impl Peripheral<P = impl TxPin<T>> + 'd, |
| 52 | irq: impl Peripheral<P = T::Interrupt> + 'd, | 52 | irq: impl Peripheral<P = T::Interrupt> + 'd, |
| @@ -54,11 +54,53 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> { | |||
| 54 | rx_buffer: &'d mut [u8], | 54 | rx_buffer: &'d mut [u8], |
| 55 | config: Config, | 55 | config: Config, |
| 56 | ) -> BufferedUart<'d, T> { | 56 | ) -> BufferedUart<'d, T> { |
| 57 | into_ref!(_peri, rx, tx, irq); | 57 | T::enable(); |
| 58 | T::reset(); | ||
| 59 | |||
| 60 | Self::new_inner(state, peri, rx, tx, irq, tx_buffer, rx_buffer, config) | ||
| 61 | } | ||
| 62 | |||
| 63 | pub fn new_with_rtscts( | ||
| 64 | state: &'d mut State<'d, T>, | ||
| 65 | peri: impl Peripheral<P = T> + 'd, | ||
| 66 | rx: impl Peripheral<P = impl RxPin<T>> + 'd, | ||
| 67 | tx: impl Peripheral<P = impl TxPin<T>> + 'd, | ||
| 68 | irq: impl Peripheral<P = T::Interrupt> + 'd, | ||
| 69 | rts: impl Peripheral<P = impl RtsPin<T>> + 'd, | ||
| 70 | cts: impl Peripheral<P = impl CtsPin<T>> + 'd, | ||
| 71 | tx_buffer: &'d mut [u8], | ||
| 72 | rx_buffer: &'d mut [u8], | ||
| 73 | config: Config, | ||
| 74 | ) -> BufferedUart<'d, T> { | ||
| 75 | into_ref!(cts, rts); | ||
| 58 | 76 | ||
| 59 | T::enable(); | 77 | T::enable(); |
| 60 | T::reset(); | 78 | T::reset(); |
| 61 | 79 | ||
| 80 | unsafe { | ||
| 81 | rts.set_as_af(rts.af_num(), AFType::OutputPushPull); | ||
| 82 | cts.set_as_af(cts.af_num(), AFType::Input); | ||
| 83 | T::regs().cr3().write(|w| { | ||
| 84 | w.set_rtse(true); | ||
| 85 | w.set_ctse(true); | ||
| 86 | }); | ||
| 87 | } | ||
| 88 | |||
| 89 | Self::new_inner(state, peri, rx, tx, irq, tx_buffer, rx_buffer, config) | ||
| 90 | } | ||
| 91 | |||
| 92 | fn new_inner( | ||
| 93 | state: &'d mut State<'d, T>, | ||
| 94 | _peri: impl Peripheral<P = T> + 'd, | ||
| 95 | rx: impl Peripheral<P = impl RxPin<T>> + 'd, | ||
| 96 | tx: impl Peripheral<P = impl TxPin<T>> + 'd, | ||
| 97 | irq: impl Peripheral<P = T::Interrupt> + 'd, | ||
| 98 | tx_buffer: &'d mut [u8], | ||
| 99 | rx_buffer: &'d mut [u8], | ||
| 100 | config: Config, | ||
| 101 | ) -> BufferedUart<'d, T> { | ||
| 102 | into_ref!(_peri, rx, tx, irq); | ||
| 103 | |||
| 62 | let r = T::regs(); | 104 | let r = T::regs(); |
| 63 | 105 | ||
| 64 | configure(r, &config, T::frequency(), T::MULTIPLIER); | 106 | configure(r, &config, T::frequency(), T::MULTIPLIER); |
| @@ -68,7 +110,6 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> { | |||
| 68 | tx.set_as_af(tx.af_num(), AFType::OutputPushPull); | 110 | tx.set_as_af(tx.af_num(), AFType::OutputPushPull); |
| 69 | 111 | ||
| 70 | r.cr2().write(|_w| {}); | 112 | r.cr2().write(|_w| {}); |
| 71 | r.cr3().write(|_w| {}); | ||
| 72 | r.cr1().write(|w| { | 113 | r.cr1().write(|w| { |
| 73 | w.set_ue(true); | 114 | w.set_ue(true); |
| 74 | w.set_te(true); | 115 | w.set_te(true); |
