Merge branch 'main' into nrf-simplepwm-config

29 files changed, 541 insertions, 147 deletions

diff --git a/embassy-nrf/CHANGELOG.md b/embassy-nrf/CHANGELOG.md
index 8ce484646..89adaf2da 100644
--- a/embassy-nrf/CHANGELOG.md
+++ b/embassy-nrf/CHANGELOG.md
@@ -11,6 +11,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - added: Add basic RTC support for nRF54L
 - changed: apply trimming values from FICR.TRIMCNF on nrf53/54l
 - changed: do not panic on BufferedUarte overrun
+- added: allow direct access to the input pin of `gpiote::InputChannel`
+- bugfix: use DETECTMODE_SEC in GPIOTE in secure mode
 - added: allow configuring the idle state of GPIO pins connected to PWM channels
 - changed: allow configuring the PWM peripheral in the constructor of `SimplePwm`
 - changed: support setting duty cycles with inverted polarity in `SimplePwm`
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index a490d5b60..3658657c0 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -77,6 +77,9 @@ pub(crate) fn init(irq_prio: crate::interrupt::Priority) {
 
         for &p in ports {
             // Enable latched detection
+            #[cfg(feature = "_s")]
+            p.detectmode_sec().write(|w| w.set_detectmode(Detectmode::LDETECT));
+            #[cfg(not(feature = "_s"))]
             p.detectmode().write(|w| w.set_detectmode(Detectmode::LDETECT));
             // Clear latch
             p.latch().write(|w| w.0 = 0xFFFFFFFF)
@@ -259,6 +262,11 @@ impl<'d> InputChannel<'d> {
         .await;
     }
 
+    /// Get the associated input pin.
+    pub fn pin(&self) -> &Input<'_> {
+        &self.pin
+    }
+
     /// Returns the IN event, for use with PPI.
     pub fn event_in(&self) -> Event<'d> {
         let g = regs();
diff --git a/embassy-nxp/CHANGELOG.md b/embassy-nxp/CHANGELOG.md
index 0fb677cd8..39f5c75bd 100644
--- a/embassy-nxp/CHANGELOG.md
+++ b/embassy-nxp/CHANGELOG.md
@@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 <!-- next-header -->
 ## Unreleased - ReleaseDate
+- LPC55: PWM simple
+- LPC55: Move ALT definitions for USART to TX/RX pin impls. 
+- LPC55: Remove internal match_iocon macro
 - LPC55: DMA Controller and asynchronous version of USART
 - Moved NXP LPC55S69 from `lpc55-pac` to `nxp-pac`
 - First release with changelog.
diff --git a/embassy-nxp/Cargo.toml b/embassy-nxp/Cargo.toml
index 33f0f2dff..f8c63ba29 100644
--- a/embassy-nxp/Cargo.toml
+++ b/embassy-nxp/Cargo.toml
@@ -38,13 +38,13 @@ embassy-time-queue-utils = { version = "0.3.0", path = "../embassy-time-queue-ut
 embedded-io = "0.6.1"
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
 ## Chip dependencies
-nxp-pac = { version = "0.1.0", optional = true, git = "https://github.com/i509VCB/nxp-pac", rev = "b736e3038254d593024aaa1a5a7b1f95a5728538"}
+nxp-pac = { version = "0.1.0", optional = true, git = "https://github.com/i509VCB/nxp-pac", rev = "477dfdbfd5e6c75c0730c56494b601c1b2257263"}
 
 imxrt-rt = { version = "0.1.7", optional = true, features = ["device"] }
 
 [build-dependencies]
 cfg_aliases = "0.2.1"
-nxp-pac = { version = "0.1.0", git = "https://github.com/i509VCB/nxp-pac", rev = "b736e3038254d593024aaa1a5a7b1f95a5728538", features = ["metadata"], optional = true }
+nxp-pac = { version = "0.1.0", git = "https://github.com/i509VCB/nxp-pac", rev = "477dfdbfd5e6c75c0730c56494b601c1b2257263", features = ["metadata"], optional = true }
 proc-macro2 = "1.0.95"
 quote = "1.0.15"
 
diff --git a/embassy-nxp/src/chips/lpc55.rs b/embassy-nxp/src/chips/lpc55.rs
index 9f4e7269f..e9addddb6 100644
--- a/embassy-nxp/src/chips/lpc55.rs
+++ b/embassy-nxp/src/chips/lpc55.rs
@@ -97,6 +97,18 @@ embassy_hal_internal::peripherals! {
     DMA_CH21,
     DMA_CH22,
 
+    // Pulse-Width Modulation Outputs.
+    PWM_OUTPUT0,
+    PWM_OUTPUT1,
+    PWM_OUTPUT2,
+    PWM_OUTPUT3,
+    PWM_OUTPUT4,
+    PWM_OUTPUT5,
+    PWM_OUTPUT6,
+    PWM_OUTPUT7,
+    PWM_OUTPUT8,
+    PWM_OUTPUT9,
+
     // Universal Synchronous/Asynchronous Receiver/Transmitter (USART) instances.
     USART0,
     USART1,
diff --git a/embassy-nxp/src/fmt.rs b/embassy-nxp/src/fmt.rs
index 27d41ace6..11275235e 100644
--- a/embassy-nxp/src/fmt.rs
+++ b/embassy-nxp/src/fmt.rs
@@ -1,5 +1,4 @@
 //! Copied from embassy-rp
-
 #![macro_use]
 #![allow(unused)]
 
diff --git a/embassy-nxp/src/gpio/lpc55.rs b/embassy-nxp/src/gpio/lpc55.rs
index ac8a27d4f..6039d8ca8 100644
--- a/embassy-nxp/src/gpio/lpc55.rs
+++ b/embassy-nxp/src/gpio/lpc55.rs
@@ -1,7 +1,8 @@
 use embassy_hal_internal::{PeripheralType, impl_peripheral};
 
+use crate::pac::common::{RW, Reg};
 use crate::pac::iocon::vals::{PioDigimode, PioMode};
-use crate::pac::{GPIO, IOCON, SYSCON};
+use crate::pac::{GPIO, IOCON, SYSCON, iocon};
 use crate::{Peri, peripherals};
 
 pub(crate) fn init() {
@@ -109,13 +110,7 @@ impl<'d> Input<'d> {
 
     /// Set the pull configuration for the pin. To disable the pull, use [Pull::None].
     pub fn set_pull(&mut self, pull: Pull) {
-        match_iocon!(register, self.pin.pin_bank(), self.pin.pin_number(), {
-            register.modify(|w| match pull {
-                Pull::None => w.set_mode(PioMode::INACTIVE),
-                Pull::Up => w.set_mode(PioMode::PULL_UP),
-                Pull::Down => w.set_mode(PioMode::PULL_DOWN),
-            });
-        });
+        self.pin.set_pull(pull);
     }
 
     /// Get the current input level of the pin.
@@ -193,11 +188,20 @@ impl<'d> Flex<'d> {
         1 << self.pin.pin_number()
     }
 
+    /// Set the pull configuration for the pin. To disable the pull, use [Pull::None].
+    pub fn set_pull(&mut self, pull: Pull) {
+        self.pin.pio().modify(|w| match pull {
+            Pull::None => w.set_mode(PioMode::INACTIVE),
+            Pull::Up => w.set_mode(PioMode::PULL_UP),
+            Pull::Down => w.set_mode(PioMode::PULL_DOWN),
+        });
+    }
+
     /// Set the pin to digital mode. This is required for using a pin as a GPIO pin. The default
     /// setting for pins is (usually) non-digital.
     fn set_as_digital(&mut self) {
-        match_iocon!(register, self.pin_bank(), self.pin_number(), {
-            register.modify(|w| w.set_digimode(PioDigimode::DIGITAL));
+        self.pin.pio().modify(|w| {
+            w.set_digimode(PioDigimode::DIGITAL);
         });
     }
 
@@ -220,6 +224,14 @@ impl<'d> Flex<'d> {
 pub(crate) trait SealedPin: Sized {
     fn pin_bank(&self) -> Bank;
     fn pin_number(&self) -> u8;
+
+    #[inline]
+    fn pio(&self) -> Reg<iocon::regs::Pio, RW> {
+        match self.pin_bank() {
+            Bank::Bank0 => IOCON.pio0(self.pin_number() as usize),
+            Bank::Bank1 => IOCON.pio1(self.pin_number() as usize),
+        }
+    }
 }
 
 /// Interface for a Pin that can be configured by an [Input] or [Output] driver, or converted to an
@@ -272,40 +284,6 @@ impl SealedPin for AnyPin {
     }
 }
 
-/// Match the pin bank and number of a pin to the corresponding IOCON register.
-///
-/// # Example
-/// ```
-/// use embassy_nxp::gpio::Bank;
-/// use embassy_nxp::pac_utils::{iocon_reg, match_iocon};
-///
-/// // Make pin PIO1_6 digital and set it to pull-down mode.
-/// match_iocon!(register, Bank::Bank1, 6, {
-///     register.modify(|w|{
-///         w.set_mode(PioMode::PULL_DOWN);
-///         w.set_digimode(PioDigimode::DIGITAL);
-///
-///     }
-/// });
-/// ```
-macro_rules! match_iocon {
-    ($register:ident, $pin_bank:expr, $pin_number:expr, $action:expr) => {
-        match $pin_bank {
-            Bank::Bank0 => {
-                let $register = IOCON.pio0($pin_number as usize);
-                $action;
-            }
-
-            Bank::Bank1 => {
-                let $register = IOCON.pio1($pin_number as usize);
-                $action;
-            }
-        }
-    };
-}
-
-pub(crate) use match_iocon;
-
 macro_rules! impl_pin {
     ($name:ident, $bank:expr, $pin_num:expr) => {
         impl Pin for peripherals::$name {}
diff --git a/embassy-nxp/src/lib.rs b/embassy-nxp/src/lib.rs
index 9576f02b1..4058881a5 100644
--- a/embassy-nxp/src/lib.rs
+++ b/embassy-nxp/src/lib.rs
@@ -10,6 +10,8 @@ pub mod gpio;
 #[cfg(feature = "lpc55-core0")]
 pub mod pint;
 #[cfg(feature = "lpc55-core0")]
+pub mod pwm;
+#[cfg(feature = "lpc55-core0")]
 pub mod usart;
 
 #[cfg(feature = "_time_driver")]
@@ -154,7 +156,10 @@ pub fn init(_config: config::Config) -> Peripherals {
     gpio::init();
 
     #[cfg(feature = "lpc55-core0")]
-    pint::init();
+    {
+        pint::init();
+        pwm::Pwm::reset();
+    }
 
     #[cfg(feature = "_time_driver")]
     time_driver::init();
diff --git a/embassy-nxp/src/pwm.rs b/embassy-nxp/src/pwm.rs
new file mode 100644
index 000000000..68980924a
--- /dev/null
+++ b/embassy-nxp/src/pwm.rs
@@ -0,0 +1,5 @@
+//! Pulse-Width Modulation (PWM) driver.
+
+#[cfg_attr(feature = "lpc55-core0", path = "./pwm/lpc55.rs")]
+mod inner;
+pub use inner::*;
diff --git a/embassy-nxp/src/pwm/lpc55.rs b/embassy-nxp/src/pwm/lpc55.rs
new file mode 100644
index 000000000..197184ad6
--- /dev/null
+++ b/embassy-nxp/src/pwm/lpc55.rs
@@ -0,0 +1,325 @@
+use core::sync::atomic::{AtomicU8, AtomicU32, Ordering};
+
+use embassy_hal_internal::{Peri, PeripheralType};
+
+use crate::gpio::AnyPin;
+use crate::pac::iocon::vals::{PioDigimode, PioFunc, PioMode, PioOd, PioSlew};
+use crate::pac::sct0::vals;
+use crate::pac::syscon::vals::{SctRst, SctclkselSel};
+use crate::pac::{SCT0, SYSCON};
+
+// Since for now the counter is shared, the TOP value has to be kept.
+static TOP_VALUE: AtomicU32 = AtomicU32::new(0);
+// To check if there are still active instances.
+static REF_COUNT: AtomicU8 = AtomicU8::new(0);
+
+/// The configuration of a PWM output.
+/// Note the period in clock cycles of an output can be computed as:
+/// `(top + 1) * (phase_correct ? 1 : 2) * divider * prescale_factor`
+/// By default, the clock used is 96 MHz.
+#[non_exhaustive]
+#[derive(Clone)]
+pub struct Config {
+    /// Inverts the PWM output signal.
+    pub invert: bool,
+    /// Enables phase-correct mode for PWM operation.
+    /// In phase-correct mode, the PWM signal is generated in such a way that
+    /// the pulse is always centered regardless of the duty cycle.
+    /// The output frequency is halved when phase-correct mode is enabled.
+    pub phase_correct: bool,
+    /// Enables the PWM output, allowing it to generate an output.
+    pub enable: bool,
+    /// A SYSCON clock divider allows precise control over
+    /// the PWM output frequency by gating the PWM counter increment.
+    /// A higher value will result in a slower output frequency.
+    /// The clock is divided by `divider + 1`.
+    pub divider: u8,
+    /// Specifies the factor by which the SCT clock is prescaled to produce the unified
+    /// counter clock. The counter clock is clocked at the rate of the SCT clock divided by
+    /// `PRE + 1`.
+    pub prescale_factor: u8,
+    /// The output goes high when `compare` is higher than the
+    /// counter. A compare of 0 will produce an always low output, while a
+    /// compare of `top` will produce an always high output.
+    pub compare: u32,
+    /// The point at which the counter resets, representing the maximum possible
+    /// period. The counter will either wrap to 0 or reverse depending on the
+    /// setting of `phase_correct`.
+    pub top: u32,
+}
+
+impl Config {
+    pub fn new(compare: u32, top: u32) -> Self {
+        Self {
+            invert: false,
+            phase_correct: false,
+            enable: true,
+            divider: 255,
+            prescale_factor: 255,
+            compare,
+            top,
+        }
+    }
+}
+
+/// PWM driver.
+pub struct Pwm<'d> {
+    _pin: Peri<'d, AnyPin>,
+    output: usize,
+}
+
+impl<'d> Pwm<'d> {
+    pub(crate) fn reset() {
+        // Reset SCTimer => Reset counter and halt it.
+        // It should be done only once during the initialization of the board.
+        SYSCON.presetctrl1().modify(|w| w.set_sct_rst(SctRst::ASSERTED));
+        SYSCON.presetctrl1().modify(|w| w.set_sct_rst(SctRst::RELEASED));
+    }
+    fn new_inner<T: Output>(output: usize, channel: Peri<'d, impl OutputChannelPin<T>>, config: Config) -> Self {
+        // Enable clocks (Syscon is enabled by default)
+        critical_section::with(|_cs| {
+            if !SYSCON.ahbclkctrl0().read().iocon() {
+                SYSCON.ahbclkctrl0().modify(|w| w.set_iocon(true));
+            }
+            if !SYSCON.ahbclkctrl1().read().sct() {
+                SYSCON.ahbclkctrl1().modify(|w| w.set_sct(true));
+            }
+        });
+
+        // Choose the clock for PWM.
+        SYSCON.sctclksel().modify(|w| w.set_sel(SctclkselSel::ENUM_0X3));
+        // For now, 96 MHz.
+
+        // IOCON Setup
+        channel.pio().modify(|w| {
+            w.set_func(channel.pin_func());
+            w.set_digimode(PioDigimode::DIGITAL);
+            w.set_slew(PioSlew::STANDARD);
+            w.set_mode(PioMode::INACTIVE);
+            w.set_od(PioOd::NORMAL);
+        });
+
+        Self::configure(output, &config);
+        REF_COUNT.fetch_add(1, Ordering::Relaxed);
+        Self {
+            _pin: channel.into(),
+            output,
+        }
+    }
+
+    /// Create PWM driver with a single 'a' pin as output.
+    #[inline]
+    pub fn new_output<T: Output>(
+        output: Peri<'d, T>,
+        channel: Peri<'d, impl OutputChannelPin<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(output.number(), channel, config)
+    }
+
+    /// Set the PWM config.
+    pub fn set_config(&mut self, config: &Config) {
+        Self::configure(self.output, config);
+    }
+
+    fn configure(output_number: usize, config: &Config) {
+        // Stop and reset the counter
+        SCT0.ctrl().modify(|w| {
+            if config.phase_correct {
+                w.set_bidir_l(vals::Bidir::UP_DOWN);
+            } else {
+                w.set_bidir_l(vals::Bidir::UP);
+            }
+            w.set_halt_l(true); // halt the counter to make new changes
+            w.set_clrctr_l(true); // clear the counter
+        });
+        // Divides clock by 1-255
+        SYSCON.sctclkdiv().modify(|w| w.set_div(config.divider));
+
+        SCT0.config().modify(|w| {
+            w.set_unify(vals::Unify::UNIFIED_COUNTER);
+            w.set_clkmode(vals::Clkmode::SYSTEM_CLOCK_MODE);
+            w.set_noreload_l(true);
+            w.set_autolimit_l(true);
+        });
+
+        // Before setting the match registers, we have to make sure that `compare` is lower or equal to `top`,
+        // otherwise the counter will not reach the match and, therefore, no events will happen.
+        assert!(config.compare <= config.top);
+
+        if TOP_VALUE.load(Ordering::Relaxed) == 0 {
+            // Match 0 will reset the timer using TOP value
+            SCT0.match_(0).modify(|w| {
+                w.set_matchn_l((config.top & 0xFFFF) as u16);
+                w.set_matchn_h((config.top >> 16) as u16);
+            });
+        } else {
+            panic!("The top value cannot be changed after the initialization.");
+        }
+        // The actual matches that are used for event logic
+        SCT0.match_(output_number + 1).modify(|w| {
+            w.set_matchn_l((config.compare & 0xFFFF) as u16);
+            w.set_matchn_h((config.compare >> 16) as u16);
+        });
+
+        SCT0.match_(15).modify(|w| {
+            w.set_matchn_l(0);
+            w.set_matchn_h(0);
+        });
+
+        // Event configuration
+        critical_section::with(|_cs| {
+            // If it is already set, don't change
+            if SCT0.ev(0).ev_ctrl().read().matchsel() != 15 {
+                SCT0.ev(0).ev_ctrl().modify(|w| {
+                    w.set_matchsel(15);
+                    w.set_combmode(vals::Combmode::MATCH);
+                    // STATE + statev, where STATE is a on-board variable.
+                    w.set_stateld(vals::Stateld::ADD);
+                    w.set_statev(0);
+                });
+            }
+        });
+        SCT0.ev(output_number + 1).ev_ctrl().modify(|w| {
+            w.set_matchsel((output_number + 1) as u8);
+            w.set_combmode(vals::Combmode::MATCH);
+            w.set_stateld(vals::Stateld::ADD);
+            // STATE + statev, where STATE is a on-board variable.
+            w.set_statev(0);
+        });
+
+        // Assign events to states
+        SCT0.ev(0).ev_state().modify(|w| w.set_statemskn(1 << 0));
+        SCT0.ev(output_number + 1)
+            .ev_state()
+            .modify(|w| w.set_statemskn(1 << 0));
+        // TODO(frihetselsker): optimize nxp-pac so that `set_clr` and `set_set` are turned into a bit array.
+        if config.invert {
+            // Low when event 0 is active
+            SCT0.out(output_number).out_clr().modify(|w| w.set_clr(1 << 0));
+            // High when event `output_number + 1` is active
+            SCT0.out(output_number)
+                .out_set()
+                .modify(|w| w.set_set(1 << (output_number + 1)));
+        } else {
+            // High when event 0 is active
+            SCT0.out(output_number).out_set().modify(|w| w.set_set(1 << 0));
+            // Low when event `output_number + 1` is active
+            SCT0.out(output_number)
+                .out_clr()
+                .modify(|w| w.set_clr(1 << (output_number + 1)));
+        }
+
+        if config.phase_correct {
+            // Take into account the set matches and reverse their actions while counting back.
+            SCT0.outputdirctrl()
+                .modify(|w| w.set_setclr(output_number, vals::Setclr::L_REVERSED));
+        }
+
+        // State 0 by default
+        SCT0.state().modify(|w| w.set_state_l(0));
+        // Remove halt and start the actual counter
+        SCT0.ctrl().modify(|w| {
+            w.set_halt_l(!config.enable);
+        });
+    }
+
+    /// Read PWM counter.
+    #[inline]
+    pub fn counter(&self) -> u32 {
+        SCT0.count().read().0
+    }
+}
+
+impl<'d> Drop for Pwm<'d> {
+    fn drop(&mut self) {
+        REF_COUNT.fetch_sub(1, Ordering::AcqRel);
+        if REF_COUNT.load(Ordering::Acquire) == 0 {
+            TOP_VALUE.store(0, Ordering::Release);
+        }
+    }
+}
+
+trait SealedOutput {
+    /// Output number.
+    fn number(&self) -> usize;
+}
+
+/// PWM Output.
+#[allow(private_bounds)]
+pub trait Output: PeripheralType + SealedOutput {}
+
+macro_rules! output {
+    ($name:ident, $num:expr) => {
+        impl SealedOutput for crate::peripherals::$name {
+            fn number(&self) -> usize {
+                $num
+            }
+        }
+        impl Output for crate::peripherals::$name {}
+    };
+}
+
+output!(PWM_OUTPUT0, 0);
+output!(PWM_OUTPUT1, 1);
+output!(PWM_OUTPUT2, 2);
+output!(PWM_OUTPUT3, 3);
+output!(PWM_OUTPUT4, 4);
+output!(PWM_OUTPUT5, 5);
+output!(PWM_OUTPUT6, 6);
+output!(PWM_OUTPUT7, 7);
+output!(PWM_OUTPUT8, 8);
+output!(PWM_OUTPUT9, 9);
+
+/// PWM Output Channel.
+pub trait OutputChannelPin<T: Output>: crate::gpio::Pin {
+    fn pin_func(&self) -> PioFunc;
+}
+
+macro_rules! impl_pin {
+    ($pin:ident, $output:ident, $func:ident) => {
+        impl crate::pwm::inner::OutputChannelPin<crate::peripherals::$output> for crate::peripherals::$pin {
+            fn pin_func(&self) -> PioFunc {
+                PioFunc::$func
+            }
+        }
+    };
+}
+
+impl_pin!(PIO0_2, PWM_OUTPUT0, ALT3);
+impl_pin!(PIO0_17, PWM_OUTPUT0, ALT4);
+impl_pin!(PIO1_4, PWM_OUTPUT0, ALT4);
+impl_pin!(PIO1_23, PWM_OUTPUT0, ALT2);
+
+impl_pin!(PIO0_3, PWM_OUTPUT1, ALT3);
+impl_pin!(PIO0_18, PWM_OUTPUT1, ALT4);
+impl_pin!(PIO1_8, PWM_OUTPUT1, ALT4);
+impl_pin!(PIO1_24, PWM_OUTPUT1, ALT2);
+
+impl_pin!(PIO0_10, PWM_OUTPUT2, ALT5);
+impl_pin!(PIO0_15, PWM_OUTPUT2, ALT4);
+impl_pin!(PIO0_19, PWM_OUTPUT2, ALT4);
+impl_pin!(PIO1_9, PWM_OUTPUT2, ALT4);
+impl_pin!(PIO1_25, PWM_OUTPUT2, ALT2);
+
+impl_pin!(PIO0_22, PWM_OUTPUT3, ALT4);
+impl_pin!(PIO0_31, PWM_OUTPUT3, ALT4);
+impl_pin!(PIO1_10, PWM_OUTPUT3, ALT4);
+impl_pin!(PIO1_26, PWM_OUTPUT3, ALT2);
+
+impl_pin!(PIO0_23, PWM_OUTPUT4, ALT4);
+impl_pin!(PIO1_3, PWM_OUTPUT4, ALT4);
+impl_pin!(PIO1_17, PWM_OUTPUT4, ALT4);
+
+impl_pin!(PIO0_26, PWM_OUTPUT5, ALT4);
+impl_pin!(PIO1_18, PWM_OUTPUT5, ALT4);
+
+impl_pin!(PIO0_27, PWM_OUTPUT6, ALT4);
+impl_pin!(PIO1_31, PWM_OUTPUT6, ALT4);
+
+impl_pin!(PIO0_28, PWM_OUTPUT7, ALT4);
+impl_pin!(PIO1_19, PWM_OUTPUT7, ALT2);
+
+impl_pin!(PIO0_29, PWM_OUTPUT8, ALT4);
+
+impl_pin!(PIO0_30, PWM_OUTPUT9, ALT4);
diff --git a/embassy-nxp/src/usart/lpc55.rs b/embassy-nxp/src/usart/lpc55.rs
index 0be5a8ce7..d54927b25 100644
--- a/embassy-nxp/src/usart/lpc55.rs
+++ b/embassy-nxp/src/usart/lpc55.rs
@@ -11,7 +11,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 use embedded_io::{self, ErrorKind};
 
 use crate::dma::{AnyChannel, Channel};
-use crate::gpio::{AnyPin, Bank, SealedPin, match_iocon};
+use crate::gpio::{AnyPin, SealedPin};
 use crate::interrupt::Interrupt;
 use crate::interrupt::typelevel::{Binding, Interrupt as _};
 use crate::pac::flexcomm::Flexcomm as FlexcommReg;
@@ -146,7 +146,8 @@ impl<'d, M: Mode> UsartTx<'d, M> {
         tx_dma: Peri<'d, impl Channel>,
         config: Config,
     ) -> Self {
-        Usart::<M>::init::<T>(Some(tx.into()), None, config);
+        let tx_func = tx.pin_func();
+        Usart::<M>::init::<T>(Some((tx.into(), tx_func)), None, config);
         Self::new_inner(T::info(), Some(tx_dma.into()))
     }
 
@@ -179,7 +180,8 @@ impl<'d, M: Mode> UsartTx<'d, M> {
 
 impl<'d> UsartTx<'d, Blocking> {
     pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, tx: Peri<'d, impl TxPin<T>>, config: Config) -> Self {
-        Usart::<Blocking>::init::<T>(Some(tx.into()), None, config);
+        let tx_func = tx.pin_func();
+        Usart::<Blocking>::init::<T>(Some((tx.into(), tx_func)), None, config);
         Self::new_inner(T::info(), None)
     }
 }
@@ -208,7 +210,8 @@ impl<'d, M: Mode> UsartRx<'d, M> {
         rx_dma: Peri<'d, impl Channel>,
         config: Config,
     ) -> Self {
-        Usart::<M>::init::<T>(None, Some(rx.into()), config);
+        let rx_func = rx.pin_func();
+        Usart::<M>::init::<T>(None, Some((rx.into(), rx_func)), config);
         Self::new_inner(T::info(), T::dma_state(), has_irq, Some(rx_dma.into()))
     }
 
@@ -280,7 +283,8 @@ impl<'d, M: Mode> UsartRx<'d, M> {
 
 impl<'d> UsartRx<'d, Blocking> {
     pub fn new_blocking<T: Instance>(_usart: Peri<'d, T>, rx: Peri<'d, impl RxPin<T>>, config: Config) -> Self {
-        Usart::<Blocking>::init::<T>(None, Some(rx.into()), config);
+        let rx_func = rx.pin_func();
+        Usart::<Blocking>::init::<T>(None, Some((rx.into(), rx_func)), config);
         Self::new_inner(T::info(), T::dma_state(), false, None)
     }
 }
@@ -405,7 +409,10 @@ impl<'d> Usart<'d, Blocking> {
         rx: Peri<'d, impl RxPin<T>>,
         config: Config,
     ) -> Self {
-        Self::new_inner(usart, tx.into(), rx.into(), false, None, None, config)
+        let tx_func = tx.pin_func();
+        let rx_func = rx.pin_func();
+
+        Self::new_inner(usart, tx.into(), tx_func, rx.into(), rx_func, false, None, None, config)
     }
 }
 
@@ -419,10 +426,15 @@ impl<'d> Usart<'d, Async> {
         rx_dma: Peri<'d, impl RxChannel<T>>,
         config: Config,
     ) -> Self {
+        let tx_func = tx.pin_func();
+        let rx_func = rx.pin_func();
+
         Self::new_inner(
             uart,
             tx.into(),
+            tx_func,
             rx.into(),
+            rx_func,
             true,
             Some(tx_dma.into()),
             Some(rx_dma.into()),
@@ -435,20 +447,26 @@ impl<'d, M: Mode> Usart<'d, M> {
     fn new_inner<T: Instance>(
         _usart: Peri<'d, T>,
         mut tx: Peri<'d, AnyPin>,
+        tx_func: PioFunc,
         mut rx: Peri<'d, AnyPin>,
+        rx_func: PioFunc,
         has_irq: bool,
         tx_dma: Option<Peri<'d, AnyChannel>>,
         rx_dma: Option<Peri<'d, AnyChannel>>,
         config: Config,
     ) -> Self {
-        Self::init::<T>(Some(tx.reborrow()), Some(rx.reborrow()), config);
+        Self::init::<T>(Some((tx.reborrow(), tx_func)), Some((rx.reborrow(), rx_func)), config);
         Self {
             tx: UsartTx::new_inner(T::info(), tx_dma),
             rx: UsartRx::new_inner(T::info(), T::dma_state(), has_irq, rx_dma),
         }
     }
 
-    fn init<T: Instance>(tx: Option<Peri<'_, AnyPin>>, rx: Option<Peri<'_, AnyPin>>, config: Config) {
+    fn init<T: Instance>(
+        tx: Option<(Peri<'_, AnyPin>, PioFunc)>,
+        rx: Option<(Peri<'_, AnyPin>, PioFunc)>,
+        config: Config,
+    ) {
         Self::configure_flexcomm(T::info().fc_reg, T::instance_number());
         Self::configure_clock::<T>(&config);
         Self::pin_config::<T>(tx, rx);
@@ -553,31 +571,27 @@ impl<'d, M: Mode> Usart<'d, M> {
             .modify(|w| w.set_brgval((brg_value - 1) as u16));
     }
 
-    fn pin_config<T: Instance>(tx: Option<Peri<'_, AnyPin>>, rx: Option<Peri<'_, AnyPin>>) {
-        if let Some(tx_pin) = tx {
-            match_iocon!(register, tx_pin.pin_bank(), tx_pin.pin_number(), {
-                register.modify(|w| {
-                    w.set_func(T::tx_pin_func());
-                    w.set_mode(iocon::vals::PioMode::INACTIVE);
-                    w.set_slew(iocon::vals::PioSlew::STANDARD);
-                    w.set_invert(false);
-                    w.set_digimode(iocon::vals::PioDigimode::DIGITAL);
-                    w.set_od(iocon::vals::PioOd::NORMAL);
-                });
-            })
+    fn pin_config<T: Instance>(tx: Option<(Peri<'_, AnyPin>, PioFunc)>, rx: Option<(Peri<'_, AnyPin>, PioFunc)>) {
+        if let Some((tx_pin, func)) = tx {
+            tx_pin.pio().modify(|w| {
+                w.set_func(func);
+                w.set_mode(iocon::vals::PioMode::INACTIVE);
+                w.set_slew(iocon::vals::PioSlew::STANDARD);
+                w.set_invert(false);
+                w.set_digimode(iocon::vals::PioDigimode::DIGITAL);
+                w.set_od(iocon::vals::PioOd::NORMAL);
+            });
         }
 
-        if let Some(rx_pin) = rx {
-            match_iocon!(register, rx_pin.pin_bank(), rx_pin.pin_number(), {
-                register.modify(|w| {
-                    w.set_func(T::rx_pin_func());
-                    w.set_mode(iocon::vals::PioMode::INACTIVE);
-                    w.set_slew(iocon::vals::PioSlew::STANDARD);
-                    w.set_invert(false);
-                    w.set_digimode(iocon::vals::PioDigimode::DIGITAL);
-                    w.set_od(iocon::vals::PioOd::NORMAL);
-                });
-            })
+        if let Some((rx_pin, func)) = rx {
+            rx_pin.pio().modify(|w| {
+                w.set_func(func);
+                w.set_mode(iocon::vals::PioMode::INACTIVE);
+                w.set_slew(iocon::vals::PioSlew::STANDARD);
+                w.set_invert(false);
+                w.set_digimode(iocon::vals::PioDigimode::DIGITAL);
+                w.set_od(iocon::vals::PioOd::NORMAL);
+            });
         };
     }
 
@@ -814,8 +828,6 @@ trait SealedInstance {
     fn info() -> &'static Info;
     fn dma_state() -> &'static DmaState;
     fn instance_number() -> usize;
-    fn tx_pin_func() -> PioFunc;
-    fn rx_pin_func() -> PioFunc;
 }
 
 /// UART instance.
@@ -826,7 +838,7 @@ pub trait Instance: SealedInstance + PeripheralType {
 }
 
 macro_rules! impl_instance {
-    ($inst:ident, $fc:ident, $tx_pin:ident, $rx_pin:ident, $fc_num:expr) => {
+    ($inst:ident, $fc:ident, $fc_num:expr) => {
         impl $crate::usart::inner::SealedInstance for $crate::peripherals::$inst {
             fn info() -> &'static Info {
                 static INFO: Info = Info {
@@ -848,14 +860,6 @@ macro_rules! impl_instance {
             fn instance_number() -> usize {
                 $fc_num
             }
-            #[inline]
-            fn tx_pin_func() -> PioFunc {
-                PioFunc::$tx_pin
-            }
-            #[inline]
-            fn rx_pin_func() -> PioFunc {
-                PioFunc::$rx_pin
-            }
         }
         impl $crate::usart::Instance for $crate::peripherals::$inst {
             type Interrupt = crate::interrupt::typelevel::$fc;
@@ -863,45 +867,72 @@ macro_rules! impl_instance {
     };
 }
 
-impl_instance!(USART0, FLEXCOMM0, ALT1, ALT1, 0);
-impl_instance!(USART1, FLEXCOMM1, ALT2, ALT2, 1);
-impl_instance!(USART2, FLEXCOMM2, ALT1, ALT1, 2);
-impl_instance!(USART3, FLEXCOMM3, ALT1, ALT1, 3);
-impl_instance!(USART4, FLEXCOMM4, ALT1, ALT2, 4);
-impl_instance!(USART5, FLEXCOMM5, ALT3, ALT3, 5);
-impl_instance!(USART6, FLEXCOMM6, ALT2, ALT2, 6);
-impl_instance!(USART7, FLEXCOMM7, ALT7, ALT7, 7);
+impl_instance!(USART0, FLEXCOMM0, 0);
+impl_instance!(USART1, FLEXCOMM1, 1);
+impl_instance!(USART2, FLEXCOMM2, 2);
+impl_instance!(USART3, FLEXCOMM3, 3);
+impl_instance!(USART4, FLEXCOMM4, 4);
+impl_instance!(USART5, FLEXCOMM5, 5);
+impl_instance!(USART6, FLEXCOMM6, 6);
+impl_instance!(USART7, FLEXCOMM7, 7);
+
+pub(crate) trait SealedTxPin<T: Instance>: crate::gpio::Pin {
+    fn pin_func(&self) -> PioFunc;
+}
+
+pub(crate) trait SealedRxPin<T: Instance>: crate::gpio::Pin {
+    fn pin_func(&self) -> PioFunc;
+}
 
 /// Trait for TX pins.
-pub trait TxPin<T: Instance>: crate::gpio::Pin {}
+#[allow(private_bounds)]
+pub trait TxPin<T: Instance>: SealedTxPin<T> + crate::gpio::Pin {}
+
 /// Trait for RX pins.
-pub trait RxPin<T: Instance>: crate::gpio::Pin {}
+#[allow(private_bounds)]
+pub trait RxPin<T: Instance>: SealedRxPin<T> + crate::gpio::Pin {}
+
+macro_rules! impl_tx_pin {
+    ($pin:ident, $instance:ident, $func: ident) => {
+        impl SealedTxPin<crate::peripherals::$instance> for crate::peripherals::$pin {
+            fn pin_func(&self) -> PioFunc {
+                PioFunc::$func
+            }
+        }
 
-macro_rules! impl_pin {
-    ($pin:ident, $instance:ident, Tx) => {
         impl TxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
     };
-    ($pin:ident, $instance:ident, Rx) => {
+}
+
+macro_rules! impl_rx_pin {
+    ($pin:ident, $instance:ident, $func: ident) => {
+        impl SealedRxPin<crate::peripherals::$instance> for crate::peripherals::$pin {
+            fn pin_func(&self) -> PioFunc {
+                PioFunc::$func
+            }
+        }
+
         impl RxPin<crate::peripherals::$instance> for crate::peripherals::$pin {}
     };
 }
 
-impl_pin!(PIO1_6, USART0, Tx);
-impl_pin!(PIO1_5, USART0, Rx);
-impl_pin!(PIO1_11, USART1, Tx);
-impl_pin!(PIO1_10, USART1, Rx);
-impl_pin!(PIO0_27, USART2, Tx);
-impl_pin!(PIO1_24, USART2, Rx);
-impl_pin!(PIO0_2, USART3, Tx);
-impl_pin!(PIO0_3, USART3, Rx);
-impl_pin!(PIO0_16, USART4, Tx);
-impl_pin!(PIO0_5, USART4, Rx);
-impl_pin!(PIO0_9, USART5, Tx);
-impl_pin!(PIO0_8, USART5, Rx);
-impl_pin!(PIO1_16, USART6, Tx);
-impl_pin!(PIO1_13, USART6, Rx);
-impl_pin!(PIO0_19, USART7, Tx);
-impl_pin!(PIO0_20, USART7, Rx);
+impl_tx_pin!(PIO1_6, USART0, ALT1);
+impl_tx_pin!(PIO1_11, USART1, ALT2);
+impl_tx_pin!(PIO0_27, USART2, ALT1);
+impl_tx_pin!(PIO0_2, USART3, ALT1);
+impl_tx_pin!(PIO0_16, USART4, ALT1);
+impl_tx_pin!(PIO0_9, USART5, ALT3);
+impl_tx_pin!(PIO1_16, USART6, ALT2);
+impl_tx_pin!(PIO0_19, USART7, ALT7);
+
+impl_rx_pin!(PIO1_5, USART0, ALT1);
+impl_rx_pin!(PIO1_10, USART1, ALT2);
+impl_rx_pin!(PIO1_24, USART2, ALT1);
+impl_rx_pin!(PIO0_3, USART3, ALT1);
+impl_rx_pin!(PIO0_5, USART4, ALT2);
+impl_rx_pin!(PIO0_8, USART5, ALT3);
+impl_rx_pin!(PIO1_13, USART6, ALT2);
+impl_rx_pin!(PIO0_20, USART7, ALT7);
 
 /// Trait for TX DMA channels.
 pub trait TxChannel<T: Instance>: crate::dma::Channel {}
diff --git a/embassy-rp/CHANGELOG.md b/embassy-rp/CHANGELOG.md
index e932bcaa3..57ec13658 100644
--- a/embassy-rp/CHANGELOG.md
+++ b/embassy-rp/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+- Fix several minor typos in documentation
 - Add PIO SPI
 - Add PIO I2S input
 - Add PIO onewire parasite power strong pullup
diff --git a/embassy-rp/src/block.rs b/embassy-rp/src/block.rs
index a3e1ad925..745883b83 100644
--- a/embassy-rp/src/block.rs
+++ b/embassy-rp/src/block.rs
@@ -240,7 +240,7 @@ impl UnpartitionedSpace {
         }
     }
 
-    /// Create a new unpartition space from run-time values.
+    /// Create a new unpartitioned space from run-time values.
     ///
     /// Get these from the ROM function `get_partition_table_info` with an argument of `PT_INFO`.
     pub const fn from_raw(permissions_and_location: u32, permissions_and_flags: u32) -> Self {
@@ -714,7 +714,7 @@ impl PartitionTableBlock {
         new_table
     }
 
-    /// Add a a SHA256 hash of the Block
+    /// Add a SHA256 hash of the Block
     ///
     /// Adds a `HASH_DEF` covering all the previous items in the Block, and a
     /// `HASH_VALUE` with a SHA-256 hash of them.
diff --git a/embassy-rp/src/clocks.rs b/embassy-rp/src/clocks.rs
index 56892d7a2..8bfb5129a 100644
--- a/embassy-rp/src/clocks.rs
+++ b/embassy-rp/src/clocks.rs
@@ -267,7 +267,7 @@ impl CoreVoltage {
     }
 }
 
-/// CLock configuration.
+/// Clock configuration.
 #[non_exhaustive]
 pub struct ClockConfig {
     /// Ring oscillator configuration.
diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs
index c15e0e41b..154fc1585 100644
--- a/embassy-rp/src/gpio.rs
+++ b/embassy-rp/src/gpio.rs
@@ -300,7 +300,7 @@ impl<'d> InputFuture<'d> {
 
         // Each INTR register is divided into 8 groups, one group for each
         // pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW,
-        // and EGDE_HIGH.
+        // and EDGE_HIGH.
         pin.int_proc()
             .inte((pin.pin() / 8) as usize)
             .write_set(|w| match level {
diff --git a/embassy-rp/src/i2c_slave.rs b/embassy-rp/src/i2c_slave.rs
index 770087bc8..0853709df 100644
--- a/embassy-rp/src/i2c_slave.rs
+++ b/embassy-rp/src/i2c_slave.rs
@@ -52,7 +52,7 @@ pub enum ReadStatus {
     Done,
     /// Transaction Incomplete, controller trying to read more bytes than were provided
     NeedMoreBytes,
-    /// Transaction Complere, but controller stopped reading bytes before we ran out
+    /// Transaction Complete, but controller stopped reading bytes before we ran out
     LeftoverBytes(u16),
 }
 
@@ -240,7 +240,7 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
 
                 if p.ic_rxflr().read().rxflr() > 0 || me.pending_byte.is_some() {
                     me.drain_fifo(buffer, &mut len);
-                    // we're recieving data, set rx fifo watermark to 12 bytes (3/4 full) to reduce interrupt noise
+                    // we're receiving data, set rx fifo watermark to 12 bytes (3/4 full) to reduce interrupt noise
                     p.ic_rx_tl().write(|w| w.set_rx_tl(11));
                 }
 
diff --git a/embassy-rp/src/multicore.rs b/embassy-rp/src/multicore.rs
index 3b120e349..572d8db91 100644
--- a/embassy-rp/src/multicore.rs
+++ b/embassy-rp/src/multicore.rs
@@ -58,7 +58,7 @@ const PAUSE_TOKEN: u32 = 0xDEADBEEF;
 const RESUME_TOKEN: u32 = !0xDEADBEEF;
 static IS_CORE1_INIT: AtomicBool = AtomicBool::new(false);
 
-/// Represents a partiticular CPU core (SIO_CPUID)
+/// Represents a particular CPU core (SIO_CPUID)
 #[derive(Debug, PartialEq, Eq, Clone, Copy, Hash)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[repr(u8)]
diff --git a/embassy-rp/src/pio/mod.rs b/embassy-rp/src/pio/mod.rs
index 38ee1f97c..92b2c603e 100644
--- a/embassy-rp/src/pio/mod.rs
+++ b/embassy-rp/src/pio/mod.rs
@@ -62,7 +62,7 @@ pub enum FifoJoin {
     #[cfg(feature = "_rp235x")]
     RxAsControl,
     /// FJOIN_RX_PUT | FJOIN_RX_GET: RX can be used as a scratch register,
-    /// not accesible from the CPU
+    /// not accessible from the CPU
     #[cfg(feature = "_rp235x")]
     PioScratch,
 }
diff --git a/embassy-rp/src/pio_programs/i2s.rs b/embassy-rp/src/pio_programs/i2s.rs
index 7e5f68ad6..5c49beecb 100644
--- a/embassy-rp/src/pio_programs/i2s.rs
+++ b/embassy-rp/src/pio_programs/i2s.rs
@@ -1,4 +1,4 @@
-//! Pio backed I2s output and output drivers
+//! Pio backed I2S output and output drivers
 
 use fixed::traits::ToFixed;
 
@@ -9,7 +9,7 @@ use crate::pio::{
     Common, Config, Direction, FifoJoin, Instance, LoadedProgram, PioPin, ShiftConfig, ShiftDirection, StateMachine,
 };
 
-/// This struct represents an i2s receiver & controller driver program
+/// This struct represents an I2S receiver & controller driver program
 pub struct PioI2sInProgram<'d, PIO: Instance> {
     prg: LoadedProgram<'d, PIO>,
 }
@@ -35,7 +35,7 @@ impl<'d, PIO: Instance> PioI2sInProgram<'d, PIO> {
     }
 }
 
-/// Pio backed I2s input driver
+/// Pio backed I2S input driver
 pub struct PioI2sIn<'d, P: Instance, const S: usize> {
     dma: Peri<'d, AnyChannel>,
     sm: StateMachine<'d, P, S>,
@@ -50,7 +50,7 @@ impl<'d, P: Instance, const S: usize> PioI2sIn<'d, P, S> {
         // Whether or not to use the MCU's internal pull-down resistor, as the
         // Pico 2 is known to have problems with the inbuilt pulldowns, many
         // opt to just use an external pull down resistor to meet requirements of common
-        // i2s microphones such as the INMP441
+        // I2S microphones such as the INMP441
         data_pulldown: bool,
         data_pin: Peri<'d, impl PioPin>,
         bit_clock_pin: Peri<'d, impl PioPin>,
@@ -90,13 +90,13 @@ impl<'d, P: Instance, const S: usize> PioI2sIn<'d, P, S> {
         Self { dma: dma.into(), sm }
     }
 
-    /// Return an in-prograss dma transfer future. Awaiting it will guarentee a complete transfer.
+    /// Return an in-progress dma transfer future. Awaiting it will guarantee a complete transfer.
     pub fn read<'b>(&'b mut self, buff: &'b mut [u32]) -> Transfer<'b, AnyChannel> {
         self.sm.rx().dma_pull(self.dma.reborrow(), buff, false)
     }
 }
 
-/// This struct represents an i2s output driver program
+/// This struct represents an I2S output driver program
 ///
 /// The sample bit-depth is set through scratch register `Y`.
 /// `Y` has to be set to sample bit-depth - 2.
@@ -128,14 +128,14 @@ impl<'d, PIO: Instance> PioI2sOutProgram<'d, PIO> {
     }
 }
 
-/// Pio backed I2s output driver
+/// Pio backed I2S output driver
 pub struct PioI2sOut<'d, P: Instance, const S: usize> {
     dma: Peri<'d, AnyChannel>,
     sm: StateMachine<'d, P, S>,
 }
 
 impl<'d, P: Instance, const S: usize> PioI2sOut<'d, P, S> {
-    /// Configure a state machine to output I2s
+    /// Configure a state machine to output I2S
     pub fn new(
         common: &mut Common<'d, P>,
         mut sm: StateMachine<'d, P, S>,
@@ -179,7 +179,7 @@ impl<'d, P: Instance, const S: usize> PioI2sOut<'d, P, S> {
         Self { dma: dma.into(), sm }
     }
 
-    /// Return an in-prograss dma transfer future. Awaiting it will guarentee a complete transfer.
+    /// Return an in-progress dma transfer future. Awaiting it will guarantee a complete transfer.
     pub fn write<'b>(&'b mut self, buff: &'b [u32]) -> Transfer<'b, AnyChannel> {
         self.sm.tx().dma_push(self.dma.reborrow(), buff, false)
     }
diff --git a/embassy-rp/src/pio_programs/pwm.rs b/embassy-rp/src/pio_programs/pwm.rs
index ba06bb3c1..e4ad4a6f0 100644
--- a/embassy-rp/src/pio_programs/pwm.rs
+++ b/embassy-rp/src/pio_programs/pwm.rs
@@ -67,7 +67,7 @@ impl<'d, T: Instance, const SM: usize> PioPwm<'d, T, SM> {
         Self { sm, pin }
     }
 
-    /// Enable's the PIO program, continuing the wave generation from the PIO program.
+    /// Enables the PIO program, continuing the wave generation from the PIO program.
     pub fn start(&mut self) {
         self.sm.set_enable(true);
     }
diff --git a/embassy-rp/src/pio_programs/spi.rs b/embassy-rp/src/pio_programs/spi.rs
index b10fc6628..765ffaa06 100644
--- a/embassy-rp/src/pio_programs/spi.rs
+++ b/embassy-rp/src/pio_programs/spi.rs
@@ -1,4 +1,4 @@
-//! PIO backed SPi drivers
+//! PIO backed SPI drivers
 
 use core::marker::PhantomData;
 
@@ -83,7 +83,7 @@ pub enum Error {
     // No errors for now
 }
 
-/// PIO based Spi driver.
+/// PIO based SPI driver.
 /// Unlike other PIO programs, the PIO SPI driver owns and holds a reference to
 /// the PIO memory it uses. This is so that it can be reconfigured at runtime if
 /// desired.
diff --git a/embassy-rp/src/pio_programs/uart.rs b/embassy-rp/src/pio_programs/uart.rs
index 444efb5db..d59596dd1 100644
--- a/embassy-rp/src/pio_programs/uart.rs
+++ b/embassy-rp/src/pio_programs/uart.rs
@@ -130,7 +130,7 @@ impl<'d, PIO: Instance> PioUartRxProgram<'d, PIO> {
     }
 }
 
-/// PIO backed Uart reciever
+/// PIO backed Uart receiver
 pub struct PioUartRx<'d, PIO: Instance, const SM: usize> {
     sm_rx: StateMachine<'d, PIO, SM>,
 }
diff --git a/embassy-rp/src/rom_data/rp2040.rs b/embassy-rp/src/rom_data/rp2040.rs
index 5a74eddd6..27a8d8981 100644
--- a/embassy-rp/src/rom_data/rp2040.rs
+++ b/embassy-rp/src/rom_data/rp2040.rs
@@ -30,7 +30,7 @@ const DATA_TABLE: *const u16 = 0x0000_0016 as _;
 /// Address of the version number of the ROM.
 const VERSION_NUMBER: *const u8 = 0x0000_0013 as _;
 
-/// Retrive rom content from a table using a code.
+/// Retrieve rom content from a table using a code.
 fn rom_table_lookup<T>(table: *const u16, tag: RomFnTableCode) -> T {
     unsafe {
         let rom_table_lookup_ptr: *const u32 = rom_hword_as_ptr(ROM_TABLE_LOOKUP_PTR);
diff --git a/embassy-rp/src/rtc/mod.rs b/embassy-rp/src/rtc/mod.rs
index 68fb3b765..054572903 100644
--- a/embassy-rp/src/rtc/mod.rs
+++ b/embassy-rp/src/rtc/mod.rs
@@ -47,7 +47,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
         Self { inner }
     }
 
-    /// Enable or disable the leap year check. The rp2040 chip will always add a Feb 29th on every year that is divisable by 4, but this may be incorrect (e.g. on century years). This function allows you to disable this check.
+    /// Enable or disable the leap year check. The rp2040 chip will always add a Feb 29th on every year that is divisible by 4, but this may be incorrect (e.g. on century years). This function allows you to disable this check.
     ///
     /// Leap year checking is enabled by default.
     pub fn set_leap_year_check(&mut self, leap_year_check_enabled: bool) {
diff --git a/embassy-rp/src/spi.rs b/embassy-rp/src/spi.rs
index 559b3b909..d9410e78d 100644
--- a/embassy-rp/src/spi.rs
+++ b/embassy-rp/src/spi.rs
@@ -157,7 +157,7 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
 
     /// Private function to apply SPI configuration (phase, polarity, frequency) settings.
     ///
-    /// Driver should be disabled before making changes and reenabled after the modifications
+    /// Driver should be disabled before making changes and re-enabled after the modifications
     /// are applied.
     fn apply_config(inner: &Peri<'d, T>, config: &Config) {
         let p = inner.regs();
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index 43187df2d..8be87a5d2 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -315,7 +315,7 @@ impl<'d, M: Mode> UartRx<'d, M> {
     }
 
     /// Returns Ok(len) if no errors occurred. Returns Err((len, err)) if an error was
-    /// encountered. in both cases, `len` is the number of *good* bytes copied into
+    /// encountered. In both cases, `len` is the number of *good* bytes copied into
     /// `buffer`.
     fn drain_fifo(&mut self, buffer: &mut [u8]) -> Result<usize, (usize, Error)> {
         let r = self.info.regs;
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 7675567ff..9848daf49 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -11,6 +11,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 * **Fix(stm32h5):** Prevent a HardFault crash on STM32H5 devices by changing `uid()` to return `[u8; 12]` by value instead of a reference. (Fixes #2696)
 ## Unreleased - ReleaseDate
 
+- fix flash erase on L4 & L5
 - fix: Fixed STM32H5 builds requiring time feature
 - feat: Derive Clone, Copy for QSPI Config
 - fix: stm32/i2c in master mode (blocking): subsequent transmissions failed after a NACK was received
diff --git a/embassy-stm32/src/flash/l.rs b/embassy-stm32/src/flash/l.rs
index cd23cda5c..b3281f2d5 100644
--- a/embassy-stm32/src/flash/l.rs
+++ b/embassy-stm32/src/flash/l.rs
@@ -96,14 +96,20 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
     #[cfg(any(flash_wl, flash_wb, flash_l4, flash_l5))]
     {
         let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
+        #[cfg(any(flash_l4, flash_l5))]
+        let pgn = super::BANK1_REGION.size as u32 / super::BANK1_REGION.erase_size as u32;
 
         #[cfg(flash_l4)]
-        let (idx, bank) = if idx > 255 { (idx - 256, true) } else { (idx, false) };
+        let (idx, bank) = if idx > (pgn - 1) {
+            (idx - pgn, true)
+        } else {
+            (idx, false)
+        };
 
         #[cfg(flash_l5)]
         let (idx, bank) = if pac::FLASH.optr().read().dbank() {
-            if idx > 255 {
-                (idx - 256, Some(true))
+            if idx > (pgn - 1) {
+                (idx - pgn, Some(true))
             } else {
                 (idx, Some(false))
             }
diff --git a/examples/lpc55s69/src/bin/pwm.rs b/examples/lpc55s69/src/bin/pwm.rs
new file mode 100644
index 000000000..93b898b9d
--- /dev/null
+++ b/examples/lpc55s69/src/bin/pwm.rs
@@ -0,0 +1,18 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_nxp::pwm::{Config, Pwm};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_halt as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_nxp::init(Default::default());
+    let pwm = Pwm::new_output(p.PWM_OUTPUT1, p.PIO0_18, Config::new(1_000_000_000, 2_000_000_000));
+    loop {
+        info!("Counter: {}", pwm.counter());
+        Timer::after_millis(50).await;
+    }
+}