diff options
| author | antonello.contini <[email protected]> | 2025-02-25 19:59:57 +0100 |
|---|---|---|
| committer | antonello.contini <[email protected]> | 2025-02-25 19:59:57 +0100 |
| commit | f1c7e388e61bd9ba2362032dd45c9ab91cf3882f (patch) | |
| tree | b09405ca9af7fa5199a44665b0e3aca27f4fe526 | |
| parent | 00ef474b94d99a1fd933e79bd66628cd3a16e3c4 (diff) | |
do not use pllsrc for i2s; added field for plli2ssrc selection
| -rw-r--r-- | embassy-stm32/src/rcc/f247.rs | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs index 79d793dcc..7426b6792 100644 --- a/embassy-stm32/src/rcc/f247.rs +++ b/embassy-stm32/src/rcc/f247.rs | |||
| @@ -4,6 +4,9 @@ pub use crate::pac::rcc::vals::{ | |||
| 4 | Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, | 4 | Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, |
| 5 | Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk, | 5 | Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk, |
| 6 | }; | 6 | }; |
| 7 | |||
| 8 | #[cfg(any(stm32f413, stm32f423, stm32f412))] | ||
| 9 | pub use crate::pac::rcc::vals::Plli2ssrc as Plli2sSource; | ||
| 7 | #[cfg(any(stm32f4, stm32f7))] | 10 | #[cfg(any(stm32f4, stm32f7))] |
| 8 | use crate::pac::PWR; | 11 | use crate::pac::PWR; |
| 9 | use crate::pac::{FLASH, RCC}; | 12 | use crate::pac::{FLASH, RCC}; |
| @@ -84,6 +87,8 @@ pub struct Config { | |||
| 84 | pub sys: Sysclk, | 87 | pub sys: Sysclk, |
| 85 | 88 | ||
| 86 | pub pll_src: PllSource, | 89 | pub pll_src: PllSource, |
| 90 | #[cfg(any(stm32f413, stm32f423, stm32f412))] | ||
| 91 | pub plli2s_src: Plli2sSource, | ||
| 87 | 92 | ||
| 88 | pub pll: Option<Pll>, | 93 | pub pll: Option<Pll>, |
| 89 | #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))] | 94 | #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))] |
| @@ -111,6 +116,8 @@ impl Default for Config { | |||
| 111 | hse: None, | 116 | hse: None, |
| 112 | sys: Sysclk::HSI, | 117 | sys: Sysclk::HSI, |
| 113 | pll_src: PllSource::HSI, | 118 | pll_src: PllSource::HSI, |
| 119 | #[cfg(any(stm32f413, stm32f423, stm32f412))] | ||
| 120 | plli2s_src: Plli2sSource::HSE_HSI, | ||
| 114 | pll: None, | 121 | pll: None, |
| 115 | #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))] | 122 | #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))] |
| 116 | plli2s: None, | 123 | plli2s: None, |
| @@ -417,7 +424,7 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll | |||
| 417 | #[cfg(any(stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))] | 424 | #[cfg(any(stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))] |
| 418 | w.set_pllm(pll.prediv); | 425 | w.set_pllm(pll.prediv); |
| 419 | #[cfg(any(stm32f412, stm32f413, stm32f423))] | 426 | #[cfg(any(stm32f412, stm32f413, stm32f423))] |
| 420 | w.set_pllsrc(input.source); | 427 | w.set_plli2ssrc(Plli2sSource::HSE_HSI); |
| 421 | 428 | ||
| 422 | write_fields!(w); | 429 | write_fields!(w); |
| 423 | }), | 430 | }), |
