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authorWillaWillNot <[email protected]>2025-11-05 16:29:34 -0500
committerWillaWillNot <[email protected]>2025-11-05 16:29:34 -0500
commitf3421b0602b1acc702df6969c888ba9650010f5c (patch)
treea1aba690cac461da35a06e75729b211caee0ad31
parent765f8dd5e5e19fb4625fb190c5efa05eb2d787e3 (diff)
Pause DMA before awaiting DMA not-running at end of I2C target DMA read/write.
-rw-r--r--embassy-stm32/src/i2c/v2.rs4
1 files changed, 3 insertions, 1 deletions
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index ba9590013..57a7acee7 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -1196,7 +1196,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
1196 1196
1197 let regs = self.info.regs; 1197 let regs = self.info.regs;
1198 1198
1199 let dma_transfer = unsafe { 1199 let mut dma_transfer = unsafe {
1200 regs.cr1().modify(|w| { 1200 regs.cr1().modify(|w| {
1201 w.set_rxdmaen(true); 1201 w.set_rxdmaen(true);
1202 w.set_stopie(true); 1202 w.set_stopie(true);
@@ -1244,6 +1244,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
1244 }) 1244 })
1245 .await?; 1245 .await?;
1246 1246
1247 dma_transfer.request_pause();
1247 dma_transfer.await; 1248 dma_transfer.await;
1248 1249
1249 drop(on_drop); 1250 drop(on_drop);
@@ -1309,6 +1310,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
1309 }) 1310 })
1310 .await?; 1311 .await?;
1311 1312
1313 dma_transfer.request_pause();
1312 dma_transfer.await; 1314 dma_transfer.await;
1313 1315
1314 drop(on_drop); 1316 drop(on_drop);