Update to new api

4 files changed, 31 insertions, 43 deletions

diff --git a/embassy-stm32/src/pwr/h7.rs b/embassy-stm32/src/pwr/h7.rs
index 3d83b5e85..b298408a4 100644
--- a/embassy-stm32/src/pwr/h7.rs
+++ b/embassy-stm32/src/pwr/h7.rs
@@ -28,8 +28,6 @@ pub struct Power {
 
 impl Power {
     pub fn new(_peri: peripherals::PWR, enable_overdrive: bool) -> Self {
-        use crate::pac::rcc::vals::Apb4enrSyscfgen;
-
         // NOTE(unsafe) we have the PWR singleton
         unsafe {
             // NB. The lower bytes of CR3 can only be written once after
@@ -57,8 +55,7 @@ impl Power {
                 VoltageScale::Scale1
             } else {
                 critical_section::with(|_| {
-                    RCC.apb4enr()
-                        .modify(|w| w.set_syscfgen(Apb4enrSyscfgen::ENABLED));
+                    RCC.apb4enr().modify(|w| w.set_syscfgen(true));
 
                     SYSCFG.pwrcr().modify(|w| w.set_oden(1));
                 });
diff --git a/embassy-stm32/src/rcc/h7/mod.rs b/embassy-stm32/src/rcc/h7/mod.rs
index 57cdd5470..f15dbe075 100644
--- a/embassy-stm32/src/rcc/h7/mod.rs
+++ b/embassy-stm32/src/rcc/h7/mod.rs
@@ -101,10 +101,7 @@ impl<'d> Rcc<'d> {
     /// achieved, but the mechanism for doing so is not yet
     /// implemented here.
     pub fn freeze(mut self, pwr: &Power) -> CoreClocks {
-        use crate::pac::rcc::vals::{
-            Apb4enrSyscfgen, Ckpersel, D1ppre, D2ppre1, D3ppre, Hpre, Hsebyp, Hsidiv, Hsion, Lsion,
-            Pllsrc, Sw,
-        };
+        use crate::pac::rcc::vals::{Ckpersel, Dppre, Hpre, Hsebyp, Hsidiv, Pllsrc, Sw};
 
         let srcclk = self.config.hse.unwrap_or(HSI); // Available clocks
         let (sys_ck, sys_use_pll1_p) = self.sys_ck_setup(srcclk);
@@ -132,10 +129,10 @@ impl<'d> Rcc<'d> {
             // do so it would need to ensure all PLLxON bits are clear
             // before changing the value of HSIDIV
             let cr = RCC.cr().read();
-            assert!(cr.hsion() == Hsion::ON);
+            assert!(cr.hsion());
             assert!(cr.hsidiv() == Hsidiv::DIV1);
 
-            RCC.csr().modify(|w| w.set_lsion(Lsion::ON));
+            RCC.csr().modify(|w| w.set_lsion(true));
             while !RCC.csr().read().lsirdy() {}
         }
 
@@ -228,12 +225,12 @@ impl<'d> Rcc<'d> {
         // NOTE(unsafe) We have the RCC singleton
         unsafe {
             // Ensure CSI is on and stable
-            RCC.cr().modify(|w| w.set_csion(Hsion::ON));
+            RCC.cr().modify(|w| w.set_csion(true));
             while !RCC.cr().read().csirdy() {}
 
             // Ensure HSI48 is on and stable
-            RCC.cr().modify(|w| w.set_hsi48on(Hsion::ON));
-            while RCC.cr().read().hsi48on() == Hsion::OFF {}
+            RCC.cr().modify(|w| w.set_hsi48on(true));
+            while !RCC.cr().read().hsi48on() {}
 
             // XXX: support MCO ?
 
@@ -241,7 +238,7 @@ impl<'d> Rcc<'d> {
                 Some(hse) => {
                     // Ensure HSE is on and stable
                     RCC.cr().modify(|w| {
-                        w.set_hseon(Hsion::ON);
+                        w.set_hseon(true);
                         w.set_hsebyp(if self.config.bypass_hse {
                             Hsebyp::BYPASSED
                         } else {
@@ -261,25 +258,27 @@ impl<'d> Rcc<'d> {
             };
             RCC.pllckselr().modify(|w| w.set_pllsrc(pllsrc));
 
+            let enable_pll = |pll| {
+                RCC.cr().modify(|w| w.set_pllon(pll, true));
+                while !RCC.cr().read().pllrdy(pll) {}
+            };
+
             if pll1_p_ck.is_some() {
-                RCC.cr().modify(|w| w.set_pll1on(Hsion::ON));
-                while !RCC.cr().read().pll1rdy() {}
+                enable_pll(0);
             }
 
             if pll2_p_ck.is_some() {
-                RCC.cr().modify(|w| w.set_pll2on(Hsion::ON));
-                while !RCC.cr().read().pll2rdy() {}
+                enable_pll(1);
             }
 
             if pll3_p_ck.is_some() {
-                RCC.cr().modify(|w| w.set_pll3on(Hsion::ON));
-                while !RCC.cr().read().pll3rdy() {}
+                enable_pll(2);
             }
 
             // Core Prescaler / AHB Prescaler / APB3 Prescaler
             RCC.d1cfgr().modify(|w| {
                 w.set_d1cpre(Hpre(d1cpre_bits));
-                w.set_d1ppre(D1ppre(ppre3_bits));
+                w.set_d1ppre(Dppre(ppre3_bits));
                 w.set_hpre(hpre_bits)
             });
             // Ensure core prescaler value is valid before future lower
@@ -288,12 +287,12 @@ impl<'d> Rcc<'d> {
 
             // APB1 / APB2 Prescaler
             RCC.d2cfgr().modify(|w| {
-                w.set_d2ppre1(D2ppre1(ppre1_bits));
-                w.set_d2ppre2(D2ppre1(ppre2_bits));
+                w.set_d2ppre1(Dppre(ppre1_bits));
+                w.set_d2ppre2(Dppre(ppre2_bits));
             });
 
             // APB4 Prescaler
-            RCC.d3cfgr().modify(|w| w.set_d3ppre(D3ppre(ppre4_bits)));
+            RCC.d3cfgr().modify(|w| w.set_d3ppre(Dppre(ppre4_bits)));
 
             // Peripheral Clock (per_ck)
             RCC.d1ccipr().modify(|w| w.set_ckpersel(ckpersel));
@@ -312,8 +311,7 @@ impl<'d> Rcc<'d> {
 
             // IO compensation cell - Requires CSI clock and SYSCFG
             assert!(RCC.cr().read().csirdy());
-            RCC.apb4enr()
-                .modify(|w| w.set_syscfgen(Apb4enrSyscfgen::ENABLED));
+            RCC.apb4enr().modify(|w| w.set_syscfgen(true));
 
             // Enable the compensation cell, using back-bias voltage code
             // provide by the cell.
@@ -364,13 +362,10 @@ impl<'d> Rcc<'d> {
     /// Set `enable_dma1` to true if you do not have at least one bus master (other than the CPU)
     /// enable during WFI/WFE
     pub fn enable_debug_wfe(&mut self, _dbg: &mut peripherals::DBGMCU, enable_dma1: bool) {
-        use crate::pac::rcc::vals::Ahb1enrDma1en;
-
         // NOTE(unsafe) We have exclusive access to the RCC and DBGMCU
         unsafe {
             if enable_dma1 {
-                RCC.ahb1enr()
-                    .modify(|w| w.set_dma1en(Ahb1enrDma1en::ENABLED));
+                RCC.ahb1enr().modify(|w| w.set_dma1en(true));
             }
 
             DBGMCU.cr().modify(|w| {
diff --git a/embassy-stm32/src/rcc/h7/pll.rs b/embassy-stm32/src/rcc/h7/pll.rs
index 4c40d84d4..d3709378b 100644
--- a/embassy-stm32/src/rcc/h7/pll.rs
+++ b/embassy-stm32/src/rcc/h7/pll.rs
@@ -46,7 +46,7 @@ fn vco_output_divider_setup(output: u32, plln: usize) -> (u32, u32) {
 ///
 /// Must have exclusive access to the RCC register block
 unsafe fn vco_setup(pll_src: u32, requested_output: u32, plln: usize) -> PllConfigResults {
-    use crate::pac::rcc::vals::{Pll1rge, Pll1vcosel};
+    use crate::pac::rcc::vals::{Pllrge, Pllvcosel};
 
     let (vco_ck_target, pll_x_p) = vco_output_divider_setup(requested_output, plln);
 
@@ -60,8 +60,8 @@ unsafe fn vco_setup(pll_src: u32, requested_output: u32, plln: usize) -> PllConf
     assert!((1_000_000..=2_000_000).contains(&ref_x_ck));
 
     RCC.pllcfgr().modify(|w| {
-        w.set_pllvcosel(plln, Pll1vcosel::MEDIUMVCO);
-        w.set_pllrge(plln, Pll1rge::RANGE1);
+        w.set_pllvcosel(plln, Pllvcosel::MEDIUMVCO);
+        w.set_pllrge(plln, Pllrge::RANGE1);
     });
     PllConfigResults {
         ref_x_ck,
@@ -79,7 +79,7 @@ pub(super) unsafe fn pll_setup(
     config: &PllConfig,
     plln: usize,
 ) -> (Option<u32>, Option<u32>, Option<u32>) {
-    use crate::pac::rcc::vals::{Divp1, Divp1en, Pll1fracen};
+    use crate::pac::rcc::vals::Divp;
 
     match config.p_ck {
         Some(requested_output) => {
@@ -101,22 +101,19 @@ pub(super) unsafe fn pll_setup(
                 .modify(|w| w.set_divn1((pll_x_n - 1) as u16));
 
             // No FRACN
-            RCC.pllcfgr()
-                .modify(|w| w.set_pllfracen(plln, Pll1fracen::RESET));
+            RCC.pllcfgr().modify(|w| w.set_pllfracen(plln, false));
             let vco_ck = ref_x_ck * pll_x_n;
 
             RCC.plldivr(plln)
-                .modify(|w| w.set_divp1(Divp1((pll_x_p - 1) as u8)));
-            RCC.pllcfgr()
-                .modify(|w| w.set_divpen(plln, Divp1en::ENABLED));
+                .modify(|w| w.set_divp1(Divp((pll_x_p - 1) as u8)));
+            RCC.pllcfgr().modify(|w| w.set_divpen(plln, true));
 
             // Calulate additional output dividers
             let q_ck = match config.q_ck {
                 Some(Hertz(ck)) if ck > 0 => {
                     let div = (vco_ck + ck - 1) / ck;
                     RCC.plldivr(plln).modify(|w| w.set_divq1((div - 1) as u8));
-                    RCC.pllcfgr()
-                        .modify(|w| w.set_divqen(plln, Divp1en::ENABLED));
+                    RCC.pllcfgr().modify(|w| w.set_divqen(plln, true));
                     Some(vco_ck / div)
                 }
                 _ => None,
@@ -125,8 +122,7 @@ pub(super) unsafe fn pll_setup(
                 Some(Hertz(ck)) if ck > 0 => {
                     let div = (vco_ck + ck - 1) / ck;
                     RCC.plldivr(plln).modify(|w| w.set_divr1((div - 1) as u8));
-                    RCC.pllcfgr()
-                        .modify(|w| w.set_divren(plln, Divp1en::ENABLED));
+                    RCC.pllcfgr().modify(|w| w.set_divren(plln, true));
                     Some(vco_ck / div)
                 }
                 _ => None,
diff --git a/stm32-data b/stm32-data
-Subproject 33dfa674865b1b5f0bfb86f3217055a6a057a6f
+Subproject ba3d77f554adf361fbd4b68d256e3c631dbae52