aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDario Nieuwenhuis <[email protected]>2021-05-06 03:59:16 +0200
committerDario Nieuwenhuis <[email protected]>2021-05-06 03:59:16 +0200
commitf5f98cdeab8e457911fe369e244c60855c951f43 (patch)
tree3dd885ba2f32fe8e84d03bcb080606fd21c2f4df
parent23ca2f9174b170c6f6cfc7bab708c4ac7cc4a247 (diff)
Autogenerate features for family, peripherals and peripheral versions
Diffstat
-rw-r--r--embassy-stm32/Cargo.toml597
-rw-r--r--embassy-stm32/gen.py18
-rw-r--r--embassy-stm32/src/exti.rs1
-rw-r--r--embassy-stm32/src/gpio.rs1
-rw-r--r--embassy-stm32/src/lib.rs9
-rw-r--r--embassy-stm32/src/pac/regs.rs6120
-rw-r--r--embassy-stm32/src/rng.rs1
-rw-r--r--embassy-stm32/src/usart.rs2
8 files changed, 3386 insertions, 3363 deletions
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index a53cf9c4d..9449f636b 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -25,300 +25,311 @@ defmt-debug = [ ]
25defmt-info = [ ] 25defmt-info = [ ]
26defmt-warn = [ ] 26defmt-warn = [ ]
27defmt-error = [ ] 27defmt-error = [ ]
28
29# BEGIN GENERATED FEATURES
30stm32f401cb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
31stm32f401cc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
32stm32f401cd = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
33stm32f401ce = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
34stm32f401rb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
35stm32f401rc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
36stm32f401rd = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
37stm32f401re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
38stm32f401vb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
39stm32f401vc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
40stm32f401vd = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
41stm32f401ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
42stm32f405oe = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
43stm32f405og = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
44stm32f405rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
45stm32f405vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
46stm32f405zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
47stm32f407ie = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
48stm32f407ig = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
49stm32f407ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
50stm32f407vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
51stm32f407ze = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
52stm32f407zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
53stm32f410c8 = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
54stm32f410cb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
55stm32f410r8 = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
56stm32f410rb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
57stm32f410t8 = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
58stm32f410tb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
59stm32f411cc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
60stm32f411ce = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
61stm32f411rc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
62stm32f411re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
63stm32f411vc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
64stm32f411ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
65stm32f412ce = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
66stm32f412cg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
67stm32f412re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
68stm32f412rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
69stm32f412ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
70stm32f412vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
71stm32f412ze = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
72stm32f412zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
73stm32f413cg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
74stm32f413ch = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
75stm32f413mg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
76stm32f413mh = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
77stm32f413rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
78stm32f413rh = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
79stm32f413vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
80stm32f413vh = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
81stm32f413zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
82stm32f413zh = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
83stm32f415og = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
84stm32f415rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
85stm32f415vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
86stm32f415zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
87stm32f417ie = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
88stm32f417ig = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
89stm32f417ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
90stm32f417vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
91stm32f417ze = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
92stm32f417zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
93stm32f423ch = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
94stm32f423mh = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
95stm32f423rh = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
96stm32f423vh = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
97stm32f423zh = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
98stm32f427ag = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
99stm32f427ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
100stm32f427ig = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
101stm32f427ii = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
102stm32f427vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
103stm32f427vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
104stm32f427zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
105stm32f427zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
106stm32f429ag = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
107stm32f429ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
108stm32f429be = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
109stm32f429bg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
110stm32f429bi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
111stm32f429ie = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
112stm32f429ig = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
113stm32f429ii = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
114stm32f429ne = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
115stm32f429ng = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
116stm32f429ni = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
117stm32f429ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
118stm32f429vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
119stm32f429vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
120stm32f429ze = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
121stm32f429zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
122stm32f429zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
123stm32f437ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
124stm32f437ig = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
125stm32f437ii = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
126stm32f437vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
127stm32f437vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
128stm32f437zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
129stm32f437zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
130stm32f439ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
131stm32f439bg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
132stm32f439bi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
133stm32f439ig = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
134stm32f439ii = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
135stm32f439ng = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
136stm32f439ni = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
137stm32f439vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
138stm32f439vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
139stm32f439zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
140stm32f439zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
141stm32f446mc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
142stm32f446me = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
143stm32f446rc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
144stm32f446re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
145stm32f446vc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
146stm32f446ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
147stm32f446zc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
148stm32f446ze = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
149stm32f469ae = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
150stm32f469ag = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
151stm32f469ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
152stm32f469be = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
153stm32f469bg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
154stm32f469bi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
155stm32f469ie = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
156stm32f469ig = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
157stm32f469ii = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
158stm32f469ne = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
159stm32f469ng = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
160stm32f469ni = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
161stm32f469ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
162stm32f469vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
163stm32f469vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
164stm32f469ze = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
165stm32f469zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
166stm32f469zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
167stm32f479ag = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
168stm32f479ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
169stm32f479bg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
170stm32f479bi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
171stm32f479ig = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
172stm32f479ii = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
173stm32f479ng = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
174stm32f479ni = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
175stm32f479vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
176stm32f479vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
177stm32f479zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
178stm32f479zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
179stm32l412c8 = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
180stm32l412cb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
181stm32l412k8 = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
182stm32l412kb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
183stm32l412r8 = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
184stm32l412rb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
185stm32l412t8 = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
186stm32l412tb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
187stm32l422cb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
188stm32l422kb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
189stm32l422rb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
190stm32l422tb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
191stm32l431cb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
192stm32l431cc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
193stm32l431kb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
194stm32l431kc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
195stm32l431rb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
196stm32l431rc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
197stm32l431vc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
198stm32l432kb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
199stm32l432kc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
200stm32l433cb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
201stm32l433cc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
202stm32l433rb = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
203stm32l433rc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
204stm32l433vc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
205stm32l442kc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
206stm32l443cc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
207stm32l443rc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
208stm32l443vc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
209stm32l451cc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
210stm32l451ce = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
211stm32l451rc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
212stm32l451re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
213stm32l451vc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
214stm32l451ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
215stm32l452cc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
216stm32l452ce = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
217stm32l452rc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
218stm32l452re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
219stm32l452vc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
220stm32l452ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
221stm32l462ce = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
222stm32l462re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
223stm32l462ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
224stm32l471qe = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
225stm32l471qg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
226stm32l471re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
227stm32l471rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
228stm32l471ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
229stm32l471vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
230stm32l471ze = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
231stm32l471zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
232stm32l475rc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
233stm32l475re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
234stm32l475rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
235stm32l475vc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
236stm32l475ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
237stm32l475vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
238stm32l476je = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
239stm32l476jg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
240stm32l476me = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
241stm32l476mg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
242stm32l476qe = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
243stm32l476qg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
244stm32l476rc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
245stm32l476re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
246stm32l476rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
247stm32l476vc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
248stm32l476ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
249stm32l476vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
250stm32l476ze = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
251stm32l476zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
252stm32l485jc = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
253stm32l485je = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
254stm32l486jg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
255stm32l486qg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
256stm32l486rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
257stm32l486vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
258stm32l486zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
259stm32l496ae = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
260stm32l496ag = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
261stm32l496qe = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
262stm32l496qg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
263stm32l496re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
264stm32l496rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
265stm32l496ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
266stm32l496vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
267stm32l496wg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
268stm32l496ze = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
269stm32l496zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
270stm32l4a6ag = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
271stm32l4a6qg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
272stm32l4a6rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
273stm32l4a6vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
274stm32l4a6zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
275stm32l4p5ae = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
276stm32l4p5ag = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
277stm32l4p5ce = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
278stm32l4p5cg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
279stm32l4p5qe = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
280stm32l4p5qg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
281stm32l4p5re = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
282stm32l4p5rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
283stm32l4p5ve = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
284stm32l4p5vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
285stm32l4p5ze = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
286stm32l4p5zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
287stm32l4q5ag = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
288stm32l4q5cg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
289stm32l4q5qg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
290stm32l4q5rg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
291stm32l4q5vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
292stm32l4q5zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
293stm32l4r5ag = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
294stm32l4r5ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
295stm32l4r5qg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
296stm32l4r5qi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
297stm32l4r5vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
298stm32l4r5vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
299stm32l4r5zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
300stm32l4r5zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
301stm32l4r7ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
302stm32l4r7vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
303stm32l4r7zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
304stm32l4r9ag = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
305stm32l4r9ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
306stm32l4r9vg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
307stm32l4r9vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
308stm32l4r9zg = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
309stm32l4r9zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
310stm32l4s5ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
311stm32l4s5qi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
312stm32l4s5vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
313stm32l4s5zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
314stm32l4s7ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
315stm32l4s7vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
316stm32l4s7zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
317stm32l4s9ai = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
318stm32l4s9vi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
319stm32l4s9zi = [ "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4p", "_syscfg", "_syscfg_l4",]
320_exti = []
321_exti_v1 = []
322_gpio = []
323_gpio_v2 = []
324_rng = []
325_rng_v1 = []
326_stm32f4 = []
327_stm32l4 = []
328_stm32l4p = []
329_syscfg = []
28_syscfg_f4 = [] 330_syscfg_f4 = []
29_syscfg_l4 = [] 331_syscfg_l4 = []
332_usart = []
30_usart_v1 = [] 333_usart_v1 = []
31_rng_v1 = [] 334_usart_v2 = []
32
33# BEGIN GENERATED FEATURES
34stm32f401cb = [ "_usart_v1",]
35stm32f401cc = [ "_usart_v1",]
36stm32f401cd = [ "_usart_v1",]
37stm32f401ce = [ "_usart_v1",]
38stm32f401rb = [ "_usart_v1",]
39stm32f401rc = [ "_usart_v1",]
40stm32f401rd = [ "_usart_v1",]
41stm32f401re = [ "_usart_v1",]
42stm32f401vb = [ "_usart_v1",]
43stm32f401vc = [ "_usart_v1",]
44stm32f401vd = [ "_usart_v1",]
45stm32f401ve = [ "_usart_v1",]
46stm32f405oe = [ "_usart_v1",]
47stm32f405og = [ "_usart_v1",]
48stm32f405rg = [ "_usart_v1",]
49stm32f405vg = [ "_usart_v1",]
50stm32f405zg = [ "_usart_v1",]
51stm32f407ie = [ "_usart_v1",]
52stm32f407ig = [ "_usart_v1",]
53stm32f407ve = [ "_usart_v1",]
54stm32f407vg = [ "_usart_v1",]
55stm32f407ze = [ "_usart_v1",]
56stm32f407zg = [ "_usart_v1",]
57stm32f410c8 = [ "_usart_v1",]
58stm32f410cb = [ "_usart_v1",]
59stm32f410r8 = [ "_usart_v1",]
60stm32f410rb = [ "_usart_v1",]
61stm32f410t8 = [ "_usart_v1",]
62stm32f410tb = [ "_usart_v1",]
63stm32f411cc = [ "_usart_v1",]
64stm32f411ce = [ "_usart_v1",]
65stm32f411rc = [ "_usart_v1",]
66stm32f411re = [ "_usart_v1",]
67stm32f411vc = [ "_usart_v1",]
68stm32f411ve = [ "_usart_v1",]
69stm32f412ce = [ "_usart_v1",]
70stm32f412cg = [ "_usart_v1",]
71stm32f412re = [ "_usart_v1",]
72stm32f412rg = [ "_usart_v1",]
73stm32f412ve = [ "_usart_v1",]
74stm32f412vg = [ "_usart_v1",]
75stm32f412ze = [ "_usart_v1",]
76stm32f412zg = [ "_usart_v1",]
77stm32f413cg = [ "_usart_v1",]
78stm32f413ch = [ "_usart_v1",]
79stm32f413mg = [ "_usart_v1",]
80stm32f413mh = [ "_usart_v1",]
81stm32f413rg = [ "_usart_v1",]
82stm32f413rh = [ "_usart_v1",]
83stm32f413vg = [ "_usart_v1",]
84stm32f413vh = [ "_usart_v1",]
85stm32f413zg = [ "_usart_v1",]
86stm32f413zh = [ "_usart_v1",]
87stm32f415og = [ "_usart_v1",]
88stm32f415rg = [ "_usart_v1",]
89stm32f415vg = [ "_usart_v1",]
90stm32f415zg = [ "_usart_v1",]
91stm32f417ie = [ "_usart_v1",]
92stm32f417ig = [ "_usart_v1",]
93stm32f417ve = [ "_usart_v1",]
94stm32f417vg = [ "_usart_v1",]
95stm32f417ze = [ "_usart_v1",]
96stm32f417zg = [ "_usart_v1",]
97stm32f423ch = [ "_usart_v1",]
98stm32f423mh = [ "_usart_v1",]
99stm32f423rh = [ "_usart_v1",]
100stm32f423vh = [ "_usart_v1",]
101stm32f423zh = [ "_usart_v1",]
102stm32f427ag = [ "_usart_v1",]
103stm32f427ai = [ "_usart_v1",]
104stm32f427ig = [ "_usart_v1",]
105stm32f427ii = [ "_usart_v1",]
106stm32f427vg = [ "_usart_v1",]
107stm32f427vi = [ "_usart_v1",]
108stm32f427zg = [ "_usart_v1",]
109stm32f427zi = [ "_usart_v1",]
110stm32f429ag = [ "_usart_v1",]
111stm32f429ai = [ "_usart_v1",]
112stm32f429be = [ "_usart_v1",]
113stm32f429bg = [ "_usart_v1",]
114stm32f429bi = [ "_usart_v1",]
115stm32f429ie = [ "_usart_v1",]
116stm32f429ig = [ "_usart_v1",]
117stm32f429ii = [ "_usart_v1",]
118stm32f429ne = [ "_usart_v1",]
119stm32f429ng = [ "_usart_v1",]
120stm32f429ni = [ "_usart_v1",]
121stm32f429ve = [ "_usart_v1",]
122stm32f429vg = [ "_usart_v1",]
123stm32f429vi = [ "_usart_v1",]
124stm32f429ze = [ "_usart_v1",]
125stm32f429zg = [ "_usart_v1",]
126stm32f429zi = [ "_usart_v1",]
127stm32f437ai = [ "_usart_v1",]
128stm32f437ig = [ "_usart_v1",]
129stm32f437ii = [ "_usart_v1",]
130stm32f437vg = [ "_usart_v1",]
131stm32f437vi = [ "_usart_v1",]
132stm32f437zg = [ "_usart_v1",]
133stm32f437zi = [ "_usart_v1",]
134stm32f439ai = [ "_usart_v1",]
135stm32f439bg = [ "_usart_v1",]
136stm32f439bi = [ "_usart_v1",]
137stm32f439ig = [ "_usart_v1",]
138stm32f439ii = [ "_usart_v1",]
139stm32f439ng = [ "_usart_v1",]
140stm32f439ni = [ "_usart_v1",]
141stm32f439vg = [ "_usart_v1",]
142stm32f439vi = [ "_usart_v1",]
143stm32f439zg = [ "_usart_v1",]
144stm32f439zi = [ "_usart_v1",]
145stm32f446mc = [ "_usart_v1",]
146stm32f446me = [ "_usart_v1",]
147stm32f446rc = [ "_usart_v1",]
148stm32f446re = [ "_usart_v1",]
149stm32f446vc = [ "_usart_v1",]
150stm32f446ve = [ "_usart_v1",]
151stm32f446zc = [ "_usart_v1",]
152stm32f446ze = [ "_usart_v1",]
153stm32f469ae = [ "_usart_v1",]
154stm32f469ag = [ "_usart_v1",]
155stm32f469ai = [ "_usart_v1",]
156stm32f469be = [ "_usart_v1",]
157stm32f469bg = [ "_usart_v1",]
158stm32f469bi = [ "_usart_v1",]
159stm32f469ie = [ "_usart_v1",]
160stm32f469ig = [ "_usart_v1",]
161stm32f469ii = [ "_usart_v1",]
162stm32f469ne = [ "_usart_v1",]
163stm32f469ng = [ "_usart_v1",]
164stm32f469ni = [ "_usart_v1",]
165stm32f469ve = [ "_usart_v1",]
166stm32f469vg = [ "_usart_v1",]
167stm32f469vi = [ "_usart_v1",]
168stm32f469ze = [ "_usart_v1",]
169stm32f469zg = [ "_usart_v1",]
170stm32f469zi = [ "_usart_v1",]
171stm32f479ag = [ "_usart_v1",]
172stm32f479ai = [ "_usart_v1",]
173stm32f479bg = [ "_usart_v1",]
174stm32f479bi = [ "_usart_v1",]
175stm32f479ig = [ "_usart_v1",]
176stm32f479ii = [ "_usart_v1",]
177stm32f479ng = [ "_usart_v1",]
178stm32f479ni = [ "_usart_v1",]
179stm32f479vg = [ "_usart_v1",]
180stm32f479vi = [ "_usart_v1",]
181stm32f479zg = [ "_usart_v1",]
182stm32f479zi = [ "_usart_v1",]
183stm32l412c8 = []
184stm32l412cb = []
185stm32l412k8 = []
186stm32l412kb = []
187stm32l412r8 = []
188stm32l412rb = []
189stm32l412t8 = []
190stm32l412tb = []
191stm32l422cb = []
192stm32l422kb = []
193stm32l422rb = []
194stm32l422tb = []
195stm32l431cb = []
196stm32l431cc = []
197stm32l431kb = []
198stm32l431kc = []
199stm32l431rb = []
200stm32l431rc = []
201stm32l431vc = []
202stm32l432kb = []
203stm32l432kc = []
204stm32l433cb = []
205stm32l433cc = []
206stm32l433rb = []
207stm32l433rc = []
208stm32l433vc = []
209stm32l442kc = []
210stm32l443cc = []
211stm32l443rc = []
212stm32l443vc = []
213stm32l451cc = []
214stm32l451ce = []
215stm32l451rc = []
216stm32l451re = []
217stm32l451vc = []
218stm32l451ve = []
219stm32l452cc = []
220stm32l452ce = []
221stm32l452rc = []
222stm32l452re = []
223stm32l452vc = []
224stm32l452ve = []
225stm32l462ce = []
226stm32l462re = []
227stm32l462ve = []
228stm32l471qe = []
229stm32l471qg = []
230stm32l471re = []
231stm32l471rg = []
232stm32l471ve = []
233stm32l471vg = []
234stm32l471ze = []
235stm32l471zg = []
236stm32l475rc = []
237stm32l475re = []
238stm32l475rg = []
239stm32l475vc = []
240stm32l475ve = []
241stm32l475vg = []
242stm32l476je = []
243stm32l476jg = []
244stm32l476me = []
245stm32l476mg = []
246stm32l476qe = []
247stm32l476qg = []
248stm32l476rc = []
249stm32l476re = []
250stm32l476rg = []
251stm32l476vc = []
252stm32l476ve = []
253stm32l476vg = []
254stm32l476ze = []
255stm32l476zg = []
256stm32l485jc = []
257stm32l485je = []
258stm32l486jg = []
259stm32l486qg = []
260stm32l486rg = []
261stm32l486vg = []
262stm32l486zg = []
263stm32l496ae = []
264stm32l496ag = []
265stm32l496qe = []
266stm32l496qg = []
267stm32l496re = []
268stm32l496rg = []
269stm32l496ve = []
270stm32l496vg = []
271stm32l496wg = []
272stm32l496ze = []
273stm32l496zg = []
274stm32l4a6ag = []
275stm32l4a6qg = []
276stm32l4a6rg = []
277stm32l4a6vg = []
278stm32l4a6zg = []
279stm32l4p5ae = []
280stm32l4p5ag = []
281stm32l4p5ce = []
282stm32l4p5cg = []
283stm32l4p5qe = []
284stm32l4p5qg = []
285stm32l4p5re = []
286stm32l4p5rg = []
287stm32l4p5ve = []
288stm32l4p5vg = []
289stm32l4p5ze = []
290stm32l4p5zg = []
291stm32l4q5ag = []
292stm32l4q5cg = []
293stm32l4q5qg = []
294stm32l4q5rg = []
295stm32l4q5vg = []
296stm32l4q5zg = []
297stm32l4r5ag = []
298stm32l4r5ai = []
299stm32l4r5qg = []
300stm32l4r5qi = []
301stm32l4r5vg = []
302stm32l4r5vi = []
303stm32l4r5zg = []
304stm32l4r5zi = []
305stm32l4r7ai = []
306stm32l4r7vi = []
307stm32l4r7zi = []
308stm32l4r9ag = []
309stm32l4r9ai = []
310stm32l4r9vg = []
311stm32l4r9vi = []
312stm32l4r9zg = []
313stm32l4r9zi = []
314stm32l4s5ai = []
315stm32l4s5qi = []
316stm32l4s5vi = []
317stm32l4s5zi = []
318stm32l4s7ai = []
319stm32l4s7vi = []
320stm32l4s7zi = []
321stm32l4s9ai = []
322stm32l4s9vi = []
323stm32l4s9zi = []
324# END GENERATED FEATURES 335# END GENERATED FEATURES
diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py
index b2bc82e46..a1af866f4 100644
--- a/embassy-stm32/gen.py
+++ b/embassy-stm32/gen.py
@@ -19,7 +19,9 @@ for f in sorted(glob('stm32-data/data/chips/*.yaml')):
19 with open(f, 'r') as f: 19 with open(f, 'r') as f:
20 chip = yaml.load(f, Loader=yaml.CSafeLoader) 20 chip = yaml.load(f, Loader=yaml.CSafeLoader)
21 chip['name'] = chip['name'].lower() 21 chip['name'] = chip['name'].lower()
22 chip['features'] = [] 22 chip['features'] = set()
23 family = chip["family"].lower().replace('+', 'p')
24 chip['features'].add(f'_{family}')
23 print(chip['name']) 25 print(chip['name'])
24 chips[chip['name']] = chip 26 chips[chip['name']] = chip
25 27
@@ -107,10 +109,13 @@ for chip in chips.values():
107 raise Exception(f'Peripheral {block_mod} has two versions: {old_version} and {block_version}') 109 raise Exception(f'Peripheral {block_mod} has two versions: {old_version} and {block_version}')
108 peripheral_versions[block_mod] = block_version 110 peripheral_versions[block_mod] = block_version
109 111
112 # Set features
113 chip['features'].add(f'_{block_mod}')
114 chip['features'].add(f'_{block_mod}_{block_version}')
115
110 f.write(f'pub const {name}: {block_mod}::{block_name} = {block_mod}::{block_name}(0x{peri["address"]:x} as _);') 116 f.write(f'pub const {name}: {block_mod}::{block_name} = {block_mod}::{block_name}(0x{peri["address"]:x} as _);')
111 117
112 if peri['block'] in ('usart_v1/USART', 'usart_v1/UART'): 118 if peri['block'] in ('usart_v1/USART', 'usart_v1/UART'):
113 chip['features'].append("_usart_v1")
114 f.write(f'impl_usart!({name});') 119 f.write(f'impl_usart!({name});')
115 for pin, funcs in af.items(): 120 for pin, funcs in af.items():
116 if pin in pins: 121 if pin in pins:
@@ -196,7 +201,14 @@ for chip in chips.values():
196 201
197# ========= Update Cargo features 202# ========= Update Cargo features
198 203
199features = {name: list(set(chip['features'])) for name, chip in chips.items()} 204features = {}
205extra_features = set()
206for name, chip in chips.items():
207 features[name] = sorted(list(chip['features']))
208 for feature in chip['features']:
209 extra_features.add(feature)
210for feature in sorted(list(extra_features)):
211 features[feature] = []
200 212
201SEPARATOR_START = '# BEGIN GENERATED FEATURES\n' 213SEPARATOR_START = '# BEGIN GENERATED FEATURES\n'
202SEPARATOR_END = '# END GENERATED FEATURES\n' 214SEPARATOR_END = '# END GENERATED FEATURES\n'
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 375e77825..250f801d3 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -1,3 +1,4 @@
1#![macro_use]
1use core::convert::Infallible; 2use core::convert::Infallible;
2use core::future::Future; 3use core::future::Future;
3use core::marker::PhantomData; 4use core::marker::PhantomData;
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index 43330d9e5..85c573a87 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -1,3 +1,4 @@
1#![macro_use]
1use core::convert::Infallible; 2use core::convert::Infallible;
2use core::marker::PhantomData; 3use core::marker::PhantomData;
3use embassy::util::Unborrow; 4use embassy::util::Unborrow;
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 122998c97..557ed61af 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -11,16 +11,11 @@ pub mod fmt;
11 11
12use embassy::interrupt::{Interrupt, InterruptExt}; 12use embassy::interrupt::{Interrupt, InterruptExt};
13 13
14#[macro_use]
15pub mod exti; 14pub mod exti;
16#[macro_use]
17pub mod gpio; 15pub mod gpio;
18//pub mod rtc; 16#[cfg(feature = "_rng")]
19#[macro_use]
20pub mod usart;
21
22#[macro_use]
23pub mod rng; 17pub mod rng;
18pub mod usart;
24 19
25// This must go LAST so that it sees the `impl_foo!` macros 20// This must go LAST so that it sees the `impl_foo!` macros
26mod pac; 21mod pac;
diff --git a/embassy-stm32/src/pac/regs.rs b/embassy-stm32/src/pac/regs.rs
index a31ef04ca..e7f853c75 100644
--- a/embassy-stm32/src/pac/regs.rs
+++ b/embassy-stm32/src/pac/regs.rs
@@ -1,304 +1,229 @@
1#![no_std] 1#![no_std]
2#![doc = "Peripheral access API (generated using svd2rust v0.17.0 (507115a 2021-04-19))"] 2#![doc = "Peripheral access API (generated using svd2rust v0.17.0 (507115a 2021-04-19))"]
3pub mod gpio_v1 { 3pub mod exti_v1 {
4 use crate::generic::*; 4 use crate::generic::*;
5 #[doc = "General purpose I/O"] 5 #[doc = "External interrupt/event controller"]
6 #[derive(Copy, Clone)] 6 #[derive(Copy, Clone)]
7 pub struct Gpio(pub *mut u8); 7 pub struct Exti(pub *mut u8);
8 unsafe impl Send for Gpio {} 8 unsafe impl Send for Exti {}
9 unsafe impl Sync for Gpio {} 9 unsafe impl Sync for Exti {}
10 impl Gpio { 10 impl Exti {
11 #[doc = "Port configuration register low (GPIOn_CRL)"] 11 #[doc = "Interrupt mask register (EXTI_IMR)"]
12 pub fn cr(self, n: usize) -> Reg<regs::Cr, RW> { 12 pub fn imr(self) -> Reg<regs::Imr, RW> {
13 assert!(n < 2usize); 13 unsafe { Reg::from_ptr(self.0.add(0usize)) }
14 unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
15 } 14 }
16 #[doc = "Port input data register (GPIOn_IDR)"] 15 #[doc = "Event mask register (EXTI_EMR)"]
17 pub fn idr(self) -> Reg<regs::Idr, R> { 16 pub fn emr(self) -> Reg<regs::Emr, RW> {
17 unsafe { Reg::from_ptr(self.0.add(4usize)) }
18 }
19 #[doc = "Rising Trigger selection register (EXTI_RTSR)"]
20 pub fn rtsr(self) -> Reg<regs::Rtsr, RW> {
18 unsafe { Reg::from_ptr(self.0.add(8usize)) } 21 unsafe { Reg::from_ptr(self.0.add(8usize)) }
19 } 22 }
20 #[doc = "Port output data register (GPIOn_ODR)"] 23 #[doc = "Falling Trigger selection register (EXTI_FTSR)"]
21 pub fn odr(self) -> Reg<regs::Odr, RW> { 24 pub fn ftsr(self) -> Reg<regs::Ftsr, RW> {
22 unsafe { Reg::from_ptr(self.0.add(12usize)) } 25 unsafe { Reg::from_ptr(self.0.add(12usize)) }
23 } 26 }
24 #[doc = "Port bit set/reset register (GPIOn_BSRR)"] 27 #[doc = "Software interrupt event register (EXTI_SWIER)"]
25 pub fn bsrr(self) -> Reg<regs::Bsrr, W> { 28 pub fn swier(self) -> Reg<regs::Swier, RW> {
26 unsafe { Reg::from_ptr(self.0.add(16usize)) } 29 unsafe { Reg::from_ptr(self.0.add(16usize)) }
27 } 30 }
28 #[doc = "Port bit reset register (GPIOn_BRR)"] 31 #[doc = "Pending register (EXTI_PR)"]
29 pub fn brr(self) -> Reg<regs::Brr, W> { 32 pub fn pr(self) -> Reg<regs::Pr, RW> {
30 unsafe { Reg::from_ptr(self.0.add(20usize)) } 33 unsafe { Reg::from_ptr(self.0.add(20usize)) }
31 } 34 }
32 #[doc = "Port configuration lock register"] 35 }
33 pub fn lckr(self) -> Reg<regs::Lckr, RW> { 36 pub mod vals {
34 unsafe { Reg::from_ptr(self.0.add(24usize)) } 37 use crate::generic::*;
38 #[repr(transparent)]
39 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
40 pub struct Prw(pub u8);
41 impl Prw {
42 #[doc = "Clears pending bit"]
43 pub const CLEAR: Self = Self(0x01);
44 }
45 #[repr(transparent)]
46 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
47 pub struct Swierw(pub u8);
48 impl Swierw {
49 #[doc = "Generates an interrupt request"]
50 pub const PEND: Self = Self(0x01);
51 }
52 #[repr(transparent)]
53 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
54 pub struct Mr(pub u8);
55 impl Mr {
56 #[doc = "Interrupt request line is masked"]
57 pub const MASKED: Self = Self(0);
58 #[doc = "Interrupt request line is unmasked"]
59 pub const UNMASKED: Self = Self(0x01);
60 }
61 #[repr(transparent)]
62 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
63 pub struct Tr(pub u8);
64 impl Tr {
65 #[doc = "Falling edge trigger is disabled"]
66 pub const DISABLED: Self = Self(0);
67 #[doc = "Falling edge trigger is enabled"]
68 pub const ENABLED: Self = Self(0x01);
69 }
70 #[repr(transparent)]
71 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
72 pub struct Prr(pub u8);
73 impl Prr {
74 #[doc = "No trigger request occurred"]
75 pub const NOTPENDING: Self = Self(0);
76 #[doc = "Selected trigger request occurred"]
77 pub const PENDING: Self = Self(0x01);
35 } 78 }
36 } 79 }
37 pub mod regs { 80 pub mod regs {
38 use crate::generic::*; 81 use crate::generic::*;
39 #[doc = "Port configuration lock register"] 82 #[doc = "Rising Trigger selection register (EXTI_RTSR)"]
40 #[repr(transparent)] 83 #[repr(transparent)]
41 #[derive(Copy, Clone, Eq, PartialEq)] 84 #[derive(Copy, Clone, Eq, PartialEq)]
42 pub struct Lckr(pub u32); 85 pub struct Rtsr(pub u32);
43 impl Lckr { 86 impl Rtsr {
44 #[doc = "Port A Lock bit"] 87 #[doc = "Rising trigger event configuration of line 0"]
45 pub fn lck(&self, n: usize) -> super::vals::Lck { 88 pub fn tr(&self, n: usize) -> super::vals::Tr {
46 assert!(n < 16usize); 89 assert!(n < 23usize);
47 let offs = 0usize + n * 1usize; 90 let offs = 0usize + n * 1usize;
48 let val = (self.0 >> offs) & 0x01; 91 let val = (self.0 >> offs) & 0x01;
49 super::vals::Lck(val as u8) 92 super::vals::Tr(val as u8)
50 } 93 }
51 #[doc = "Port A Lock bit"] 94 #[doc = "Rising trigger event configuration of line 0"]
52 pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { 95 pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) {
53 assert!(n < 16usize); 96 assert!(n < 23usize);
54 let offs = 0usize + n * 1usize; 97 let offs = 0usize + n * 1usize;
55 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); 98 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
56 } 99 }
57 #[doc = "Lock key"]
58 pub const fn lckk(&self) -> super::vals::Lckk {
59 let val = (self.0 >> 16usize) & 0x01;
60 super::vals::Lckk(val as u8)
61 }
62 #[doc = "Lock key"]
63 pub fn set_lckk(&mut self, val: super::vals::Lckk) {
64 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
65 }
66 } 100 }
67 impl Default for Lckr { 101 impl Default for Rtsr {
68 fn default() -> Lckr { 102 fn default() -> Rtsr {
69 Lckr(0) 103 Rtsr(0)
70 } 104 }
71 } 105 }
72 #[doc = "Port output data register (GPIOn_ODR)"] 106 #[doc = "Falling Trigger selection register (EXTI_FTSR)"]
73 #[repr(transparent)] 107 #[repr(transparent)]
74 #[derive(Copy, Clone, Eq, PartialEq)] 108 #[derive(Copy, Clone, Eq, PartialEq)]
75 pub struct Odr(pub u32); 109 pub struct Ftsr(pub u32);
76 impl Odr { 110 impl Ftsr {
77 #[doc = "Port output data"] 111 #[doc = "Falling trigger event configuration of line 0"]
78 pub fn odr(&self, n: usize) -> super::vals::Odr { 112 pub fn tr(&self, n: usize) -> super::vals::Tr {
79 assert!(n < 16usize); 113 assert!(n < 23usize);
80 let offs = 0usize + n * 1usize; 114 let offs = 0usize + n * 1usize;
81 let val = (self.0 >> offs) & 0x01; 115 let val = (self.0 >> offs) & 0x01;
82 super::vals::Odr(val as u8) 116 super::vals::Tr(val as u8)
83 } 117 }
84 #[doc = "Port output data"] 118 #[doc = "Falling trigger event configuration of line 0"]
85 pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { 119 pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) {
86 assert!(n < 16usize); 120 assert!(n < 23usize);
87 let offs = 0usize + n * 1usize; 121 let offs = 0usize + n * 1usize;
88 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); 122 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
89 } 123 }
90 } 124 }
91 impl Default for Odr { 125 impl Default for Ftsr {
92 fn default() -> Odr { 126 fn default() -> Ftsr {
93 Odr(0) 127 Ftsr(0)
94 } 128 }
95 } 129 }
96 #[doc = "Port bit set/reset register (GPIOn_BSRR)"] 130 #[doc = "Pending register (EXTI_PR)"]
97 #[repr(transparent)] 131 #[repr(transparent)]
98 #[derive(Copy, Clone, Eq, PartialEq)] 132 #[derive(Copy, Clone, Eq, PartialEq)]
99 pub struct Bsrr(pub u32); 133 pub struct Pr(pub u32);
100 impl Bsrr { 134 impl Pr {
101 #[doc = "Set bit"] 135 #[doc = "Pending bit 0"]
102 pub fn bs(&self, n: usize) -> bool { 136 pub fn pr(&self, n: usize) -> bool {
103 assert!(n < 16usize); 137 assert!(n < 23usize);
104 let offs = 0usize + n * 1usize; 138 let offs = 0usize + n * 1usize;
105 let val = (self.0 >> offs) & 0x01; 139 let val = (self.0 >> offs) & 0x01;
106 val != 0 140 val != 0
107 } 141 }
108 #[doc = "Set bit"] 142 #[doc = "Pending bit 0"]
109 pub fn set_bs(&mut self, n: usize, val: bool) { 143 pub fn set_pr(&mut self, n: usize, val: bool) {
110 assert!(n < 16usize); 144 assert!(n < 23usize);
111 let offs = 0usize + n * 1usize; 145 let offs = 0usize + n * 1usize;
112 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); 146 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
113 } 147 }
114 #[doc = "Reset bit"]
115 pub fn br(&self, n: usize) -> bool {
116 assert!(n < 16usize);
117 let offs = 16usize + n * 1usize;
118 let val = (self.0 >> offs) & 0x01;
119 val != 0
120 }
121 #[doc = "Reset bit"]
122 pub fn set_br(&mut self, n: usize, val: bool) {
123 assert!(n < 16usize);
124 let offs = 16usize + n * 1usize;
125 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
126 }
127 } 148 }
128 impl Default for Bsrr { 149 impl Default for Pr {
129 fn default() -> Bsrr { 150 fn default() -> Pr {
130 Bsrr(0) 151 Pr(0)
131 } 152 }
132 } 153 }
133 #[doc = "Port configuration register (GPIOn_CRx)"] 154 #[doc = "Software interrupt event register (EXTI_SWIER)"]
134 #[repr(transparent)] 155 #[repr(transparent)]
135 #[derive(Copy, Clone, Eq, PartialEq)] 156 #[derive(Copy, Clone, Eq, PartialEq)]
136 pub struct Cr(pub u32); 157 pub struct Swier(pub u32);
137 impl Cr { 158 impl Swier {
138 #[doc = "Port n mode bits"] 159 #[doc = "Software Interrupt on line 0"]
139 pub fn mode(&self, n: usize) -> super::vals::Mode { 160 pub fn swier(&self, n: usize) -> bool {
140 assert!(n < 8usize); 161 assert!(n < 23usize);
141 let offs = 0usize + n * 4usize; 162 let offs = 0usize + n * 1usize;
142 let val = (self.0 >> offs) & 0x03; 163 let val = (self.0 >> offs) & 0x01;
143 super::vals::Mode(val as u8) 164 val != 0
144 }
145 #[doc = "Port n mode bits"]
146 pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) {
147 assert!(n < 8usize);
148 let offs = 0usize + n * 4usize;
149 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
150 }
151 #[doc = "Port n configuration bits"]
152 pub fn cnf(&self, n: usize) -> super::vals::Cnf {
153 assert!(n < 8usize);
154 let offs = 2usize + n * 4usize;
155 let val = (self.0 >> offs) & 0x03;
156 super::vals::Cnf(val as u8)
157 } 165 }
158 #[doc = "Port n configuration bits"] 166 #[doc = "Software Interrupt on line 0"]
159 pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) { 167 pub fn set_swier(&mut self, n: usize, val: bool) {
160 assert!(n < 8usize); 168 assert!(n < 23usize);
161 let offs = 2usize + n * 4usize; 169 let offs = 0usize + n * 1usize;
162 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); 170 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
163 } 171 }
164 } 172 }
165 impl Default for Cr { 173 impl Default for Swier {
166 fn default() -> Cr { 174 fn default() -> Swier {
167 Cr(0) 175 Swier(0)
168 } 176 }
169 } 177 }
170 #[doc = "Port bit reset register (GPIOn_BRR)"] 178 #[doc = "Interrupt mask register (EXTI_IMR)"]
171 #[repr(transparent)] 179 #[repr(transparent)]
172 #[derive(Copy, Clone, Eq, PartialEq)] 180 #[derive(Copy, Clone, Eq, PartialEq)]
173 pub struct Brr(pub u32); 181 pub struct Imr(pub u32);
174 impl Brr { 182 impl Imr {
175 #[doc = "Reset bit"] 183 #[doc = "Interrupt Mask on line 0"]
176 pub fn br(&self, n: usize) -> bool { 184 pub fn mr(&self, n: usize) -> super::vals::Mr {
177 assert!(n < 16usize); 185 assert!(n < 23usize);
178 let offs = 0usize + n * 1usize; 186 let offs = 0usize + n * 1usize;
179 let val = (self.0 >> offs) & 0x01; 187 let val = (self.0 >> offs) & 0x01;
180 val != 0 188 super::vals::Mr(val as u8)
181 } 189 }
182 #[doc = "Reset bit"] 190 #[doc = "Interrupt Mask on line 0"]
183 pub fn set_br(&mut self, n: usize, val: bool) { 191 pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) {
184 assert!(n < 16usize); 192 assert!(n < 23usize);
185 let offs = 0usize + n * 1usize; 193 let offs = 0usize + n * 1usize;
186 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); 194 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
187 } 195 }
188 } 196 }
189 impl Default for Brr { 197 impl Default for Imr {
190 fn default() -> Brr { 198 fn default() -> Imr {
191 Brr(0) 199 Imr(0)
192 } 200 }
193 } 201 }
194 #[doc = "Port input data register (GPIOn_IDR)"] 202 #[doc = "Event mask register (EXTI_EMR)"]
195 #[repr(transparent)] 203 #[repr(transparent)]
196 #[derive(Copy, Clone, Eq, PartialEq)] 204 #[derive(Copy, Clone, Eq, PartialEq)]
197 pub struct Idr(pub u32); 205 pub struct Emr(pub u32);
198 impl Idr { 206 impl Emr {
199 #[doc = "Port input data"] 207 #[doc = "Event Mask on line 0"]
200 pub fn idr(&self, n: usize) -> super::vals::Idr { 208 pub fn mr(&self, n: usize) -> super::vals::Mr {
201 assert!(n < 16usize); 209 assert!(n < 23usize);
202 let offs = 0usize + n * 1usize; 210 let offs = 0usize + n * 1usize;
203 let val = (self.0 >> offs) & 0x01; 211 let val = (self.0 >> offs) & 0x01;
204 super::vals::Idr(val as u8) 212 super::vals::Mr(val as u8)
205 } 213 }
206 #[doc = "Port input data"] 214 #[doc = "Event Mask on line 0"]
207 pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { 215 pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) {
208 assert!(n < 16usize); 216 assert!(n < 23usize);
209 let offs = 0usize + n * 1usize; 217 let offs = 0usize + n * 1usize;
210 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); 218 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
211 } 219 }
212 } 220 }
213 impl Default for Idr { 221 impl Default for Emr {
214 fn default() -> Idr { 222 fn default() -> Emr {
215 Idr(0) 223 Emr(0)
216 } 224 }
217 } 225 }
218 } 226 }
219 pub mod vals {
220 use crate::generic::*;
221 #[repr(transparent)]
222 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
223 pub struct Mode(pub u8);
224 impl Mode {
225 #[doc = "Input mode (reset state)"]
226 pub const INPUT: Self = Self(0);
227 #[doc = "Output mode 10 MHz"]
228 pub const OUTPUT: Self = Self(0x01);
229 #[doc = "Output mode 2 MHz"]
230 pub const OUTPUT2: Self = Self(0x02);
231 #[doc = "Output mode 50 MHz"]
232 pub const OUTPUT50: Self = Self(0x03);
233 }
234 #[repr(transparent)]
235 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
236 pub struct Odr(pub u8);
237 impl Odr {
238 #[doc = "Set output to logic low"]
239 pub const LOW: Self = Self(0);
240 #[doc = "Set output to logic high"]
241 pub const HIGH: Self = Self(0x01);
242 }
243 #[repr(transparent)]
244 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
245 pub struct Lckk(pub u8);
246 impl Lckk {
247 #[doc = "Port configuration lock key not active"]
248 pub const NOTACTIVE: Self = Self(0);
249 #[doc = "Port configuration lock key active"]
250 pub const ACTIVE: Self = Self(0x01);
251 }
252 #[repr(transparent)]
253 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
254 pub struct Brw(pub u8);
255 impl Brw {
256 #[doc = "No action on the corresponding ODx bit"]
257 pub const NOACTION: Self = Self(0);
258 #[doc = "Reset the ODx bit"]
259 pub const RESET: Self = Self(0x01);
260 }
261 #[repr(transparent)]
262 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
263 pub struct Idr(pub u8);
264 impl Idr {
265 #[doc = "Input is logic low"]
266 pub const LOW: Self = Self(0);
267 #[doc = "Input is logic high"]
268 pub const HIGH: Self = Self(0x01);
269 }
270 #[repr(transparent)]
271 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
272 pub struct Bsw(pub u8);
273 impl Bsw {
274 #[doc = "No action on the corresponding ODx bit"]
275 pub const NOACTION: Self = Self(0);
276 #[doc = "Sets the corresponding ODRx bit"]
277 pub const SET: Self = Self(0x01);
278 }
279 #[repr(transparent)]
280 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
281 pub struct Lck(pub u8);
282 impl Lck {
283 #[doc = "Port configuration not locked"]
284 pub const UNLOCKED: Self = Self(0);
285 #[doc = "Port configuration locked"]
286 pub const LOCKED: Self = Self(0x01);
287 }
288 #[repr(transparent)]
289 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
290 pub struct Cnf(pub u8);
291 impl Cnf {
292 #[doc = "Analog mode / Push-Pull mode"]
293 pub const PUSHPULL: Self = Self(0);
294 #[doc = "Floating input (reset state) / Open Drain-Mode"]
295 pub const OPENDRAIN: Self = Self(0x01);
296 #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"]
297 pub const ALTPUSHPULL: Self = Self(0x02);
298 #[doc = "Alternate Function Open-Drain Mode"]
299 pub const ALTOPENDRAIN: Self = Self(0x03);
300 }
301 }
302} 227}
303pub mod syscfg_f4 { 228pub mod syscfg_f4 {
304 use crate::generic::*; 229 use crate::generic::*;
@@ -375,42 +300,33 @@ pub mod syscfg_f4 {
375 Pmc(0) 300 Pmc(0)
376 } 301 }
377 } 302 }
378 #[doc = "memory remap register"] 303 #[doc = "Compensation cell control register"]
379 #[repr(transparent)] 304 #[repr(transparent)]
380 #[derive(Copy, Clone, Eq, PartialEq)] 305 #[derive(Copy, Clone, Eq, PartialEq)]
381 pub struct Memrm(pub u32); 306 pub struct Cmpcr(pub u32);
382 impl Memrm { 307 impl Cmpcr {
383 #[doc = "Memory mapping selection"] 308 #[doc = "Compensation cell power-down"]
384 pub const fn mem_mode(&self) -> u8 { 309 pub const fn cmp_pd(&self) -> bool {
385 let val = (self.0 >> 0usize) & 0x07; 310 let val = (self.0 >> 0usize) & 0x01;
386 val as u8 311 val != 0
387 } 312 }
388 #[doc = "Memory mapping selection"] 313 #[doc = "Compensation cell power-down"]
389 pub fn set_mem_mode(&mut self, val: u8) { 314 pub fn set_cmp_pd(&mut self, val: bool) {
390 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); 315 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
391 } 316 }
392 #[doc = "Flash bank mode selection"] 317 #[doc = "READY"]
393 pub const fn fb_mode(&self) -> bool { 318 pub const fn ready(&self) -> bool {
394 let val = (self.0 >> 8usize) & 0x01; 319 let val = (self.0 >> 8usize) & 0x01;
395 val != 0 320 val != 0
396 } 321 }
397 #[doc = "Flash bank mode selection"] 322 #[doc = "READY"]
398 pub fn set_fb_mode(&mut self, val: bool) { 323 pub fn set_ready(&mut self, val: bool) {
399 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); 324 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
400 } 325 }
401 #[doc = "FMC memory mapping swap"]
402 pub const fn swp_fmc(&self) -> u8 {
403 let val = (self.0 >> 10usize) & 0x03;
404 val as u8
405 }
406 #[doc = "FMC memory mapping swap"]
407 pub fn set_swp_fmc(&mut self, val: u8) {
408 self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
409 }
410 } 326 }
411 impl Default for Memrm { 327 impl Default for Cmpcr {
412 fn default() -> Memrm { 328 fn default() -> Cmpcr {
413 Memrm(0) 329 Cmpcr(0)
414 } 330 }
415 } 331 }
416 #[doc = "external interrupt configuration register"] 332 #[doc = "external interrupt configuration register"]
@@ -437,33 +353,42 @@ pub mod syscfg_f4 {
437 Exticr(0) 353 Exticr(0)
438 } 354 }
439 } 355 }
440 #[doc = "Compensation cell control register"] 356 #[doc = "memory remap register"]
441 #[repr(transparent)] 357 #[repr(transparent)]
442 #[derive(Copy, Clone, Eq, PartialEq)] 358 #[derive(Copy, Clone, Eq, PartialEq)]
443 pub struct Cmpcr(pub u32); 359 pub struct Memrm(pub u32);
444 impl Cmpcr { 360 impl Memrm {
445 #[doc = "Compensation cell power-down"] 361 #[doc = "Memory mapping selection"]
446 pub const fn cmp_pd(&self) -> bool { 362 pub const fn mem_mode(&self) -> u8 {
447 let val = (self.0 >> 0usize) & 0x01; 363 let val = (self.0 >> 0usize) & 0x07;
448 val != 0 364 val as u8
449 } 365 }
450 #[doc = "Compensation cell power-down"] 366 #[doc = "Memory mapping selection"]
451 pub fn set_cmp_pd(&mut self, val: bool) { 367 pub fn set_mem_mode(&mut self, val: u8) {
452 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 368 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
453 } 369 }
454 #[doc = "READY"] 370 #[doc = "Flash bank mode selection"]
455 pub const fn ready(&self) -> bool { 371 pub const fn fb_mode(&self) -> bool {
456 let val = (self.0 >> 8usize) & 0x01; 372 let val = (self.0 >> 8usize) & 0x01;
457 val != 0 373 val != 0
458 } 374 }
459 #[doc = "READY"] 375 #[doc = "Flash bank mode selection"]
460 pub fn set_ready(&mut self, val: bool) { 376 pub fn set_fb_mode(&mut self, val: bool) {
461 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); 377 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
462 } 378 }
379 #[doc = "FMC memory mapping swap"]
380 pub const fn swp_fmc(&self) -> u8 {
381 let val = (self.0 >> 10usize) & 0x03;
382 val as u8
383 }
384 #[doc = "FMC memory mapping swap"]
385 pub fn set_swp_fmc(&mut self, val: u8) {
386 self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
387 }
463 } 388 }
464 impl Default for Cmpcr { 389 impl Default for Memrm {
465 fn default() -> Cmpcr { 390 fn default() -> Memrm {
466 Cmpcr(0) 391 Memrm(0)
467 } 392 }
468 } 393 }
469 } 394 }
@@ -588,15 +513,6 @@ pub mod gpio_v2 {
588 use crate::generic::*; 513 use crate::generic::*;
589 #[repr(transparent)] 514 #[repr(transparent)]
590 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 515 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
591 pub struct Lck(pub u8);
592 impl Lck {
593 #[doc = "Port configuration not locked"]
594 pub const UNLOCKED: Self = Self(0);
595 #[doc = "Port configuration locked"]
596 pub const LOCKED: Self = Self(0x01);
597 }
598 #[repr(transparent)]
599 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
600 pub struct Ot(pub u8); 516 pub struct Ot(pub u8);
601 impl Ot { 517 impl Ot {
602 #[doc = "Output push-pull (reset state)"] 518 #[doc = "Output push-pull (reset state)"]
@@ -606,6 +522,13 @@ pub mod gpio_v2 {
606 } 522 }
607 #[repr(transparent)] 523 #[repr(transparent)]
608 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 524 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
525 pub struct Brw(pub u8);
526 impl Brw {
527 #[doc = "Resets the corresponding ODRx bit"]
528 pub const RESET: Self = Self(0x01);
529 }
530 #[repr(transparent)]
531 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
609 pub struct Pupdr(pub u8); 532 pub struct Pupdr(pub u8);
610 impl Pupdr { 533 impl Pupdr {
611 #[doc = "No pull-up, pull-down"] 534 #[doc = "No pull-up, pull-down"]
@@ -630,6 +553,13 @@ pub mod gpio_v2 {
630 } 553 }
631 #[repr(transparent)] 554 #[repr(transparent)]
632 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 555 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
556 pub struct Bsw(pub u8);
557 impl Bsw {
558 #[doc = "Sets the corresponding ODRx bit"]
559 pub const SET: Self = Self(0x01);
560 }
561 #[repr(transparent)]
562 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
633 pub struct Odr(pub u8); 563 pub struct Odr(pub u8);
634 impl Odr { 564 impl Odr {
635 #[doc = "Set output to logic low"] 565 #[doc = "Set output to logic low"]
@@ -639,6 +569,37 @@ pub mod gpio_v2 {
639 } 569 }
640 #[repr(transparent)] 570 #[repr(transparent)]
641 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 571 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
572 pub struct Idr(pub u8);
573 impl Idr {
574 #[doc = "Input is logic low"]
575 pub const LOW: Self = Self(0);
576 #[doc = "Input is logic high"]
577 pub const HIGH: Self = Self(0x01);
578 }
579 #[repr(transparent)]
580 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
581 pub struct Lckk(pub u8);
582 impl Lckk {
583 #[doc = "Port configuration lock key not active"]
584 pub const NOTACTIVE: Self = Self(0);
585 #[doc = "Port configuration lock key active"]
586 pub const ACTIVE: Self = Self(0x01);
587 }
588 #[repr(transparent)]
589 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
590 pub struct Ospeedr(pub u8);
591 impl Ospeedr {
592 #[doc = "Low speed"]
593 pub const LOWSPEED: Self = Self(0);
594 #[doc = "Medium speed"]
595 pub const MEDIUMSPEED: Self = Self(0x01);
596 #[doc = "High speed"]
597 pub const HIGHSPEED: Self = Self(0x02);
598 #[doc = "Very high speed"]
599 pub const VERYHIGHSPEED: Self = Self(0x03);
600 }
601 #[repr(transparent)]
602 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
642 pub struct Afr(pub u8); 603 pub struct Afr(pub u8);
643 impl Afr { 604 impl Afr {
644 #[doc = "AF0"] 605 #[doc = "AF0"]
@@ -676,122 +637,38 @@ pub mod gpio_v2 {
676 } 637 }
677 #[repr(transparent)] 638 #[repr(transparent)]
678 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 639 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
679 pub struct Lckk(pub u8); 640 pub struct Lck(pub u8);
680 impl Lckk { 641 impl Lck {
681 #[doc = "Port configuration lock key not active"] 642 #[doc = "Port configuration not locked"]
682 pub const NOTACTIVE: Self = Self(0); 643 pub const UNLOCKED: Self = Self(0);
683 #[doc = "Port configuration lock key active"] 644 #[doc = "Port configuration locked"]
684 pub const ACTIVE: Self = Self(0x01); 645 pub const LOCKED: Self = Self(0x01);
685 }
686 #[repr(transparent)]
687 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
688 pub struct Brw(pub u8);
689 impl Brw {
690 #[doc = "Resets the corresponding ODRx bit"]
691 pub const RESET: Self = Self(0x01);
692 }
693 #[repr(transparent)]
694 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
695 pub struct Idr(pub u8);
696 impl Idr {
697 #[doc = "Input is logic low"]
698 pub const LOW: Self = Self(0);
699 #[doc = "Input is logic high"]
700 pub const HIGH: Self = Self(0x01);
701 }
702 #[repr(transparent)]
703 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
704 pub struct Ospeedr(pub u8);
705 impl Ospeedr {
706 #[doc = "Low speed"]
707 pub const LOWSPEED: Self = Self(0);
708 #[doc = "Medium speed"]
709 pub const MEDIUMSPEED: Self = Self(0x01);
710 #[doc = "High speed"]
711 pub const HIGHSPEED: Self = Self(0x02);
712 #[doc = "Very high speed"]
713 pub const VERYHIGHSPEED: Self = Self(0x03);
714 }
715 #[repr(transparent)]
716 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
717 pub struct Bsw(pub u8);
718 impl Bsw {
719 #[doc = "Sets the corresponding ODRx bit"]
720 pub const SET: Self = Self(0x01);
721 } 646 }
722 } 647 }
723 pub mod regs { 648 pub mod regs {
724 use crate::generic::*; 649 use crate::generic::*;
725 #[doc = "GPIO port mode register"] 650 #[doc = "GPIO port output data register"]
726 #[repr(transparent)]
727 #[derive(Copy, Clone, Eq, PartialEq)]
728 pub struct Moder(pub u32);
729 impl Moder {
730 #[doc = "Port x configuration bits (y = 0..15)"]
731 pub fn moder(&self, n: usize) -> super::vals::Moder {
732 assert!(n < 16usize);
733 let offs = 0usize + n * 2usize;
734 let val = (self.0 >> offs) & 0x03;
735 super::vals::Moder(val as u8)
736 }
737 #[doc = "Port x configuration bits (y = 0..15)"]
738 pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) {
739 assert!(n < 16usize);
740 let offs = 0usize + n * 2usize;
741 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
742 }
743 }
744 impl Default for Moder {
745 fn default() -> Moder {
746 Moder(0)
747 }
748 }
749 #[doc = "GPIO port output type register"]
750 #[repr(transparent)] 651 #[repr(transparent)]
751 #[derive(Copy, Clone, Eq, PartialEq)] 652 #[derive(Copy, Clone, Eq, PartialEq)]
752 pub struct Otyper(pub u32); 653 pub struct Odr(pub u32);
753 impl Otyper { 654 impl Odr {
754 #[doc = "Port x configuration bits (y = 0..15)"] 655 #[doc = "Port output data (y = 0..15)"]
755 pub fn ot(&self, n: usize) -> super::vals::Ot { 656 pub fn odr(&self, n: usize) -> super::vals::Odr {
756 assert!(n < 16usize); 657 assert!(n < 16usize);
757 let offs = 0usize + n * 1usize; 658 let offs = 0usize + n * 1usize;
758 let val = (self.0 >> offs) & 0x01; 659 let val = (self.0 >> offs) & 0x01;
759 super::vals::Ot(val as u8) 660 super::vals::Odr(val as u8)
760 } 661 }
761 #[doc = "Port x configuration bits (y = 0..15)"] 662 #[doc = "Port output data (y = 0..15)"]
762 pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) { 663 pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) {
763 assert!(n < 16usize); 664 assert!(n < 16usize);
764 let offs = 0usize + n * 1usize; 665 let offs = 0usize + n * 1usize;
765 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); 666 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
766 } 667 }
767 } 668 }
768 impl Default for Otyper { 669 impl Default for Odr {
769 fn default() -> Otyper { 670 fn default() -> Odr {
770 Otyper(0) 671 Odr(0)
771 }
772 }
773 #[doc = "GPIO port output speed register"]
774 #[repr(transparent)]
775 #[derive(Copy, Clone, Eq, PartialEq)]
776 pub struct Ospeedr(pub u32);
777 impl Ospeedr {
778 #[doc = "Port x configuration bits (y = 0..15)"]
779 pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr {
780 assert!(n < 16usize);
781 let offs = 0usize + n * 2usize;
782 let val = (self.0 >> offs) & 0x03;
783 super::vals::Ospeedr(val as u8)
784 }
785 #[doc = "Port x configuration bits (y = 0..15)"]
786 pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) {
787 assert!(n < 16usize);
788 let offs = 0usize + n * 2usize;
789 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
790 }
791 }
792 impl Default for Ospeedr {
793 fn default() -> Ospeedr {
794 Ospeedr(0)
795 } 672 }
796 } 673 }
797 #[doc = "GPIO port bit set/reset register"] 674 #[doc = "GPIO port bit set/reset register"]
@@ -831,63 +708,6 @@ pub mod gpio_v2 {
831 Bsrr(0) 708 Bsrr(0)
832 } 709 }
833 } 710 }
834 #[doc = "GPIO alternate function register"]
835 #[repr(transparent)]
836 #[derive(Copy, Clone, Eq, PartialEq)]
837 pub struct Afr(pub u32);
838 impl Afr {
839 #[doc = "Alternate function selection for port x bit y (y = 0..15)"]
840 pub fn afr(&self, n: usize) -> super::vals::Afr {
841 assert!(n < 8usize);
842 let offs = 0usize + n * 4usize;
843 let val = (self.0 >> offs) & 0x0f;
844 super::vals::Afr(val as u8)
845 }
846 #[doc = "Alternate function selection for port x bit y (y = 0..15)"]
847 pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) {
848 assert!(n < 8usize);
849 let offs = 0usize + n * 4usize;
850 self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
851 }
852 }
853 impl Default for Afr {
854 fn default() -> Afr {
855 Afr(0)
856 }
857 }
858 #[doc = "GPIO port configuration lock register"]
859 #[repr(transparent)]
860 #[derive(Copy, Clone, Eq, PartialEq)]
861 pub struct Lckr(pub u32);
862 impl Lckr {
863 #[doc = "Port x lock bit y (y= 0..15)"]
864 pub fn lck(&self, n: usize) -> super::vals::Lck {
865 assert!(n < 16usize);
866 let offs = 0usize + n * 1usize;
867 let val = (self.0 >> offs) & 0x01;
868 super::vals::Lck(val as u8)
869 }
870 #[doc = "Port x lock bit y (y= 0..15)"]
871 pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) {
872 assert!(n < 16usize);
873 let offs = 0usize + n * 1usize;
874 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
875 }
876 #[doc = "Port x lock bit y (y= 0..15)"]
877 pub const fn lckk(&self) -> super::vals::Lckk {
878 let val = (self.0 >> 16usize) & 0x01;
879 super::vals::Lckk(val as u8)
880 }
881 #[doc = "Port x lock bit y (y= 0..15)"]
882 pub fn set_lckk(&mut self, val: super::vals::Lckk) {
883 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
884 }
885 }
886 impl Default for Lckr {
887 fn default() -> Lckr {
888 Lckr(0)
889 }
890 }
891 #[doc = "GPIO port input data register"] 711 #[doc = "GPIO port input data register"]
892 #[repr(transparent)] 712 #[repr(transparent)]
893 #[derive(Copy, Clone, Eq, PartialEq)] 713 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -912,6 +732,30 @@ pub mod gpio_v2 {
912 Idr(0) 732 Idr(0)
913 } 733 }
914 } 734 }
735 #[doc = "GPIO port mode register"]
736 #[repr(transparent)]
737 #[derive(Copy, Clone, Eq, PartialEq)]
738 pub struct Moder(pub u32);
739 impl Moder {
740 #[doc = "Port x configuration bits (y = 0..15)"]
741 pub fn moder(&self, n: usize) -> super::vals::Moder {
742 assert!(n < 16usize);
743 let offs = 0usize + n * 2usize;
744 let val = (self.0 >> offs) & 0x03;
745 super::vals::Moder(val as u8)
746 }
747 #[doc = "Port x configuration bits (y = 0..15)"]
748 pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) {
749 assert!(n < 16usize);
750 let offs = 0usize + n * 2usize;
751 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
752 }
753 }
754 impl Default for Moder {
755 fn default() -> Moder {
756 Moder(0)
757 }
758 }
915 #[doc = "GPIO port pull-up/pull-down register"] 759 #[doc = "GPIO port pull-up/pull-down register"]
916 #[repr(transparent)] 760 #[repr(transparent)]
917 #[derive(Copy, Clone, Eq, PartialEq)] 761 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -936,34 +780,154 @@ pub mod gpio_v2 {
936 Pupdr(0) 780 Pupdr(0)
937 } 781 }
938 } 782 }
939 #[doc = "GPIO port output data register"] 783 #[doc = "GPIO alternate function register"]
940 #[repr(transparent)] 784 #[repr(transparent)]
941 #[derive(Copy, Clone, Eq, PartialEq)] 785 #[derive(Copy, Clone, Eq, PartialEq)]
942 pub struct Odr(pub u32); 786 pub struct Afr(pub u32);
943 impl Odr { 787 impl Afr {
944 #[doc = "Port output data (y = 0..15)"] 788 #[doc = "Alternate function selection for port x bit y (y = 0..15)"]
945 pub fn odr(&self, n: usize) -> super::vals::Odr { 789 pub fn afr(&self, n: usize) -> super::vals::Afr {
790 assert!(n < 8usize);
791 let offs = 0usize + n * 4usize;
792 let val = (self.0 >> offs) & 0x0f;
793 super::vals::Afr(val as u8)
794 }
795 #[doc = "Alternate function selection for port x bit y (y = 0..15)"]
796 pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) {
797 assert!(n < 8usize);
798 let offs = 0usize + n * 4usize;
799 self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
800 }
801 }
802 impl Default for Afr {
803 fn default() -> Afr {
804 Afr(0)
805 }
806 }
807 #[doc = "GPIO port output speed register"]
808 #[repr(transparent)]
809 #[derive(Copy, Clone, Eq, PartialEq)]
810 pub struct Ospeedr(pub u32);
811 impl Ospeedr {
812 #[doc = "Port x configuration bits (y = 0..15)"]
813 pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr {
814 assert!(n < 16usize);
815 let offs = 0usize + n * 2usize;
816 let val = (self.0 >> offs) & 0x03;
817 super::vals::Ospeedr(val as u8)
818 }
819 #[doc = "Port x configuration bits (y = 0..15)"]
820 pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) {
821 assert!(n < 16usize);
822 let offs = 0usize + n * 2usize;
823 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
824 }
825 }
826 impl Default for Ospeedr {
827 fn default() -> Ospeedr {
828 Ospeedr(0)
829 }
830 }
831 #[doc = "GPIO port output type register"]
832 #[repr(transparent)]
833 #[derive(Copy, Clone, Eq, PartialEq)]
834 pub struct Otyper(pub u32);
835 impl Otyper {
836 #[doc = "Port x configuration bits (y = 0..15)"]
837 pub fn ot(&self, n: usize) -> super::vals::Ot {
946 assert!(n < 16usize); 838 assert!(n < 16usize);
947 let offs = 0usize + n * 1usize; 839 let offs = 0usize + n * 1usize;
948 let val = (self.0 >> offs) & 0x01; 840 let val = (self.0 >> offs) & 0x01;
949 super::vals::Odr(val as u8) 841 super::vals::Ot(val as u8)
950 } 842 }
951 #[doc = "Port output data (y = 0..15)"] 843 #[doc = "Port x configuration bits (y = 0..15)"]
952 pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { 844 pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) {
953 assert!(n < 16usize); 845 assert!(n < 16usize);
954 let offs = 0usize + n * 1usize; 846 let offs = 0usize + n * 1usize;
955 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); 847 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
956 } 848 }
957 } 849 }
958 impl Default for Odr { 850 impl Default for Otyper {
959 fn default() -> Odr { 851 fn default() -> Otyper {
960 Odr(0) 852 Otyper(0)
853 }
854 }
855 #[doc = "GPIO port configuration lock register"]
856 #[repr(transparent)]
857 #[derive(Copy, Clone, Eq, PartialEq)]
858 pub struct Lckr(pub u32);
859 impl Lckr {
860 #[doc = "Port x lock bit y (y= 0..15)"]
861 pub fn lck(&self, n: usize) -> super::vals::Lck {
862 assert!(n < 16usize);
863 let offs = 0usize + n * 1usize;
864 let val = (self.0 >> offs) & 0x01;
865 super::vals::Lck(val as u8)
866 }
867 #[doc = "Port x lock bit y (y= 0..15)"]
868 pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) {
869 assert!(n < 16usize);
870 let offs = 0usize + n * 1usize;
871 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
872 }
873 #[doc = "Port x lock bit y (y= 0..15)"]
874 pub const fn lckk(&self) -> super::vals::Lckk {
875 let val = (self.0 >> 16usize) & 0x01;
876 super::vals::Lckk(val as u8)
877 }
878 #[doc = "Port x lock bit y (y= 0..15)"]
879 pub fn set_lckk(&mut self, val: super::vals::Lckk) {
880 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
881 }
882 }
883 impl Default for Lckr {
884 fn default() -> Lckr {
885 Lckr(0)
961 } 886 }
962 } 887 }
963 } 888 }
964} 889}
965pub mod timer_v1 { 890pub mod timer_v1 {
966 use crate::generic::*; 891 use crate::generic::*;
892 #[doc = "Basic timer"]
893 #[derive(Copy, Clone)]
894 pub struct TimBasic(pub *mut u8);
895 unsafe impl Send for TimBasic {}
896 unsafe impl Sync for TimBasic {}
897 impl TimBasic {
898 #[doc = "control register 1"]
899 pub fn cr1(self) -> Reg<regs::Cr1Basic, RW> {
900 unsafe { Reg::from_ptr(self.0.add(0usize)) }
901 }
902 #[doc = "control register 2"]
903 pub fn cr2(self) -> Reg<regs::Cr2Basic, RW> {
904 unsafe { Reg::from_ptr(self.0.add(4usize)) }
905 }
906 #[doc = "DMA/Interrupt enable register"]
907 pub fn dier(self) -> Reg<regs::DierBasic, RW> {
908 unsafe { Reg::from_ptr(self.0.add(12usize)) }
909 }
910 #[doc = "status register"]
911 pub fn sr(self) -> Reg<regs::SrBasic, RW> {
912 unsafe { Reg::from_ptr(self.0.add(16usize)) }
913 }
914 #[doc = "event generation register"]
915 pub fn egr(self) -> Reg<regs::EgrBasic, W> {
916 unsafe { Reg::from_ptr(self.0.add(20usize)) }
917 }
918 #[doc = "counter"]
919 pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
920 unsafe { Reg::from_ptr(self.0.add(36usize)) }
921 }
922 #[doc = "prescaler"]
923 pub fn psc(self) -> Reg<regs::Psc, RW> {
924 unsafe { Reg::from_ptr(self.0.add(40usize)) }
925 }
926 #[doc = "auto-reload register"]
927 pub fn arr(self) -> Reg<regs::Arr16, RW> {
928 unsafe { Reg::from_ptr(self.0.add(44usize)) }
929 }
930 }
967 #[doc = "General purpose 32-bit timer"] 931 #[doc = "General purpose 32-bit timer"]
968 #[derive(Copy, Clone)] 932 #[derive(Copy, Clone)]
969 pub struct TimGp32(pub *mut u8); 933 pub struct TimGp32(pub *mut u8);
@@ -1034,45 +998,6 @@ pub mod timer_v1 {
1034 unsafe { Reg::from_ptr(self.0.add(76usize)) } 998 unsafe { Reg::from_ptr(self.0.add(76usize)) }
1035 } 999 }
1036 } 1000 }
1037 #[doc = "Basic timer"]
1038 #[derive(Copy, Clone)]
1039 pub struct TimBasic(pub *mut u8);
1040 unsafe impl Send for TimBasic {}
1041 unsafe impl Sync for TimBasic {}
1042 impl TimBasic {
1043 #[doc = "control register 1"]
1044 pub fn cr1(self) -> Reg<regs::Cr1Basic, RW> {
1045 unsafe { Reg::from_ptr(self.0.add(0usize)) }
1046 }
1047 #[doc = "control register 2"]
1048 pub fn cr2(self) -> Reg<regs::Cr2Basic, RW> {
1049 unsafe { Reg::from_ptr(self.0.add(4usize)) }
1050 }
1051 #[doc = "DMA/Interrupt enable register"]
1052 pub fn dier(self) -> Reg<regs::DierBasic, RW> {
1053 unsafe { Reg::from_ptr(self.0.add(12usize)) }
1054 }
1055 #[doc = "status register"]
1056 pub fn sr(self) -> Reg<regs::SrBasic, RW> {
1057 unsafe { Reg::from_ptr(self.0.add(16usize)) }
1058 }
1059 #[doc = "event generation register"]
1060 pub fn egr(self) -> Reg<regs::EgrBasic, W> {
1061 unsafe { Reg::from_ptr(self.0.add(20usize)) }
1062 }
1063 #[doc = "counter"]
1064 pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
1065 unsafe { Reg::from_ptr(self.0.add(36usize)) }
1066 }
1067 #[doc = "prescaler"]
1068 pub fn psc(self) -> Reg<regs::Psc, RW> {
1069 unsafe { Reg::from_ptr(self.0.add(40usize)) }
1070 }
1071 #[doc = "auto-reload register"]
1072 pub fn arr(self) -> Reg<regs::Arr16, RW> {
1073 unsafe { Reg::from_ptr(self.0.add(44usize)) }
1074 }
1075 }
1076 #[doc = "General purpose 16-bit timer"] 1001 #[doc = "General purpose 16-bit timer"]
1077 #[derive(Copy, Clone)] 1002 #[derive(Copy, Clone)]
1078 pub struct TimGp16(pub *mut u8); 1003 pub struct TimGp16(pub *mut u8);
@@ -1225,173 +1150,6 @@ pub mod timer_v1 {
1225 use crate::generic::*; 1150 use crate::generic::*;
1226 #[repr(transparent)] 1151 #[repr(transparent)]
1227 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 1152 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1228 pub struct Dir(pub u8);
1229 impl Dir {
1230 #[doc = "Counter used as upcounter"]
1231 pub const UP: Self = Self(0);
1232 #[doc = "Counter used as downcounter"]
1233 pub const DOWN: Self = Self(0x01);
1234 }
1235 #[repr(transparent)]
1236 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1237 pub struct Opm(pub u8);
1238 impl Opm {
1239 #[doc = "Counter is not stopped at update event"]
1240 pub const DISABLED: Self = Self(0);
1241 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
1242 pub const ENABLED: Self = Self(0x01);
1243 }
1244 #[repr(transparent)]
1245 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1246 pub struct Cms(pub u8);
1247 impl Cms {
1248 #[doc = "The counter counts up or down depending on the direction bit"]
1249 pub const EDGEALIGNED: Self = Self(0);
1250 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
1251 pub const CENTERALIGNED1: Self = Self(0x01);
1252 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."]
1253 pub const CENTERALIGNED2: Self = Self(0x02);
1254 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."]
1255 pub const CENTERALIGNED3: Self = Self(0x03);
1256 }
1257 #[repr(transparent)]
1258 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1259 pub struct Ts(pub u8);
1260 impl Ts {
1261 #[doc = "Internal Trigger 0 (ITR0)"]
1262 pub const ITR0: Self = Self(0);
1263 #[doc = "Internal Trigger 1 (ITR1)"]
1264 pub const ITR1: Self = Self(0x01);
1265 #[doc = "Internal Trigger 2 (ITR2)"]
1266 pub const ITR2: Self = Self(0x02);
1267 #[doc = "TI1 Edge Detector (TI1F_ED)"]
1268 pub const TI1F_ED: Self = Self(0x04);
1269 #[doc = "Filtered Timer Input 1 (TI1FP1)"]
1270 pub const TI1FP1: Self = Self(0x05);
1271 #[doc = "Filtered Timer Input 2 (TI2FP2)"]
1272 pub const TI2FP2: Self = Self(0x06);
1273 #[doc = "External Trigger input (ETRF)"]
1274 pub const ETRF: Self = Self(0x07);
1275 }
1276 #[repr(transparent)]
1277 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1278 pub struct CcmrOutputCcs(pub u8);
1279 impl CcmrOutputCcs {
1280 #[doc = "CCx channel is configured as output"]
1281 pub const OUTPUT: Self = Self(0);
1282 }
1283 #[repr(transparent)]
1284 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1285 pub struct Etps(pub u8);
1286 impl Etps {
1287 #[doc = "Prescaler OFF"]
1288 pub const DIV1: Self = Self(0);
1289 #[doc = "ETRP frequency divided by 2"]
1290 pub const DIV2: Self = Self(0x01);
1291 #[doc = "ETRP frequency divided by 4"]
1292 pub const DIV4: Self = Self(0x02);
1293 #[doc = "ETRP frequency divided by 8"]
1294 pub const DIV8: Self = Self(0x03);
1295 }
1296 #[repr(transparent)]
1297 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1298 pub struct Tis(pub u8);
1299 impl Tis {
1300 #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
1301 pub const NORMAL: Self = Self(0);
1302 #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
1303 pub const XOR: Self = Self(0x01);
1304 }
1305 #[repr(transparent)]
1306 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1307 pub struct Etp(pub u8);
1308 impl Etp {
1309 #[doc = "ETR is noninverted, active at high level or rising edge"]
1310 pub const NOTINVERTED: Self = Self(0);
1311 #[doc = "ETR is inverted, active at low level or falling edge"]
1312 pub const INVERTED: Self = Self(0x01);
1313 }
1314 #[repr(transparent)]
1315 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1316 pub struct CcmrInputCcs(pub u8);
1317 impl CcmrInputCcs {
1318 #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"]
1319 pub const TI4: Self = Self(0x01);
1320 #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"]
1321 pub const TI3: Self = Self(0x02);
1322 #[doc = "CCx channel is configured as input, ICx is mapped on TRC"]
1323 pub const TRC: Self = Self(0x03);
1324 }
1325 #[repr(transparent)]
1326 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1327 pub struct Ocpe(pub u8);
1328 impl Ocpe {
1329 #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"]
1330 pub const DISABLED: Self = Self(0);
1331 #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"]
1332 pub const ENABLED: Self = Self(0x01);
1333 }
1334 #[repr(transparent)]
1335 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1336 pub struct Mms(pub u8);
1337 impl Mms {
1338 #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
1339 pub const RESET: Self = Self(0);
1340 #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
1341 pub const ENABLE: Self = Self(0x01);
1342 #[doc = "The update event is selected as trigger output"]
1343 pub const UPDATE: Self = Self(0x02);
1344 #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
1345 pub const COMPAREPULSE: Self = Self(0x03);
1346 #[doc = "OC1REF signal is used as trigger output"]
1347 pub const COMPAREOC1: Self = Self(0x04);
1348 #[doc = "OC2REF signal is used as trigger output"]
1349 pub const COMPAREOC2: Self = Self(0x05);
1350 #[doc = "OC3REF signal is used as trigger output"]
1351 pub const COMPAREOC3: Self = Self(0x06);
1352 #[doc = "OC4REF signal is used as trigger output"]
1353 pub const COMPAREOC4: Self = Self(0x07);
1354 }
1355 #[repr(transparent)]
1356 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1357 pub struct Arpe(pub u8);
1358 impl Arpe {
1359 #[doc = "TIMx_APRR register is not buffered"]
1360 pub const DISABLED: Self = Self(0);
1361 #[doc = "TIMx_APRR register is buffered"]
1362 pub const ENABLED: Self = Self(0x01);
1363 }
1364 #[repr(transparent)]
1365 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1366 pub struct Ccds(pub u8);
1367 impl Ccds {
1368 #[doc = "CCx DMA request sent when CCx event occurs"]
1369 pub const ONCOMPARE: Self = Self(0);
1370 #[doc = "CCx DMA request sent when update event occurs"]
1371 pub const ONUPDATE: Self = Self(0x01);
1372 }
1373 #[repr(transparent)]
1374 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1375 pub struct Ckd(pub u8);
1376 impl Ckd {
1377 #[doc = "t_DTS = t_CK_INT"]
1378 pub const DIV1: Self = Self(0);
1379 #[doc = "t_DTS = 2 × t_CK_INT"]
1380 pub const DIV2: Self = Self(0x01);
1381 #[doc = "t_DTS = 4 × t_CK_INT"]
1382 pub const DIV4: Self = Self(0x02);
1383 }
1384 #[repr(transparent)]
1385 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1386 pub struct Msm(pub u8);
1387 impl Msm {
1388 #[doc = "No action"]
1389 pub const NOSYNC: Self = Self(0);
1390 #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
1391 pub const SYNC: Self = Self(0x01);
1392 }
1393 #[repr(transparent)]
1394 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1395 pub struct Icf(pub u8); 1153 pub struct Icf(pub u8);
1396 impl Icf { 1154 impl Icf {
1397 #[doc = "No filter, sampling is done at fDTS"] 1155 #[doc = "No filter, sampling is done at fDTS"]
@@ -1459,12 +1217,14 @@ pub mod timer_v1 {
1459 } 1217 }
1460 #[repr(transparent)] 1218 #[repr(transparent)]
1461 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 1219 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1462 pub struct Ossr(pub u8); 1220 pub struct CcmrInputCcs(pub u8);
1463 impl Ossr { 1221 impl CcmrInputCcs {
1464 #[doc = "When inactive, OC/OCN outputs are disabled"] 1222 #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"]
1465 pub const DISABLED: Self = Self(0); 1223 pub const TI4: Self = Self(0x01);
1466 #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"] 1224 #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"]
1467 pub const IDLELEVEL: Self = Self(0x01); 1225 pub const TI3: Self = Self(0x02);
1226 #[doc = "CCx channel is configured as input, ICx is mapped on TRC"]
1227 pub const TRC: Self = Self(0x03);
1468 } 1228 }
1469 #[repr(transparent)] 1229 #[repr(transparent)]
1470 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 1230 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -1477,6 +1237,67 @@ pub mod timer_v1 {
1477 } 1237 }
1478 #[repr(transparent)] 1238 #[repr(transparent)]
1479 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 1239 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1240 pub struct Urs(pub u8);
1241 impl Urs {
1242 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
1243 pub const ANYEVENT: Self = Self(0);
1244 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
1245 pub const COUNTERONLY: Self = Self(0x01);
1246 }
1247 #[repr(transparent)]
1248 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1249 pub struct Opm(pub u8);
1250 impl Opm {
1251 #[doc = "Counter is not stopped at update event"]
1252 pub const DISABLED: Self = Self(0);
1253 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
1254 pub const ENABLED: Self = Self(0x01);
1255 }
1256 #[repr(transparent)]
1257 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1258 pub struct Mms(pub u8);
1259 impl Mms {
1260 #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
1261 pub const RESET: Self = Self(0);
1262 #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
1263 pub const ENABLE: Self = Self(0x01);
1264 #[doc = "The update event is selected as trigger output"]
1265 pub const UPDATE: Self = Self(0x02);
1266 #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
1267 pub const COMPAREPULSE: Self = Self(0x03);
1268 #[doc = "OC1REF signal is used as trigger output"]
1269 pub const COMPAREOC1: Self = Self(0x04);
1270 #[doc = "OC2REF signal is used as trigger output"]
1271 pub const COMPAREOC2: Self = Self(0x05);
1272 #[doc = "OC3REF signal is used as trigger output"]
1273 pub const COMPAREOC3: Self = Self(0x06);
1274 #[doc = "OC4REF signal is used as trigger output"]
1275 pub const COMPAREOC4: Self = Self(0x07);
1276 }
1277 #[repr(transparent)]
1278 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1279 pub struct Arpe(pub u8);
1280 impl Arpe {
1281 #[doc = "TIMx_APRR register is not buffered"]
1282 pub const DISABLED: Self = Self(0);
1283 #[doc = "TIMx_APRR register is buffered"]
1284 pub const ENABLED: Self = Self(0x01);
1285 }
1286 #[repr(transparent)]
1287 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1288 pub struct Cms(pub u8);
1289 impl Cms {
1290 #[doc = "The counter counts up or down depending on the direction bit"]
1291 pub const EDGEALIGNED: Self = Self(0);
1292 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
1293 pub const CENTERALIGNED1: Self = Self(0x01);
1294 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."]
1295 pub const CENTERALIGNED2: Self = Self(0x02);
1296 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."]
1297 pub const CENTERALIGNED3: Self = Self(0x03);
1298 }
1299 #[repr(transparent)]
1300 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1480 pub struct Ocm(pub u8); 1301 pub struct Ocm(pub u8);
1481 impl Ocm { 1302 impl Ocm {
1482 #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] 1303 #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
@@ -1498,12 +1319,72 @@ pub mod timer_v1 {
1498 } 1319 }
1499 #[repr(transparent)] 1320 #[repr(transparent)]
1500 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 1321 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1501 pub struct Urs(pub u8); 1322 pub struct Tis(pub u8);
1502 impl Urs { 1323 impl Tis {
1503 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] 1324 #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
1504 pub const ANYEVENT: Self = Self(0); 1325 pub const NORMAL: Self = Self(0);
1505 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"] 1326 #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
1506 pub const COUNTERONLY: Self = Self(0x01); 1327 pub const XOR: Self = Self(0x01);
1328 }
1329 #[repr(transparent)]
1330 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1331 pub struct Ckd(pub u8);
1332 impl Ckd {
1333 #[doc = "t_DTS = t_CK_INT"]
1334 pub const DIV1: Self = Self(0);
1335 #[doc = "t_DTS = 2 × t_CK_INT"]
1336 pub const DIV2: Self = Self(0x01);
1337 #[doc = "t_DTS = 4 × t_CK_INT"]
1338 pub const DIV4: Self = Self(0x02);
1339 }
1340 #[repr(transparent)]
1341 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1342 pub struct Ossr(pub u8);
1343 impl Ossr {
1344 #[doc = "When inactive, OC/OCN outputs are disabled"]
1345 pub const DISABLED: Self = Self(0);
1346 #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"]
1347 pub const IDLELEVEL: Self = Self(0x01);
1348 }
1349 #[repr(transparent)]
1350 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1351 pub struct Etp(pub u8);
1352 impl Etp {
1353 #[doc = "ETR is noninverted, active at high level or rising edge"]
1354 pub const NOTINVERTED: Self = Self(0);
1355 #[doc = "ETR is inverted, active at low level or falling edge"]
1356 pub const INVERTED: Self = Self(0x01);
1357 }
1358 #[repr(transparent)]
1359 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1360 pub struct Etps(pub u8);
1361 impl Etps {
1362 #[doc = "Prescaler OFF"]
1363 pub const DIV1: Self = Self(0);
1364 #[doc = "ETRP frequency divided by 2"]
1365 pub const DIV2: Self = Self(0x01);
1366 #[doc = "ETRP frequency divided by 4"]
1367 pub const DIV4: Self = Self(0x02);
1368 #[doc = "ETRP frequency divided by 8"]
1369 pub const DIV8: Self = Self(0x03);
1370 }
1371 #[repr(transparent)]
1372 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1373 pub struct Msm(pub u8);
1374 impl Msm {
1375 #[doc = "No action"]
1376 pub const NOSYNC: Self = Self(0);
1377 #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
1378 pub const SYNC: Self = Self(0x01);
1379 }
1380 #[repr(transparent)]
1381 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1382 pub struct Ccds(pub u8);
1383 impl Ccds {
1384 #[doc = "CCx DMA request sent when CCx event occurs"]
1385 pub const ONCOMPARE: Self = Self(0);
1386 #[doc = "CCx DMA request sent when update event occurs"]
1387 pub const ONUPDATE: Self = Self(0x01);
1507 } 1388 }
1508 #[repr(transparent)] 1389 #[repr(transparent)]
1509 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 1390 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -1542,27 +1423,261 @@ pub mod timer_v1 {
1542 #[doc = "fSAMPLING=fDTS/32, N=8"] 1423 #[doc = "fSAMPLING=fDTS/32, N=8"]
1543 pub const FDTS_DIV32_N8: Self = Self(0x0f); 1424 pub const FDTS_DIV32_N8: Self = Self(0x0f);
1544 } 1425 }
1426 #[repr(transparent)]
1427 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1428 pub struct Ocpe(pub u8);
1429 impl Ocpe {
1430 #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"]
1431 pub const DISABLED: Self = Self(0);
1432 #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"]
1433 pub const ENABLED: Self = Self(0x01);
1434 }
1435 #[repr(transparent)]
1436 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1437 pub struct Dir(pub u8);
1438 impl Dir {
1439 #[doc = "Counter used as upcounter"]
1440 pub const UP: Self = Self(0);
1441 #[doc = "Counter used as downcounter"]
1442 pub const DOWN: Self = Self(0x01);
1443 }
1444 #[repr(transparent)]
1445 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1446 pub struct CcmrOutputCcs(pub u8);
1447 impl CcmrOutputCcs {
1448 #[doc = "CCx channel is configured as output"]
1449 pub const OUTPUT: Self = Self(0);
1450 }
1451 #[repr(transparent)]
1452 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1453 pub struct Ts(pub u8);
1454 impl Ts {
1455 #[doc = "Internal Trigger 0 (ITR0)"]
1456 pub const ITR0: Self = Self(0);
1457 #[doc = "Internal Trigger 1 (ITR1)"]
1458 pub const ITR1: Self = Self(0x01);
1459 #[doc = "Internal Trigger 2 (ITR2)"]
1460 pub const ITR2: Self = Self(0x02);
1461 #[doc = "TI1 Edge Detector (TI1F_ED)"]
1462 pub const TI1F_ED: Self = Self(0x04);
1463 #[doc = "Filtered Timer Input 1 (TI1FP1)"]
1464 pub const TI1FP1: Self = Self(0x05);
1465 #[doc = "Filtered Timer Input 2 (TI2FP2)"]
1466 pub const TI2FP2: Self = Self(0x06);
1467 #[doc = "External Trigger input (ETRF)"]
1468 pub const ETRF: Self = Self(0x07);
1469 }
1545 } 1470 }
1546 pub mod regs { 1471 pub mod regs {
1547 use crate::generic::*; 1472 use crate::generic::*;
1548 #[doc = "capture/compare register 1"] 1473 #[doc = "prescaler"]
1549 #[repr(transparent)] 1474 #[repr(transparent)]
1550 #[derive(Copy, Clone, Eq, PartialEq)] 1475 #[derive(Copy, Clone, Eq, PartialEq)]
1551 pub struct Ccr16(pub u32); 1476 pub struct Psc(pub u32);
1552 impl Ccr16 { 1477 impl Psc {
1553 #[doc = "Capture/Compare 1 value"] 1478 #[doc = "Prescaler value"]
1554 pub const fn ccr(&self) -> u16 { 1479 pub const fn psc(&self) -> u16 {
1555 let val = (self.0 >> 0usize) & 0xffff; 1480 let val = (self.0 >> 0usize) & 0xffff;
1556 val as u16 1481 val as u16
1557 } 1482 }
1558 #[doc = "Capture/Compare 1 value"] 1483 #[doc = "Prescaler value"]
1559 pub fn set_ccr(&mut self, val: u16) { 1484 pub fn set_psc(&mut self, val: u16) {
1560 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); 1485 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1561 } 1486 }
1562 } 1487 }
1563 impl Default for Ccr16 { 1488 impl Default for Psc {
1564 fn default() -> Ccr16 { 1489 fn default() -> Psc {
1565 Ccr16(0) 1490 Psc(0)
1491 }
1492 }
1493 #[doc = "control register 2"]
1494 #[repr(transparent)]
1495 #[derive(Copy, Clone, Eq, PartialEq)]
1496 pub struct Cr2Adv(pub u32);
1497 impl Cr2Adv {
1498 #[doc = "Capture/compare preloaded control"]
1499 pub const fn ccpc(&self) -> bool {
1500 let val = (self.0 >> 0usize) & 0x01;
1501 val != 0
1502 }
1503 #[doc = "Capture/compare preloaded control"]
1504 pub fn set_ccpc(&mut self, val: bool) {
1505 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1506 }
1507 #[doc = "Capture/compare control update selection"]
1508 pub const fn ccus(&self) -> bool {
1509 let val = (self.0 >> 2usize) & 0x01;
1510 val != 0
1511 }
1512 #[doc = "Capture/compare control update selection"]
1513 pub fn set_ccus(&mut self, val: bool) {
1514 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1515 }
1516 #[doc = "Capture/compare DMA selection"]
1517 pub const fn ccds(&self) -> super::vals::Ccds {
1518 let val = (self.0 >> 3usize) & 0x01;
1519 super::vals::Ccds(val as u8)
1520 }
1521 #[doc = "Capture/compare DMA selection"]
1522 pub fn set_ccds(&mut self, val: super::vals::Ccds) {
1523 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
1524 }
1525 #[doc = "Master mode selection"]
1526 pub const fn mms(&self) -> super::vals::Mms {
1527 let val = (self.0 >> 4usize) & 0x07;
1528 super::vals::Mms(val as u8)
1529 }
1530 #[doc = "Master mode selection"]
1531 pub fn set_mms(&mut self, val: super::vals::Mms) {
1532 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
1533 }
1534 #[doc = "TI1 selection"]
1535 pub const fn ti1s(&self) -> super::vals::Tis {
1536 let val = (self.0 >> 7usize) & 0x01;
1537 super::vals::Tis(val as u8)
1538 }
1539 #[doc = "TI1 selection"]
1540 pub fn set_ti1s(&mut self, val: super::vals::Tis) {
1541 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
1542 }
1543 #[doc = "Output Idle state 1"]
1544 pub fn ois(&self, n: usize) -> bool {
1545 assert!(n < 4usize);
1546 let offs = 8usize + n * 2usize;
1547 let val = (self.0 >> offs) & 0x01;
1548 val != 0
1549 }
1550 #[doc = "Output Idle state 1"]
1551 pub fn set_ois(&mut self, n: usize, val: bool) {
1552 assert!(n < 4usize);
1553 let offs = 8usize + n * 2usize;
1554 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1555 }
1556 #[doc = "Output Idle state 1"]
1557 pub const fn ois1n(&self) -> bool {
1558 let val = (self.0 >> 9usize) & 0x01;
1559 val != 0
1560 }
1561 #[doc = "Output Idle state 1"]
1562 pub fn set_ois1n(&mut self, val: bool) {
1563 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1564 }
1565 #[doc = "Output Idle state 2"]
1566 pub const fn ois2n(&self) -> bool {
1567 let val = (self.0 >> 11usize) & 0x01;
1568 val != 0
1569 }
1570 #[doc = "Output Idle state 2"]
1571 pub fn set_ois2n(&mut self, val: bool) {
1572 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1573 }
1574 #[doc = "Output Idle state 3"]
1575 pub const fn ois3n(&self) -> bool {
1576 let val = (self.0 >> 13usize) & 0x01;
1577 val != 0
1578 }
1579 #[doc = "Output Idle state 3"]
1580 pub fn set_ois3n(&mut self, val: bool) {
1581 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
1582 }
1583 }
1584 impl Default for Cr2Adv {
1585 fn default() -> Cr2Adv {
1586 Cr2Adv(0)
1587 }
1588 }
1589 #[doc = "control register 2"]
1590 #[repr(transparent)]
1591 #[derive(Copy, Clone, Eq, PartialEq)]
1592 pub struct Cr2Basic(pub u32);
1593 impl Cr2Basic {
1594 #[doc = "Master mode selection"]
1595 pub const fn mms(&self) -> super::vals::Mms {
1596 let val = (self.0 >> 4usize) & 0x07;
1597 super::vals::Mms(val as u8)
1598 }
1599 #[doc = "Master mode selection"]
1600 pub fn set_mms(&mut self, val: super::vals::Mms) {
1601 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
1602 }
1603 }
1604 impl Default for Cr2Basic {
1605 fn default() -> Cr2Basic {
1606 Cr2Basic(0)
1607 }
1608 }
1609 #[doc = "slave mode control register"]
1610 #[repr(transparent)]
1611 #[derive(Copy, Clone, Eq, PartialEq)]
1612 pub struct Smcr(pub u32);
1613 impl Smcr {
1614 #[doc = "Slave mode selection"]
1615 pub const fn sms(&self) -> super::vals::Sms {
1616 let val = (self.0 >> 0usize) & 0x07;
1617 super::vals::Sms(val as u8)
1618 }
1619 #[doc = "Slave mode selection"]
1620 pub fn set_sms(&mut self, val: super::vals::Sms) {
1621 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize);
1622 }
1623 #[doc = "Trigger selection"]
1624 pub const fn ts(&self) -> super::vals::Ts {
1625 let val = (self.0 >> 4usize) & 0x07;
1626 super::vals::Ts(val as u8)
1627 }
1628 #[doc = "Trigger selection"]
1629 pub fn set_ts(&mut self, val: super::vals::Ts) {
1630 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
1631 }
1632 #[doc = "Master/Slave mode"]
1633 pub const fn msm(&self) -> super::vals::Msm {
1634 let val = (self.0 >> 7usize) & 0x01;
1635 super::vals::Msm(val as u8)
1636 }
1637 #[doc = "Master/Slave mode"]
1638 pub fn set_msm(&mut self, val: super::vals::Msm) {
1639 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
1640 }
1641 #[doc = "External trigger filter"]
1642 pub const fn etf(&self) -> super::vals::Etf {
1643 let val = (self.0 >> 8usize) & 0x0f;
1644 super::vals::Etf(val as u8)
1645 }
1646 #[doc = "External trigger filter"]
1647 pub fn set_etf(&mut self, val: super::vals::Etf) {
1648 self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize);
1649 }
1650 #[doc = "External trigger prescaler"]
1651 pub const fn etps(&self) -> super::vals::Etps {
1652 let val = (self.0 >> 12usize) & 0x03;
1653 super::vals::Etps(val as u8)
1654 }
1655 #[doc = "External trigger prescaler"]
1656 pub fn set_etps(&mut self, val: super::vals::Etps) {
1657 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
1658 }
1659 #[doc = "External clock enable"]
1660 pub const fn ece(&self) -> super::vals::Ece {
1661 let val = (self.0 >> 14usize) & 0x01;
1662 super::vals::Ece(val as u8)
1663 }
1664 #[doc = "External clock enable"]
1665 pub fn set_ece(&mut self, val: super::vals::Ece) {
1666 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
1667 }
1668 #[doc = "External trigger polarity"]
1669 pub const fn etp(&self) -> super::vals::Etp {
1670 let val = (self.0 >> 15usize) & 0x01;
1671 super::vals::Etp(val as u8)
1672 }
1673 #[doc = "External trigger polarity"]
1674 pub fn set_etp(&mut self, val: super::vals::Etp) {
1675 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
1676 }
1677 }
1678 impl Default for Smcr {
1679 fn default() -> Smcr {
1680 Smcr(0)
1566 } 1681 }
1567 } 1682 }
1568 #[doc = "capture/compare mode register 2 (output mode)"] 1683 #[doc = "capture/compare mode register 2 (output mode)"]
@@ -1641,179 +1756,6 @@ pub mod timer_v1 {
1641 CcmrOutput(0) 1756 CcmrOutput(0)
1642 } 1757 }
1643 } 1758 }
1644 #[doc = "DMA/Interrupt enable register"]
1645 #[repr(transparent)]
1646 #[derive(Copy, Clone, Eq, PartialEq)]
1647 pub struct DierBasic(pub u32);
1648 impl DierBasic {
1649 #[doc = "Update interrupt enable"]
1650 pub const fn uie(&self) -> bool {
1651 let val = (self.0 >> 0usize) & 0x01;
1652 val != 0
1653 }
1654 #[doc = "Update interrupt enable"]
1655 pub fn set_uie(&mut self, val: bool) {
1656 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1657 }
1658 #[doc = "Update DMA request enable"]
1659 pub const fn ude(&self) -> bool {
1660 let val = (self.0 >> 8usize) & 0x01;
1661 val != 0
1662 }
1663 #[doc = "Update DMA request enable"]
1664 pub fn set_ude(&mut self, val: bool) {
1665 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1666 }
1667 }
1668 impl Default for DierBasic {
1669 fn default() -> DierBasic {
1670 DierBasic(0)
1671 }
1672 }
1673 #[doc = "capture/compare register 1"]
1674 #[repr(transparent)]
1675 #[derive(Copy, Clone, Eq, PartialEq)]
1676 pub struct Ccr32(pub u32);
1677 impl Ccr32 {
1678 #[doc = "Capture/Compare 1 value"]
1679 pub const fn ccr(&self) -> u32 {
1680 let val = (self.0 >> 0usize) & 0xffff_ffff;
1681 val as u32
1682 }
1683 #[doc = "Capture/Compare 1 value"]
1684 pub fn set_ccr(&mut self, val: u32) {
1685 self.0 =
1686 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1687 }
1688 }
1689 impl Default for Ccr32 {
1690 fn default() -> Ccr32 {
1691 Ccr32(0)
1692 }
1693 }
1694 #[doc = "prescaler"]
1695 #[repr(transparent)]
1696 #[derive(Copy, Clone, Eq, PartialEq)]
1697 pub struct Psc(pub u32);
1698 impl Psc {
1699 #[doc = "Prescaler value"]
1700 pub const fn psc(&self) -> u16 {
1701 let val = (self.0 >> 0usize) & 0xffff;
1702 val as u16
1703 }
1704 #[doc = "Prescaler value"]
1705 pub fn set_psc(&mut self, val: u16) {
1706 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1707 }
1708 }
1709 impl Default for Psc {
1710 fn default() -> Psc {
1711 Psc(0)
1712 }
1713 }
1714 #[doc = "break and dead-time register"]
1715 #[repr(transparent)]
1716 #[derive(Copy, Clone, Eq, PartialEq)]
1717 pub struct Bdtr(pub u32);
1718 impl Bdtr {
1719 #[doc = "Dead-time generator setup"]
1720 pub const fn dtg(&self) -> u8 {
1721 let val = (self.0 >> 0usize) & 0xff;
1722 val as u8
1723 }
1724 #[doc = "Dead-time generator setup"]
1725 pub fn set_dtg(&mut self, val: u8) {
1726 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1727 }
1728 #[doc = "Lock configuration"]
1729 pub const fn lock(&self) -> u8 {
1730 let val = (self.0 >> 8usize) & 0x03;
1731 val as u8
1732 }
1733 #[doc = "Lock configuration"]
1734 pub fn set_lock(&mut self, val: u8) {
1735 self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
1736 }
1737 #[doc = "Off-state selection for Idle mode"]
1738 pub const fn ossi(&self) -> super::vals::Ossi {
1739 let val = (self.0 >> 10usize) & 0x01;
1740 super::vals::Ossi(val as u8)
1741 }
1742 #[doc = "Off-state selection for Idle mode"]
1743 pub fn set_ossi(&mut self, val: super::vals::Ossi) {
1744 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
1745 }
1746 #[doc = "Off-state selection for Run mode"]
1747 pub const fn ossr(&self) -> super::vals::Ossr {
1748 let val = (self.0 >> 11usize) & 0x01;
1749 super::vals::Ossr(val as u8)
1750 }
1751 #[doc = "Off-state selection for Run mode"]
1752 pub fn set_ossr(&mut self, val: super::vals::Ossr) {
1753 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
1754 }
1755 #[doc = "Break enable"]
1756 pub const fn bke(&self) -> bool {
1757 let val = (self.0 >> 12usize) & 0x01;
1758 val != 0
1759 }
1760 #[doc = "Break enable"]
1761 pub fn set_bke(&mut self, val: bool) {
1762 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1763 }
1764 #[doc = "Break polarity"]
1765 pub const fn bkp(&self) -> bool {
1766 let val = (self.0 >> 13usize) & 0x01;
1767 val != 0
1768 }
1769 #[doc = "Break polarity"]
1770 pub fn set_bkp(&mut self, val: bool) {
1771 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
1772 }
1773 #[doc = "Automatic output enable"]
1774 pub const fn aoe(&self) -> bool {
1775 let val = (self.0 >> 14usize) & 0x01;
1776 val != 0
1777 }
1778 #[doc = "Automatic output enable"]
1779 pub fn set_aoe(&mut self, val: bool) {
1780 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1781 }
1782 #[doc = "Main output enable"]
1783 pub const fn moe(&self) -> bool {
1784 let val = (self.0 >> 15usize) & 0x01;
1785 val != 0
1786 }
1787 #[doc = "Main output enable"]
1788 pub fn set_moe(&mut self, val: bool) {
1789 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1790 }
1791 }
1792 impl Default for Bdtr {
1793 fn default() -> Bdtr {
1794 Bdtr(0)
1795 }
1796 }
1797 #[doc = "status register"]
1798 #[repr(transparent)]
1799 #[derive(Copy, Clone, Eq, PartialEq)]
1800 pub struct SrBasic(pub u32);
1801 impl SrBasic {
1802 #[doc = "Update interrupt flag"]
1803 pub const fn uif(&self) -> bool {
1804 let val = (self.0 >> 0usize) & 0x01;
1805 val != 0
1806 }
1807 #[doc = "Update interrupt flag"]
1808 pub fn set_uif(&mut self, val: bool) {
1809 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1810 }
1811 }
1812 impl Default for SrBasic {
1813 fn default() -> SrBasic {
1814 SrBasic(0)
1815 }
1816 }
1817 #[doc = "status register"] 1759 #[doc = "status register"]
1818 #[repr(transparent)] 1760 #[repr(transparent)]
1819 #[derive(Copy, Clone, Eq, PartialEq)] 1761 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -1887,31 +1829,11 @@ pub mod timer_v1 {
1887 SrGp(0) 1829 SrGp(0)
1888 } 1830 }
1889 } 1831 }
1890 #[doc = "DMA address for full transfer"]
1891 #[repr(transparent)]
1892 #[derive(Copy, Clone, Eq, PartialEq)]
1893 pub struct Dmar(pub u32);
1894 impl Dmar {
1895 #[doc = "DMA register for burst accesses"]
1896 pub const fn dmab(&self) -> u16 {
1897 let val = (self.0 >> 0usize) & 0xffff;
1898 val as u16
1899 }
1900 #[doc = "DMA register for burst accesses"]
1901 pub fn set_dmab(&mut self, val: u16) {
1902 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1903 }
1904 }
1905 impl Default for Dmar {
1906 fn default() -> Dmar {
1907 Dmar(0)
1908 }
1909 }
1910 #[doc = "event generation register"] 1832 #[doc = "event generation register"]
1911 #[repr(transparent)] 1833 #[repr(transparent)]
1912 #[derive(Copy, Clone, Eq, PartialEq)] 1834 #[derive(Copy, Clone, Eq, PartialEq)]
1913 pub struct EgrAdv(pub u32); 1835 pub struct EgrGp(pub u32);
1914 impl EgrAdv { 1836 impl EgrGp {
1915 #[doc = "Update generation"] 1837 #[doc = "Update generation"]
1916 pub const fn ug(&self) -> bool { 1838 pub const fn ug(&self) -> bool {
1917 let val = (self.0 >> 0usize) & 0x01; 1839 let val = (self.0 >> 0usize) & 0x01;
@@ -1962,50 +1884,132 @@ pub mod timer_v1 {
1962 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); 1884 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1963 } 1885 }
1964 } 1886 }
1965 impl Default for EgrAdv { 1887 impl Default for EgrGp {
1966 fn default() -> EgrAdv { 1888 fn default() -> EgrGp {
1967 EgrAdv(0) 1889 EgrGp(0)
1968 } 1890 }
1969 } 1891 }
1970 #[doc = "event generation register"] 1892 #[doc = "control register 1"]
1971 #[repr(transparent)] 1893 #[repr(transparent)]
1972 #[derive(Copy, Clone, Eq, PartialEq)] 1894 #[derive(Copy, Clone, Eq, PartialEq)]
1973 pub struct EgrBasic(pub u32); 1895 pub struct Cr1Basic(pub u32);
1974 impl EgrBasic { 1896 impl Cr1Basic {
1975 #[doc = "Update generation"] 1897 #[doc = "Counter enable"]
1976 pub const fn ug(&self) -> bool { 1898 pub const fn cen(&self) -> bool {
1977 let val = (self.0 >> 0usize) & 0x01; 1899 let val = (self.0 >> 0usize) & 0x01;
1978 val != 0 1900 val != 0
1979 } 1901 }
1980 #[doc = "Update generation"] 1902 #[doc = "Counter enable"]
1981 pub fn set_ug(&mut self, val: bool) { 1903 pub fn set_cen(&mut self, val: bool) {
1982 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 1904 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1983 } 1905 }
1906 #[doc = "Update disable"]
1907 pub const fn udis(&self) -> bool {
1908 let val = (self.0 >> 1usize) & 0x01;
1909 val != 0
1910 }
1911 #[doc = "Update disable"]
1912 pub fn set_udis(&mut self, val: bool) {
1913 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1914 }
1915 #[doc = "Update request source"]
1916 pub const fn urs(&self) -> super::vals::Urs {
1917 let val = (self.0 >> 2usize) & 0x01;
1918 super::vals::Urs(val as u8)
1919 }
1920 #[doc = "Update request source"]
1921 pub fn set_urs(&mut self, val: super::vals::Urs) {
1922 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
1923 }
1924 #[doc = "One-pulse mode"]
1925 pub const fn opm(&self) -> super::vals::Opm {
1926 let val = (self.0 >> 3usize) & 0x01;
1927 super::vals::Opm(val as u8)
1928 }
1929 #[doc = "One-pulse mode"]
1930 pub fn set_opm(&mut self, val: super::vals::Opm) {
1931 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
1932 }
1933 #[doc = "Auto-reload preload enable"]
1934 pub const fn arpe(&self) -> super::vals::Arpe {
1935 let val = (self.0 >> 7usize) & 0x01;
1936 super::vals::Arpe(val as u8)
1937 }
1938 #[doc = "Auto-reload preload enable"]
1939 pub fn set_arpe(&mut self, val: super::vals::Arpe) {
1940 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
1941 }
1984 } 1942 }
1985 impl Default for EgrBasic { 1943 impl Default for Cr1Basic {
1986 fn default() -> EgrBasic { 1944 fn default() -> Cr1Basic {
1987 EgrBasic(0) 1945 Cr1Basic(0)
1988 } 1946 }
1989 } 1947 }
1990 #[doc = "counter"] 1948 #[doc = "DMA control register"]
1991 #[repr(transparent)] 1949 #[repr(transparent)]
1992 #[derive(Copy, Clone, Eq, PartialEq)] 1950 #[derive(Copy, Clone, Eq, PartialEq)]
1993 pub struct Cnt32(pub u32); 1951 pub struct Dcr(pub u32);
1994 impl Cnt32 { 1952 impl Dcr {
1995 #[doc = "counter value"] 1953 #[doc = "DMA base address"]
1996 pub const fn cnt(&self) -> u32 { 1954 pub const fn dba(&self) -> u8 {
1997 let val = (self.0 >> 0usize) & 0xffff_ffff; 1955 let val = (self.0 >> 0usize) & 0x1f;
1998 val as u32 1956 val as u8
1999 } 1957 }
2000 #[doc = "counter value"] 1958 #[doc = "DMA base address"]
2001 pub fn set_cnt(&mut self, val: u32) { 1959 pub fn set_dba(&mut self, val: u8) {
2002 self.0 = 1960 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
2003 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); 1961 }
1962 #[doc = "DMA burst length"]
1963 pub const fn dbl(&self) -> u8 {
1964 let val = (self.0 >> 8usize) & 0x1f;
1965 val as u8
1966 }
1967 #[doc = "DMA burst length"]
1968 pub fn set_dbl(&mut self, val: u8) {
1969 self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
2004 } 1970 }
2005 } 1971 }
2006 impl Default for Cnt32 { 1972 impl Default for Dcr {
2007 fn default() -> Cnt32 { 1973 fn default() -> Dcr {
2008 Cnt32(0) 1974 Dcr(0)
1975 }
1976 }
1977 #[doc = "control register 2"]
1978 #[repr(transparent)]
1979 #[derive(Copy, Clone, Eq, PartialEq)]
1980 pub struct Cr2Gp(pub u32);
1981 impl Cr2Gp {
1982 #[doc = "Capture/compare DMA selection"]
1983 pub const fn ccds(&self) -> super::vals::Ccds {
1984 let val = (self.0 >> 3usize) & 0x01;
1985 super::vals::Ccds(val as u8)
1986 }
1987 #[doc = "Capture/compare DMA selection"]
1988 pub fn set_ccds(&mut self, val: super::vals::Ccds) {
1989 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
1990 }
1991 #[doc = "Master mode selection"]
1992 pub const fn mms(&self) -> super::vals::Mms {
1993 let val = (self.0 >> 4usize) & 0x07;
1994 super::vals::Mms(val as u8)
1995 }
1996 #[doc = "Master mode selection"]
1997 pub fn set_mms(&mut self, val: super::vals::Mms) {
1998 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
1999 }
2000 #[doc = "TI1 selection"]
2001 pub const fn ti1s(&self) -> super::vals::Tis {
2002 let val = (self.0 >> 7usize) & 0x01;
2003 super::vals::Tis(val as u8)
2004 }
2005 #[doc = "TI1 selection"]
2006 pub fn set_ti1s(&mut self, val: super::vals::Tis) {
2007 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
2008 }
2009 }
2010 impl Default for Cr2Gp {
2011 fn default() -> Cr2Gp {
2012 Cr2Gp(0)
2009 } 2013 }
2010 } 2014 }
2011 #[doc = "DMA/Interrupt enable register"] 2015 #[doc = "DMA/Interrupt enable register"]
@@ -2081,6 +2085,35 @@ pub mod timer_v1 {
2081 DierGp(0) 2085 DierGp(0)
2082 } 2086 }
2083 } 2087 }
2088 #[doc = "DMA/Interrupt enable register"]
2089 #[repr(transparent)]
2090 #[derive(Copy, Clone, Eq, PartialEq)]
2091 pub struct DierBasic(pub u32);
2092 impl DierBasic {
2093 #[doc = "Update interrupt enable"]
2094 pub const fn uie(&self) -> bool {
2095 let val = (self.0 >> 0usize) & 0x01;
2096 val != 0
2097 }
2098 #[doc = "Update interrupt enable"]
2099 pub fn set_uie(&mut self, val: bool) {
2100 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2101 }
2102 #[doc = "Update DMA request enable"]
2103 pub const fn ude(&self) -> bool {
2104 let val = (self.0 >> 8usize) & 0x01;
2105 val != 0
2106 }
2107 #[doc = "Update DMA request enable"]
2108 pub fn set_ude(&mut self, val: bool) {
2109 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
2110 }
2111 }
2112 impl Default for DierBasic {
2113 fn default() -> DierBasic {
2114 DierBasic(0)
2115 }
2116 }
2084 #[doc = "control register 1"] 2117 #[doc = "control register 1"]
2085 #[repr(transparent)] 2118 #[repr(transparent)]
2086 #[derive(Copy, Clone, Eq, PartialEq)] 2119 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -2164,120 +2197,178 @@ pub mod timer_v1 {
2164 Cr1Gp(0) 2197 Cr1Gp(0)
2165 } 2198 }
2166 } 2199 }
2167 #[doc = "control register 2"] 2200 #[doc = "break and dead-time register"]
2168 #[repr(transparent)] 2201 #[repr(transparent)]
2169 #[derive(Copy, Clone, Eq, PartialEq)] 2202 #[derive(Copy, Clone, Eq, PartialEq)]
2170 pub struct Cr2Adv(pub u32); 2203 pub struct Bdtr(pub u32);
2171 impl Cr2Adv { 2204 impl Bdtr {
2172 #[doc = "Capture/compare preloaded control"] 2205 #[doc = "Dead-time generator setup"]
2173 pub const fn ccpc(&self) -> bool { 2206 pub const fn dtg(&self) -> u8 {
2174 let val = (self.0 >> 0usize) & 0x01; 2207 let val = (self.0 >> 0usize) & 0xff;
2175 val != 0 2208 val as u8
2176 } 2209 }
2177 #[doc = "Capture/compare preloaded control"] 2210 #[doc = "Dead-time generator setup"]
2178 pub fn set_ccpc(&mut self, val: bool) { 2211 pub fn set_dtg(&mut self, val: u8) {
2179 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 2212 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
2180 } 2213 }
2181 #[doc = "Capture/compare control update selection"] 2214 #[doc = "Lock configuration"]
2182 pub const fn ccus(&self) -> bool { 2215 pub const fn lock(&self) -> u8 {
2183 let val = (self.0 >> 2usize) & 0x01; 2216 let val = (self.0 >> 8usize) & 0x03;
2184 val != 0 2217 val as u8
2185 } 2218 }
2186 #[doc = "Capture/compare control update selection"] 2219 #[doc = "Lock configuration"]
2187 pub fn set_ccus(&mut self, val: bool) { 2220 pub fn set_lock(&mut self, val: u8) {
2188 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); 2221 self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
2189 } 2222 }
2190 #[doc = "Capture/compare DMA selection"] 2223 #[doc = "Off-state selection for Idle mode"]
2191 pub const fn ccds(&self) -> super::vals::Ccds { 2224 pub const fn ossi(&self) -> super::vals::Ossi {
2192 let val = (self.0 >> 3usize) & 0x01; 2225 let val = (self.0 >> 10usize) & 0x01;
2193 super::vals::Ccds(val as u8) 2226 super::vals::Ossi(val as u8)
2194 } 2227 }
2195 #[doc = "Capture/compare DMA selection"] 2228 #[doc = "Off-state selection for Idle mode"]
2196 pub fn set_ccds(&mut self, val: super::vals::Ccds) { 2229 pub fn set_ossi(&mut self, val: super::vals::Ossi) {
2197 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); 2230 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
2198 } 2231 }
2199 #[doc = "Master mode selection"] 2232 #[doc = "Off-state selection for Run mode"]
2200 pub const fn mms(&self) -> super::vals::Mms { 2233 pub const fn ossr(&self) -> super::vals::Ossr {
2201 let val = (self.0 >> 4usize) & 0x07; 2234 let val = (self.0 >> 11usize) & 0x01;
2202 super::vals::Mms(val as u8) 2235 super::vals::Ossr(val as u8)
2203 } 2236 }
2204 #[doc = "Master mode selection"] 2237 #[doc = "Off-state selection for Run mode"]
2205 pub fn set_mms(&mut self, val: super::vals::Mms) { 2238 pub fn set_ossr(&mut self, val: super::vals::Ossr) {
2206 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); 2239 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
2207 } 2240 }
2208 #[doc = "TI1 selection"] 2241 #[doc = "Break enable"]
2209 pub const fn ti1s(&self) -> super::vals::Tis { 2242 pub const fn bke(&self) -> bool {
2210 let val = (self.0 >> 7usize) & 0x01; 2243 let val = (self.0 >> 12usize) & 0x01;
2211 super::vals::Tis(val as u8) 2244 val != 0
2212 } 2245 }
2213 #[doc = "TI1 selection"] 2246 #[doc = "Break enable"]
2214 pub fn set_ti1s(&mut self, val: super::vals::Tis) { 2247 pub fn set_bke(&mut self, val: bool) {
2215 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); 2248 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2216 } 2249 }
2217 #[doc = "Output Idle state 1"] 2250 #[doc = "Break polarity"]
2218 pub fn ois(&self, n: usize) -> bool { 2251 pub const fn bkp(&self) -> bool {
2219 assert!(n < 4usize); 2252 let val = (self.0 >> 13usize) & 0x01;
2220 let offs = 8usize + n * 2usize;
2221 let val = (self.0 >> offs) & 0x01;
2222 val != 0 2253 val != 0
2223 } 2254 }
2224 #[doc = "Output Idle state 1"] 2255 #[doc = "Break polarity"]
2225 pub fn set_ois(&mut self, n: usize, val: bool) { 2256 pub fn set_bkp(&mut self, val: bool) {
2226 assert!(n < 4usize); 2257 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
2227 let offs = 8usize + n * 2usize;
2228 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2229 } 2258 }
2230 #[doc = "Output Idle state 1"] 2259 #[doc = "Automatic output enable"]
2231 pub const fn ois1n(&self) -> bool { 2260 pub const fn aoe(&self) -> bool {
2232 let val = (self.0 >> 9usize) & 0x01; 2261 let val = (self.0 >> 14usize) & 0x01;
2233 val != 0 2262 val != 0
2234 } 2263 }
2235 #[doc = "Output Idle state 1"] 2264 #[doc = "Automatic output enable"]
2236 pub fn set_ois1n(&mut self, val: bool) { 2265 pub fn set_aoe(&mut self, val: bool) {
2237 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); 2266 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
2238 } 2267 }
2239 #[doc = "Output Idle state 2"] 2268 #[doc = "Main output enable"]
2240 pub const fn ois2n(&self) -> bool { 2269 pub const fn moe(&self) -> bool {
2241 let val = (self.0 >> 11usize) & 0x01; 2270 let val = (self.0 >> 15usize) & 0x01;
2242 val != 0 2271 val != 0
2243 } 2272 }
2244 #[doc = "Output Idle state 2"] 2273 #[doc = "Main output enable"]
2245 pub fn set_ois2n(&mut self, val: bool) { 2274 pub fn set_moe(&mut self, val: bool) {
2246 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); 2275 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
2247 } 2276 }
2248 #[doc = "Output Idle state 3"] 2277 }
2249 pub const fn ois3n(&self) -> bool { 2278 impl Default for Bdtr {
2250 let val = (self.0 >> 13usize) & 0x01; 2279 fn default() -> Bdtr {
2251 val != 0 2280 Bdtr(0)
2252 } 2281 }
2253 #[doc = "Output Idle state 3"] 2282 }
2254 pub fn set_ois3n(&mut self, val: bool) { 2283 #[doc = "capture/compare mode register 1 (input mode)"]
2255 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); 2284 #[repr(transparent)]
2285 #[derive(Copy, Clone, Eq, PartialEq)]
2286 pub struct CcmrInput(pub u32);
2287 impl CcmrInput {
2288 #[doc = "Capture/Compare 1 selection"]
2289 pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs {
2290 assert!(n < 2usize);
2291 let offs = 0usize + n * 8usize;
2292 let val = (self.0 >> offs) & 0x03;
2293 super::vals::CcmrInputCcs(val as u8)
2294 }
2295 #[doc = "Capture/Compare 1 selection"]
2296 pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) {
2297 assert!(n < 2usize);
2298 let offs = 0usize + n * 8usize;
2299 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
2300 }
2301 #[doc = "Input capture 1 prescaler"]
2302 pub fn icpsc(&self, n: usize) -> u8 {
2303 assert!(n < 2usize);
2304 let offs = 2usize + n * 8usize;
2305 let val = (self.0 >> offs) & 0x03;
2306 val as u8
2307 }
2308 #[doc = "Input capture 1 prescaler"]
2309 pub fn set_icpsc(&mut self, n: usize, val: u8) {
2310 assert!(n < 2usize);
2311 let offs = 2usize + n * 8usize;
2312 self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs);
2313 }
2314 #[doc = "Input capture 1 filter"]
2315 pub fn icf(&self, n: usize) -> super::vals::Icf {
2316 assert!(n < 2usize);
2317 let offs = 4usize + n * 8usize;
2318 let val = (self.0 >> offs) & 0x0f;
2319 super::vals::Icf(val as u8)
2320 }
2321 #[doc = "Input capture 1 filter"]
2322 pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) {
2323 assert!(n < 2usize);
2324 let offs = 4usize + n * 8usize;
2325 self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
2256 } 2326 }
2257 } 2327 }
2258 impl Default for Cr2Adv { 2328 impl Default for CcmrInput {
2259 fn default() -> Cr2Adv { 2329 fn default() -> CcmrInput {
2260 Cr2Adv(0) 2330 CcmrInput(0)
2261 } 2331 }
2262 } 2332 }
2263 #[doc = "auto-reload register"] 2333 #[doc = "DMA address for full transfer"]
2264 #[repr(transparent)] 2334 #[repr(transparent)]
2265 #[derive(Copy, Clone, Eq, PartialEq)] 2335 #[derive(Copy, Clone, Eq, PartialEq)]
2266 pub struct Arr16(pub u32); 2336 pub struct Dmar(pub u32);
2267 impl Arr16 { 2337 impl Dmar {
2268 #[doc = "Auto-reload value"] 2338 #[doc = "DMA register for burst accesses"]
2269 pub const fn arr(&self) -> u16 { 2339 pub const fn dmab(&self) -> u16 {
2270 let val = (self.0 >> 0usize) & 0xffff; 2340 let val = (self.0 >> 0usize) & 0xffff;
2271 val as u16 2341 val as u16
2272 } 2342 }
2273 #[doc = "Auto-reload value"] 2343 #[doc = "DMA register for burst accesses"]
2274 pub fn set_arr(&mut self, val: u16) { 2344 pub fn set_dmab(&mut self, val: u16) {
2275 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); 2345 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
2276 } 2346 }
2277 } 2347 }
2278 impl Default for Arr16 { 2348 impl Default for Dmar {
2279 fn default() -> Arr16 { 2349 fn default() -> Dmar {
2280 Arr16(0) 2350 Dmar(0)
2351 }
2352 }
2353 #[doc = "counter"]
2354 #[repr(transparent)]
2355 #[derive(Copy, Clone, Eq, PartialEq)]
2356 pub struct Cnt32(pub u32);
2357 impl Cnt32 {
2358 #[doc = "counter value"]
2359 pub const fn cnt(&self) -> u32 {
2360 let val = (self.0 >> 0usize) & 0xffff_ffff;
2361 val as u32
2362 }
2363 #[doc = "counter value"]
2364 pub fn set_cnt(&mut self, val: u32) {
2365 self.0 =
2366 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
2367 }
2368 }
2369 impl Default for Cnt32 {
2370 fn default() -> Cnt32 {
2371 Cnt32(0)
2281 } 2372 }
2282 } 2373 }
2283 #[doc = "DMA/Interrupt enable register"] 2374 #[doc = "DMA/Interrupt enable register"]
@@ -2380,33 +2471,104 @@ pub mod timer_v1 {
2380 DierAdv(0) 2471 DierAdv(0)
2381 } 2472 }
2382 } 2473 }
2383 #[doc = "DMA control register"] 2474 #[doc = "status register"]
2384 #[repr(transparent)] 2475 #[repr(transparent)]
2385 #[derive(Copy, Clone, Eq, PartialEq)] 2476 #[derive(Copy, Clone, Eq, PartialEq)]
2386 pub struct Dcr(pub u32); 2477 pub struct SrBasic(pub u32);
2387 impl Dcr { 2478 impl SrBasic {
2388 #[doc = "DMA base address"] 2479 #[doc = "Update interrupt flag"]
2389 pub const fn dba(&self) -> u8 { 2480 pub const fn uif(&self) -> bool {
2390 let val = (self.0 >> 0usize) & 0x1f; 2481 let val = (self.0 >> 0usize) & 0x01;
2391 val as u8 2482 val != 0
2392 } 2483 }
2393 #[doc = "DMA base address"] 2484 #[doc = "Update interrupt flag"]
2394 pub fn set_dba(&mut self, val: u8) { 2485 pub fn set_uif(&mut self, val: bool) {
2395 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); 2486 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2396 } 2487 }
2397 #[doc = "DMA burst length"] 2488 }
2398 pub const fn dbl(&self) -> u8 { 2489 impl Default for SrBasic {
2399 let val = (self.0 >> 8usize) & 0x1f; 2490 fn default() -> SrBasic {
2491 SrBasic(0)
2492 }
2493 }
2494 #[doc = "event generation register"]
2495 #[repr(transparent)]
2496 #[derive(Copy, Clone, Eq, PartialEq)]
2497 pub struct EgrAdv(pub u32);
2498 impl EgrAdv {
2499 #[doc = "Update generation"]
2500 pub const fn ug(&self) -> bool {
2501 let val = (self.0 >> 0usize) & 0x01;
2502 val != 0
2503 }
2504 #[doc = "Update generation"]
2505 pub fn set_ug(&mut self, val: bool) {
2506 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2507 }
2508 #[doc = "Capture/compare 1 generation"]
2509 pub fn ccg(&self, n: usize) -> bool {
2510 assert!(n < 4usize);
2511 let offs = 1usize + n * 1usize;
2512 let val = (self.0 >> offs) & 0x01;
2513 val != 0
2514 }
2515 #[doc = "Capture/compare 1 generation"]
2516 pub fn set_ccg(&mut self, n: usize, val: bool) {
2517 assert!(n < 4usize);
2518 let offs = 1usize + n * 1usize;
2519 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2520 }
2521 #[doc = "Capture/Compare control update generation"]
2522 pub const fn comg(&self) -> bool {
2523 let val = (self.0 >> 5usize) & 0x01;
2524 val != 0
2525 }
2526 #[doc = "Capture/Compare control update generation"]
2527 pub fn set_comg(&mut self, val: bool) {
2528 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2529 }
2530 #[doc = "Trigger generation"]
2531 pub const fn tg(&self) -> bool {
2532 let val = (self.0 >> 6usize) & 0x01;
2533 val != 0
2534 }
2535 #[doc = "Trigger generation"]
2536 pub fn set_tg(&mut self, val: bool) {
2537 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2538 }
2539 #[doc = "Break generation"]
2540 pub const fn bg(&self) -> bool {
2541 let val = (self.0 >> 7usize) & 0x01;
2542 val != 0
2543 }
2544 #[doc = "Break generation"]
2545 pub fn set_bg(&mut self, val: bool) {
2546 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
2547 }
2548 }
2549 impl Default for EgrAdv {
2550 fn default() -> EgrAdv {
2551 EgrAdv(0)
2552 }
2553 }
2554 #[doc = "repetition counter register"]
2555 #[repr(transparent)]
2556 #[derive(Copy, Clone, Eq, PartialEq)]
2557 pub struct Rcr(pub u32);
2558 impl Rcr {
2559 #[doc = "Repetition counter value"]
2560 pub const fn rep(&self) -> u8 {
2561 let val = (self.0 >> 0usize) & 0xff;
2400 val as u8 2562 val as u8
2401 } 2563 }
2402 #[doc = "DMA burst length"] 2564 #[doc = "Repetition counter value"]
2403 pub fn set_dbl(&mut self, val: u8) { 2565 pub fn set_rep(&mut self, val: u8) {
2404 self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); 2566 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
2405 } 2567 }
2406 } 2568 }
2407 impl Default for Dcr { 2569 impl Default for Rcr {
2408 fn default() -> Dcr { 2570 fn default() -> Rcr {
2409 Dcr(0) 2571 Rcr(0)
2410 } 2572 }
2411 } 2573 }
2412 #[doc = "auto-reload register"] 2574 #[doc = "auto-reload register"]
@@ -2430,6 +2592,66 @@ pub mod timer_v1 {
2430 Arr32(0) 2592 Arr32(0)
2431 } 2593 }
2432 } 2594 }
2595 #[doc = "event generation register"]
2596 #[repr(transparent)]
2597 #[derive(Copy, Clone, Eq, PartialEq)]
2598 pub struct EgrBasic(pub u32);
2599 impl EgrBasic {
2600 #[doc = "Update generation"]
2601 pub const fn ug(&self) -> bool {
2602 let val = (self.0 >> 0usize) & 0x01;
2603 val != 0
2604 }
2605 #[doc = "Update generation"]
2606 pub fn set_ug(&mut self, val: bool) {
2607 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2608 }
2609 }
2610 impl Default for EgrBasic {
2611 fn default() -> EgrBasic {
2612 EgrBasic(0)
2613 }
2614 }
2615 #[doc = "counter"]
2616 #[repr(transparent)]
2617 #[derive(Copy, Clone, Eq, PartialEq)]
2618 pub struct Cnt16(pub u32);
2619 impl Cnt16 {
2620 #[doc = "counter value"]
2621 pub const fn cnt(&self) -> u16 {
2622 let val = (self.0 >> 0usize) & 0xffff;
2623 val as u16
2624 }
2625 #[doc = "counter value"]
2626 pub fn set_cnt(&mut self, val: u16) {
2627 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
2628 }
2629 }
2630 impl Default for Cnt16 {
2631 fn default() -> Cnt16 {
2632 Cnt16(0)
2633 }
2634 }
2635 #[doc = "auto-reload register"]
2636 #[repr(transparent)]
2637 #[derive(Copy, Clone, Eq, PartialEq)]
2638 pub struct Arr16(pub u32);
2639 impl Arr16 {
2640 #[doc = "Auto-reload value"]
2641 pub const fn arr(&self) -> u16 {
2642 let val = (self.0 >> 0usize) & 0xffff;
2643 val as u16
2644 }
2645 #[doc = "Auto-reload value"]
2646 pub fn set_arr(&mut self, val: u16) {
2647 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
2648 }
2649 }
2650 impl Default for Arr16 {
2651 fn default() -> Arr16 {
2652 Arr16(0)
2653 }
2654 }
2433 #[doc = "capture/compare enable register"] 2655 #[doc = "capture/compare enable register"]
2434 #[repr(transparent)] 2656 #[repr(transparent)]
2435 #[derive(Copy, Clone, Eq, PartialEq)] 2657 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -2493,24 +2715,45 @@ pub mod timer_v1 {
2493 CcerAdv(0) 2715 CcerAdv(0)
2494 } 2716 }
2495 } 2717 }
2496 #[doc = "control register 2"] 2718 #[doc = "capture/compare register 1"]
2497 #[repr(transparent)] 2719 #[repr(transparent)]
2498 #[derive(Copy, Clone, Eq, PartialEq)] 2720 #[derive(Copy, Clone, Eq, PartialEq)]
2499 pub struct Cr2Basic(pub u32); 2721 pub struct Ccr16(pub u32);
2500 impl Cr2Basic { 2722 impl Ccr16 {
2501 #[doc = "Master mode selection"] 2723 #[doc = "Capture/Compare 1 value"]
2502 pub const fn mms(&self) -> super::vals::Mms { 2724 pub const fn ccr(&self) -> u16 {
2503 let val = (self.0 >> 4usize) & 0x07; 2725 let val = (self.0 >> 0usize) & 0xffff;
2504 super::vals::Mms(val as u8) 2726 val as u16
2505 } 2727 }
2506 #[doc = "Master mode selection"] 2728 #[doc = "Capture/Compare 1 value"]
2507 pub fn set_mms(&mut self, val: super::vals::Mms) { 2729 pub fn set_ccr(&mut self, val: u16) {
2508 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); 2730 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
2509 } 2731 }
2510 } 2732 }
2511 impl Default for Cr2Basic { 2733 impl Default for Ccr16 {
2512 fn default() -> Cr2Basic { 2734 fn default() -> Ccr16 {
2513 Cr2Basic(0) 2735 Ccr16(0)
2736 }
2737 }
2738 #[doc = "capture/compare register 1"]
2739 #[repr(transparent)]
2740 #[derive(Copy, Clone, Eq, PartialEq)]
2741 pub struct Ccr32(pub u32);
2742 impl Ccr32 {
2743 #[doc = "Capture/Compare 1 value"]
2744 pub const fn ccr(&self) -> u32 {
2745 let val = (self.0 >> 0usize) & 0xffff_ffff;
2746 val as u32
2747 }
2748 #[doc = "Capture/Compare 1 value"]
2749 pub fn set_ccr(&mut self, val: u32) {
2750 self.0 =
2751 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
2752 }
2753 }
2754 impl Default for Ccr32 {
2755 fn default() -> Ccr32 {
2756 Ccr32(0)
2514 } 2757 }
2515 } 2758 }
2516 #[doc = "capture/compare enable register"] 2759 #[doc = "capture/compare enable register"]
@@ -2563,324 +2806,6 @@ pub mod timer_v1 {
2563 CcerGp(0) 2806 CcerGp(0)
2564 } 2807 }
2565 } 2808 }
2566 #[doc = "slave mode control register"]
2567 #[repr(transparent)]
2568 #[derive(Copy, Clone, Eq, PartialEq)]
2569 pub struct Smcr(pub u32);
2570 impl Smcr {
2571 #[doc = "Slave mode selection"]
2572 pub const fn sms(&self) -> super::vals::Sms {
2573 let val = (self.0 >> 0usize) & 0x07;
2574 super::vals::Sms(val as u8)
2575 }
2576 #[doc = "Slave mode selection"]
2577 pub fn set_sms(&mut self, val: super::vals::Sms) {
2578 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize);
2579 }
2580 #[doc = "Trigger selection"]
2581 pub const fn ts(&self) -> super::vals::Ts {
2582 let val = (self.0 >> 4usize) & 0x07;
2583 super::vals::Ts(val as u8)
2584 }
2585 #[doc = "Trigger selection"]
2586 pub fn set_ts(&mut self, val: super::vals::Ts) {
2587 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
2588 }
2589 #[doc = "Master/Slave mode"]
2590 pub const fn msm(&self) -> super::vals::Msm {
2591 let val = (self.0 >> 7usize) & 0x01;
2592 super::vals::Msm(val as u8)
2593 }
2594 #[doc = "Master/Slave mode"]
2595 pub fn set_msm(&mut self, val: super::vals::Msm) {
2596 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
2597 }
2598 #[doc = "External trigger filter"]
2599 pub const fn etf(&self) -> super::vals::Etf {
2600 let val = (self.0 >> 8usize) & 0x0f;
2601 super::vals::Etf(val as u8)
2602 }
2603 #[doc = "External trigger filter"]
2604 pub fn set_etf(&mut self, val: super::vals::Etf) {
2605 self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize);
2606 }
2607 #[doc = "External trigger prescaler"]
2608 pub const fn etps(&self) -> super::vals::Etps {
2609 let val = (self.0 >> 12usize) & 0x03;
2610 super::vals::Etps(val as u8)
2611 }
2612 #[doc = "External trigger prescaler"]
2613 pub fn set_etps(&mut self, val: super::vals::Etps) {
2614 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
2615 }
2616 #[doc = "External clock enable"]
2617 pub const fn ece(&self) -> super::vals::Ece {
2618 let val = (self.0 >> 14usize) & 0x01;
2619 super::vals::Ece(val as u8)
2620 }
2621 #[doc = "External clock enable"]
2622 pub fn set_ece(&mut self, val: super::vals::Ece) {
2623 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
2624 }
2625 #[doc = "External trigger polarity"]
2626 pub const fn etp(&self) -> super::vals::Etp {
2627 let val = (self.0 >> 15usize) & 0x01;
2628 super::vals::Etp(val as u8)
2629 }
2630 #[doc = "External trigger polarity"]
2631 pub fn set_etp(&mut self, val: super::vals::Etp) {
2632 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
2633 }
2634 }
2635 impl Default for Smcr {
2636 fn default() -> Smcr {
2637 Smcr(0)
2638 }
2639 }
2640 #[doc = "capture/compare mode register 1 (input mode)"]
2641 #[repr(transparent)]
2642 #[derive(Copy, Clone, Eq, PartialEq)]
2643 pub struct CcmrInput(pub u32);
2644 impl CcmrInput {
2645 #[doc = "Capture/Compare 1 selection"]
2646 pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs {
2647 assert!(n < 2usize);
2648 let offs = 0usize + n * 8usize;
2649 let val = (self.0 >> offs) & 0x03;
2650 super::vals::CcmrInputCcs(val as u8)
2651 }
2652 #[doc = "Capture/Compare 1 selection"]
2653 pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) {
2654 assert!(n < 2usize);
2655 let offs = 0usize + n * 8usize;
2656 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
2657 }
2658 #[doc = "Input capture 1 prescaler"]
2659 pub fn icpsc(&self, n: usize) -> u8 {
2660 assert!(n < 2usize);
2661 let offs = 2usize + n * 8usize;
2662 let val = (self.0 >> offs) & 0x03;
2663 val as u8
2664 }
2665 #[doc = "Input capture 1 prescaler"]
2666 pub fn set_icpsc(&mut self, n: usize, val: u8) {
2667 assert!(n < 2usize);
2668 let offs = 2usize + n * 8usize;
2669 self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs);
2670 }
2671 #[doc = "Input capture 1 filter"]
2672 pub fn icf(&self, n: usize) -> super::vals::Icf {
2673 assert!(n < 2usize);
2674 let offs = 4usize + n * 8usize;
2675 let val = (self.0 >> offs) & 0x0f;
2676 super::vals::Icf(val as u8)
2677 }
2678 #[doc = "Input capture 1 filter"]
2679 pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) {
2680 assert!(n < 2usize);
2681 let offs = 4usize + n * 8usize;
2682 self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
2683 }
2684 }
2685 impl Default for CcmrInput {
2686 fn default() -> CcmrInput {
2687 CcmrInput(0)
2688 }
2689 }
2690 #[doc = "event generation register"]
2691 #[repr(transparent)]
2692 #[derive(Copy, Clone, Eq, PartialEq)]
2693 pub struct EgrGp(pub u32);
2694 impl EgrGp {
2695 #[doc = "Update generation"]
2696 pub const fn ug(&self) -> bool {
2697 let val = (self.0 >> 0usize) & 0x01;
2698 val != 0
2699 }
2700 #[doc = "Update generation"]
2701 pub fn set_ug(&mut self, val: bool) {
2702 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2703 }
2704 #[doc = "Capture/compare 1 generation"]
2705 pub fn ccg(&self, n: usize) -> bool {
2706 assert!(n < 4usize);
2707 let offs = 1usize + n * 1usize;
2708 let val = (self.0 >> offs) & 0x01;
2709 val != 0
2710 }
2711 #[doc = "Capture/compare 1 generation"]
2712 pub fn set_ccg(&mut self, n: usize, val: bool) {
2713 assert!(n < 4usize);
2714 let offs = 1usize + n * 1usize;
2715 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2716 }
2717 #[doc = "Capture/Compare control update generation"]
2718 pub const fn comg(&self) -> bool {
2719 let val = (self.0 >> 5usize) & 0x01;
2720 val != 0
2721 }
2722 #[doc = "Capture/Compare control update generation"]
2723 pub fn set_comg(&mut self, val: bool) {
2724 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2725 }
2726 #[doc = "Trigger generation"]
2727 pub const fn tg(&self) -> bool {
2728 let val = (self.0 >> 6usize) & 0x01;
2729 val != 0
2730 }
2731 #[doc = "Trigger generation"]
2732 pub fn set_tg(&mut self, val: bool) {
2733 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2734 }
2735 #[doc = "Break generation"]
2736 pub const fn bg(&self) -> bool {
2737 let val = (self.0 >> 7usize) & 0x01;
2738 val != 0
2739 }
2740 #[doc = "Break generation"]
2741 pub fn set_bg(&mut self, val: bool) {
2742 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
2743 }
2744 }
2745 impl Default for EgrGp {
2746 fn default() -> EgrGp {
2747 EgrGp(0)
2748 }
2749 }
2750 #[doc = "control register 2"]
2751 #[repr(transparent)]
2752 #[derive(Copy, Clone, Eq, PartialEq)]
2753 pub struct Cr2Gp(pub u32);
2754 impl Cr2Gp {
2755 #[doc = "Capture/compare DMA selection"]
2756 pub const fn ccds(&self) -> super::vals::Ccds {
2757 let val = (self.0 >> 3usize) & 0x01;
2758 super::vals::Ccds(val as u8)
2759 }
2760 #[doc = "Capture/compare DMA selection"]
2761 pub fn set_ccds(&mut self, val: super::vals::Ccds) {
2762 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
2763 }
2764 #[doc = "Master mode selection"]
2765 pub const fn mms(&self) -> super::vals::Mms {
2766 let val = (self.0 >> 4usize) & 0x07;
2767 super::vals::Mms(val as u8)
2768 }
2769 #[doc = "Master mode selection"]
2770 pub fn set_mms(&mut self, val: super::vals::Mms) {
2771 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
2772 }
2773 #[doc = "TI1 selection"]
2774 pub const fn ti1s(&self) -> super::vals::Tis {
2775 let val = (self.0 >> 7usize) & 0x01;
2776 super::vals::Tis(val as u8)
2777 }
2778 #[doc = "TI1 selection"]
2779 pub fn set_ti1s(&mut self, val: super::vals::Tis) {
2780 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
2781 }
2782 }
2783 impl Default for Cr2Gp {
2784 fn default() -> Cr2Gp {
2785 Cr2Gp(0)
2786 }
2787 }
2788 #[doc = "counter"]
2789 #[repr(transparent)]
2790 #[derive(Copy, Clone, Eq, PartialEq)]
2791 pub struct Cnt16(pub u32);
2792 impl Cnt16 {
2793 #[doc = "counter value"]
2794 pub const fn cnt(&self) -> u16 {
2795 let val = (self.0 >> 0usize) & 0xffff;
2796 val as u16
2797 }
2798 #[doc = "counter value"]
2799 pub fn set_cnt(&mut self, val: u16) {
2800 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
2801 }
2802 }
2803 impl Default for Cnt16 {
2804 fn default() -> Cnt16 {
2805 Cnt16(0)
2806 }
2807 }
2808 #[doc = "control register 1"]
2809 #[repr(transparent)]
2810 #[derive(Copy, Clone, Eq, PartialEq)]
2811 pub struct Cr1Basic(pub u32);
2812 impl Cr1Basic {
2813 #[doc = "Counter enable"]
2814 pub const fn cen(&self) -> bool {
2815 let val = (self.0 >> 0usize) & 0x01;
2816 val != 0
2817 }
2818 #[doc = "Counter enable"]
2819 pub fn set_cen(&mut self, val: bool) {
2820 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2821 }
2822 #[doc = "Update disable"]
2823 pub const fn udis(&self) -> bool {
2824 let val = (self.0 >> 1usize) & 0x01;
2825 val != 0
2826 }
2827 #[doc = "Update disable"]
2828 pub fn set_udis(&mut self, val: bool) {
2829 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2830 }
2831 #[doc = "Update request source"]
2832 pub const fn urs(&self) -> super::vals::Urs {
2833 let val = (self.0 >> 2usize) & 0x01;
2834 super::vals::Urs(val as u8)
2835 }
2836 #[doc = "Update request source"]
2837 pub fn set_urs(&mut self, val: super::vals::Urs) {
2838 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
2839 }
2840 #[doc = "One-pulse mode"]
2841 pub const fn opm(&self) -> super::vals::Opm {
2842 let val = (self.0 >> 3usize) & 0x01;
2843 super::vals::Opm(val as u8)
2844 }
2845 #[doc = "One-pulse mode"]
2846 pub fn set_opm(&mut self, val: super::vals::Opm) {
2847 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
2848 }
2849 #[doc = "Auto-reload preload enable"]
2850 pub const fn arpe(&self) -> super::vals::Arpe {
2851 let val = (self.0 >> 7usize) & 0x01;
2852 super::vals::Arpe(val as u8)
2853 }
2854 #[doc = "Auto-reload preload enable"]
2855 pub fn set_arpe(&mut self, val: super::vals::Arpe) {
2856 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
2857 }
2858 }
2859 impl Default for Cr1Basic {
2860 fn default() -> Cr1Basic {
2861 Cr1Basic(0)
2862 }
2863 }
2864 #[doc = "repetition counter register"]
2865 #[repr(transparent)]
2866 #[derive(Copy, Clone, Eq, PartialEq)]
2867 pub struct Rcr(pub u32);
2868 impl Rcr {
2869 #[doc = "Repetition counter value"]
2870 pub const fn rep(&self) -> u8 {
2871 let val = (self.0 >> 0usize) & 0xff;
2872 val as u8
2873 }
2874 #[doc = "Repetition counter value"]
2875 pub fn set_rep(&mut self, val: u8) {
2876 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
2877 }
2878 }
2879 impl Default for Rcr {
2880 fn default() -> Rcr {
2881 Rcr(0)
2882 }
2883 }
2884 #[doc = "status register"] 2809 #[doc = "status register"]
2885 #[repr(transparent)] 2810 #[repr(transparent)]
2886 #[derive(Copy, Clone, Eq, PartialEq)] 2811 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -2956,1274 +2881,553 @@ pub mod timer_v1 {
2956 } 2881 }
2957 } 2882 }
2958} 2883}
2959pub mod dma_v2 { 2884pub mod syscfg_l4 {
2960 use crate::generic::*; 2885 use crate::generic::*;
2961 #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] 2886 #[doc = "System configuration controller"]
2962 #[derive(Copy, Clone)] 2887 #[derive(Copy, Clone)]
2963 pub struct St(pub *mut u8); 2888 pub struct Syscfg(pub *mut u8);
2964 unsafe impl Send for St {} 2889 unsafe impl Send for Syscfg {}
2965 unsafe impl Sync for St {} 2890 unsafe impl Sync for Syscfg {}
2966 impl St { 2891 impl Syscfg {
2967 #[doc = "stream x configuration register"] 2892 #[doc = "memory remap register"]
2968 pub fn cr(self) -> Reg<regs::Cr, RW> { 2893 pub fn memrmp(self) -> Reg<regs::Memrmp, RW> {
2969 unsafe { Reg::from_ptr(self.0.add(0usize)) } 2894 unsafe { Reg::from_ptr(self.0.add(0usize)) }
2970 } 2895 }
2971 #[doc = "stream x number of data register"] 2896 #[doc = "configuration register 1"]
2972 pub fn ndtr(self) -> Reg<regs::Ndtr, RW> { 2897 pub fn cfgr1(self) -> Reg<regs::Cfgr1, RW> {
2973 unsafe { Reg::from_ptr(self.0.add(4usize)) } 2898 unsafe { Reg::from_ptr(self.0.add(4usize)) }
2974 } 2899 }
2975 #[doc = "stream x peripheral address register"] 2900 #[doc = "external interrupt configuration register 1"]
2976 pub fn par(self) -> Reg<u32, RW> { 2901 pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
2977 unsafe { Reg::from_ptr(self.0.add(8usize)) } 2902 assert!(n < 4usize);
2978 } 2903 unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
2979 #[doc = "stream x memory 0 address register"]
2980 pub fn m0ar(self) -> Reg<u32, RW> {
2981 unsafe { Reg::from_ptr(self.0.add(12usize)) }
2982 }
2983 #[doc = "stream x memory 1 address register"]
2984 pub fn m1ar(self) -> Reg<u32, RW> {
2985 unsafe { Reg::from_ptr(self.0.add(16usize)) }
2986 } 2904 }
2987 #[doc = "stream x FIFO control register"] 2905 #[doc = "SCSR"]
2988 pub fn fcr(self) -> Reg<regs::Fcr, RW> { 2906 pub fn scsr(self) -> Reg<regs::Scsr, RW> {
2989 unsafe { Reg::from_ptr(self.0.add(20usize)) } 2907 unsafe { Reg::from_ptr(self.0.add(24usize)) }
2990 } 2908 }
2991 } 2909 #[doc = "CFGR2"]
2992 #[doc = "DMA controller"] 2910 pub fn cfgr2(self) -> Reg<regs::Cfgr2, RW> {
2993 #[derive(Copy, Clone)] 2911 unsafe { Reg::from_ptr(self.0.add(28usize)) }
2994 pub struct Dma(pub *mut u8);
2995 unsafe impl Send for Dma {}
2996 unsafe impl Sync for Dma {}
2997 impl Dma {
2998 #[doc = "low interrupt status register"]
2999 pub fn isr(self, n: usize) -> Reg<regs::Isr, R> {
3000 assert!(n < 2usize);
3001 unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
3002 } 2912 }
3003 #[doc = "low interrupt flag clear register"] 2913 #[doc = "SWPR"]
3004 pub fn ifcr(self, n: usize) -> Reg<regs::Ifcr, W> { 2914 pub fn swpr(self) -> Reg<regs::Swpr, W> {
3005 assert!(n < 2usize); 2915 unsafe { Reg::from_ptr(self.0.add(32usize)) }
3006 unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
3007 } 2916 }
3008 #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] 2917 #[doc = "SKR"]
3009 pub fn st(self, n: usize) -> St { 2918 pub fn skr(self) -> Reg<regs::Skr, W> {
3010 assert!(n < 8usize); 2919 unsafe { Reg::from_ptr(self.0.add(36usize)) }
3011 unsafe { St(self.0.add(16usize + n * 24usize)) }
3012 } 2920 }
3013 } 2921 }
3014 pub mod regs { 2922 pub mod regs {
3015 use crate::generic::*; 2923 use crate::generic::*;
3016 #[doc = "stream x number of data register"] 2924 #[doc = "external interrupt configuration register 4"]
3017 #[repr(transparent)] 2925 #[repr(transparent)]
3018 #[derive(Copy, Clone, Eq, PartialEq)] 2926 #[derive(Copy, Clone, Eq, PartialEq)]
3019 pub struct Ndtr(pub u32); 2927 pub struct Exticr(pub u32);
3020 impl Ndtr { 2928 impl Exticr {
3021 #[doc = "Number of data items to transfer"] 2929 #[doc = "EXTI12 configuration bits"]
3022 pub const fn ndt(&self) -> u16 { 2930 pub fn exti(&self, n: usize) -> u8 {
3023 let val = (self.0 >> 0usize) & 0xffff; 2931 assert!(n < 4usize);
3024 val as u16 2932 let offs = 0usize + n * 4usize;
2933 let val = (self.0 >> offs) & 0x0f;
2934 val as u8
3025 } 2935 }
3026 #[doc = "Number of data items to transfer"] 2936 #[doc = "EXTI12 configuration bits"]
3027 pub fn set_ndt(&mut self, val: u16) { 2937 pub fn set_exti(&mut self, n: usize, val: u8) {
3028 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); 2938 assert!(n < 4usize);
2939 let offs = 0usize + n * 4usize;
2940 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
3029 } 2941 }
3030 } 2942 }
3031 impl Default for Ndtr { 2943 impl Default for Exticr {
3032 fn default() -> Ndtr { 2944 fn default() -> Exticr {
3033 Ndtr(0) 2945 Exticr(0)
3034 } 2946 }
3035 } 2947 }
3036 #[doc = "stream x FIFO control register"] 2948 #[doc = "SWPR"]
3037 #[repr(transparent)] 2949 #[repr(transparent)]
3038 #[derive(Copy, Clone, Eq, PartialEq)] 2950 #[derive(Copy, Clone, Eq, PartialEq)]
3039 pub struct Fcr(pub u32); 2951 pub struct Swpr(pub u32);
3040 impl Fcr { 2952 impl Swpr {
3041 #[doc = "FIFO threshold selection"] 2953 #[doc = "SRAWM2 write protection."]
3042 pub const fn fth(&self) -> super::vals::Fth { 2954 pub fn pwp(&self, n: usize) -> bool {
3043 let val = (self.0 >> 0usize) & 0x03; 2955 assert!(n < 32usize);
3044 super::vals::Fth(val as u8) 2956 let offs = 0usize + n * 1usize;
3045 } 2957 let val = (self.0 >> offs) & 0x01;
3046 #[doc = "FIFO threshold selection"]
3047 pub fn set_fth(&mut self, val: super::vals::Fth) {
3048 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
3049 }
3050 #[doc = "Direct mode disable"]
3051 pub const fn dmdis(&self) -> super::vals::Dmdis {
3052 let val = (self.0 >> 2usize) & 0x01;
3053 super::vals::Dmdis(val as u8)
3054 }
3055 #[doc = "Direct mode disable"]
3056 pub fn set_dmdis(&mut self, val: super::vals::Dmdis) {
3057 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
3058 }
3059 #[doc = "FIFO status"]
3060 pub const fn fs(&self) -> super::vals::Fs {
3061 let val = (self.0 >> 3usize) & 0x07;
3062 super::vals::Fs(val as u8)
3063 }
3064 #[doc = "FIFO status"]
3065 pub fn set_fs(&mut self, val: super::vals::Fs) {
3066 self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
3067 }
3068 #[doc = "FIFO error interrupt enable"]
3069 pub const fn feie(&self) -> bool {
3070 let val = (self.0 >> 7usize) & 0x01;
3071 val != 0 2958 val != 0
3072 } 2959 }
3073 #[doc = "FIFO error interrupt enable"] 2960 #[doc = "SRAWM2 write protection."]
3074 pub fn set_feie(&mut self, val: bool) { 2961 pub fn set_pwp(&mut self, n: usize, val: bool) {
3075 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); 2962 assert!(n < 32usize);
2963 let offs = 0usize + n * 1usize;
2964 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3076 } 2965 }
3077 } 2966 }
3078 impl Default for Fcr { 2967 impl Default for Swpr {
3079 fn default() -> Fcr { 2968 fn default() -> Swpr {
3080 Fcr(0) 2969 Swpr(0)
3081 } 2970 }
3082 } 2971 }
3083 #[doc = "stream x configuration register"] 2972 #[doc = "SCSR"]
3084 #[repr(transparent)] 2973 #[repr(transparent)]
3085 #[derive(Copy, Clone, Eq, PartialEq)] 2974 #[derive(Copy, Clone, Eq, PartialEq)]
3086 pub struct Cr(pub u32); 2975 pub struct Scsr(pub u32);
3087 impl Cr { 2976 impl Scsr {
3088 #[doc = "Stream enable / flag stream ready when read low"] 2977 #[doc = "SRAM2 Erase"]
3089 pub const fn en(&self) -> bool { 2978 pub const fn sram2er(&self) -> bool {
3090 let val = (self.0 >> 0usize) & 0x01; 2979 let val = (self.0 >> 0usize) & 0x01;
3091 val != 0 2980 val != 0
3092 } 2981 }
3093 #[doc = "Stream enable / flag stream ready when read low"] 2982 #[doc = "SRAM2 Erase"]
3094 pub fn set_en(&mut self, val: bool) { 2983 pub fn set_sram2er(&mut self, val: bool) {
3095 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 2984 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3096 } 2985 }
3097 #[doc = "Direct mode error interrupt enable"] 2986 #[doc = "SRAM2 busy by erase operation"]
3098 pub const fn dmeie(&self) -> bool { 2987 pub const fn sram2bsy(&self) -> bool {
3099 let val = (self.0 >> 1usize) & 0x01; 2988 let val = (self.0 >> 1usize) & 0x01;
3100 val != 0 2989 val != 0
3101 } 2990 }
3102 #[doc = "Direct mode error interrupt enable"] 2991 #[doc = "SRAM2 busy by erase operation"]
3103 pub fn set_dmeie(&mut self, val: bool) { 2992 pub fn set_sram2bsy(&mut self, val: bool) {
3104 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); 2993 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3105 } 2994 }
3106 #[doc = "Transfer error interrupt enable"]
3107 pub const fn teie(&self) -> bool {
3108 let val = (self.0 >> 2usize) & 0x01;
3109 val != 0
3110 }
3111 #[doc = "Transfer error interrupt enable"]
3112 pub fn set_teie(&mut self, val: bool) {
3113 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3114 }
3115 #[doc = "Half transfer interrupt enable"]
3116 pub const fn htie(&self) -> bool {
3117 let val = (self.0 >> 3usize) & 0x01;
3118 val != 0
3119 }
3120 #[doc = "Half transfer interrupt enable"]
3121 pub fn set_htie(&mut self, val: bool) {
3122 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
3123 }
3124 #[doc = "Transfer complete interrupt enable"]
3125 pub const fn tcie(&self) -> bool {
3126 let val = (self.0 >> 4usize) & 0x01;
3127 val != 0
3128 }
3129 #[doc = "Transfer complete interrupt enable"]
3130 pub fn set_tcie(&mut self, val: bool) {
3131 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
3132 }
3133 #[doc = "Peripheral flow controller"]
3134 pub const fn pfctrl(&self) -> super::vals::Pfctrl {
3135 let val = (self.0 >> 5usize) & 0x01;
3136 super::vals::Pfctrl(val as u8)
3137 }
3138 #[doc = "Peripheral flow controller"]
3139 pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) {
3140 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
3141 }
3142 #[doc = "Data transfer direction"]
3143 pub const fn dir(&self) -> super::vals::Dir {
3144 let val = (self.0 >> 6usize) & 0x03;
3145 super::vals::Dir(val as u8)
3146 }
3147 #[doc = "Data transfer direction"]
3148 pub fn set_dir(&mut self, val: super::vals::Dir) {
3149 self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize);
3150 }
3151 #[doc = "Circular mode"]
3152 pub const fn circ(&self) -> super::vals::Circ {
3153 let val = (self.0 >> 8usize) & 0x01;
3154 super::vals::Circ(val as u8)
3155 }
3156 #[doc = "Circular mode"]
3157 pub fn set_circ(&mut self, val: super::vals::Circ) {
3158 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
3159 }
3160 #[doc = "Peripheral increment mode"]
3161 pub const fn pinc(&self) -> super::vals::Inc {
3162 let val = (self.0 >> 9usize) & 0x01;
3163 super::vals::Inc(val as u8)
3164 }
3165 #[doc = "Peripheral increment mode"]
3166 pub fn set_pinc(&mut self, val: super::vals::Inc) {
3167 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
3168 }
3169 #[doc = "Memory increment mode"]
3170 pub const fn minc(&self) -> super::vals::Inc {
3171 let val = (self.0 >> 10usize) & 0x01;
3172 super::vals::Inc(val as u8)
3173 }
3174 #[doc = "Memory increment mode"]
3175 pub fn set_minc(&mut self, val: super::vals::Inc) {
3176 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
3177 }
3178 #[doc = "Peripheral data size"]
3179 pub const fn psize(&self) -> super::vals::Size {
3180 let val = (self.0 >> 11usize) & 0x03;
3181 super::vals::Size(val as u8)
3182 }
3183 #[doc = "Peripheral data size"]
3184 pub fn set_psize(&mut self, val: super::vals::Size) {
3185 self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize);
3186 }
3187 #[doc = "Memory data size"]
3188 pub const fn msize(&self) -> super::vals::Size {
3189 let val = (self.0 >> 13usize) & 0x03;
3190 super::vals::Size(val as u8)
3191 }
3192 #[doc = "Memory data size"]
3193 pub fn set_msize(&mut self, val: super::vals::Size) {
3194 self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize);
3195 }
3196 #[doc = "Peripheral increment offset size"]
3197 pub const fn pincos(&self) -> super::vals::Pincos {
3198 let val = (self.0 >> 15usize) & 0x01;
3199 super::vals::Pincos(val as u8)
3200 }
3201 #[doc = "Peripheral increment offset size"]
3202 pub fn set_pincos(&mut self, val: super::vals::Pincos) {
3203 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
3204 }
3205 #[doc = "Priority level"]
3206 pub const fn pl(&self) -> super::vals::Pl {
3207 let val = (self.0 >> 16usize) & 0x03;
3208 super::vals::Pl(val as u8)
3209 }
3210 #[doc = "Priority level"]
3211 pub fn set_pl(&mut self, val: super::vals::Pl) {
3212 self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize);
3213 }
3214 #[doc = "Double buffer mode"]
3215 pub const fn dbm(&self) -> super::vals::Dbm {
3216 let val = (self.0 >> 18usize) & 0x01;
3217 super::vals::Dbm(val as u8)
3218 }
3219 #[doc = "Double buffer mode"]
3220 pub fn set_dbm(&mut self, val: super::vals::Dbm) {
3221 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
3222 }
3223 #[doc = "Current target (only in double buffer mode)"]
3224 pub const fn ct(&self) -> super::vals::Ct {
3225 let val = (self.0 >> 19usize) & 0x01;
3226 super::vals::Ct(val as u8)
3227 }
3228 #[doc = "Current target (only in double buffer mode)"]
3229 pub fn set_ct(&mut self, val: super::vals::Ct) {
3230 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
3231 }
3232 #[doc = "Peripheral burst transfer configuration"]
3233 pub const fn pburst(&self) -> super::vals::Burst {
3234 let val = (self.0 >> 21usize) & 0x03;
3235 super::vals::Burst(val as u8)
3236 }
3237 #[doc = "Peripheral burst transfer configuration"]
3238 pub fn set_pburst(&mut self, val: super::vals::Burst) {
3239 self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize);
3240 }
3241 #[doc = "Memory burst transfer configuration"]
3242 pub const fn mburst(&self) -> super::vals::Burst {
3243 let val = (self.0 >> 23usize) & 0x03;
3244 super::vals::Burst(val as u8)
3245 }
3246 #[doc = "Memory burst transfer configuration"]
3247 pub fn set_mburst(&mut self, val: super::vals::Burst) {
3248 self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize);
3249 }
3250 #[doc = "Channel selection"]
3251 pub const fn chsel(&self) -> u8 {
3252 let val = (self.0 >> 25usize) & 0x0f;
3253 val as u8
3254 }
3255 #[doc = "Channel selection"]
3256 pub fn set_chsel(&mut self, val: u8) {
3257 self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize);
3258 }
3259 }
3260 impl Default for Cr {
3261 fn default() -> Cr {
3262 Cr(0)
3263 }
3264 } 2995 }
3265 #[doc = "low interrupt status register"] 2996 impl Default for Scsr {
3266 #[repr(transparent)] 2997 fn default() -> Scsr {
3267 #[derive(Copy, Clone, Eq, PartialEq)] 2998 Scsr(0)
3268 pub struct Isr(pub u32);
3269 impl Isr {
3270 #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
3271 pub fn feif(&self, n: usize) -> bool {
3272 assert!(n < 4usize);
3273 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3274 let val = (self.0 >> offs) & 0x01;
3275 val != 0
3276 }
3277 #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
3278 pub fn set_feif(&mut self, n: usize, val: bool) {
3279 assert!(n < 4usize);
3280 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3281 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3282 }
3283 #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
3284 pub fn dmeif(&self, n: usize) -> bool {
3285 assert!(n < 4usize);
3286 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3287 let val = (self.0 >> offs) & 0x01;
3288 val != 0
3289 }
3290 #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
3291 pub fn set_dmeif(&mut self, n: usize, val: bool) {
3292 assert!(n < 4usize);
3293 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3294 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3295 }
3296 #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
3297 pub fn teif(&self, n: usize) -> bool {
3298 assert!(n < 4usize);
3299 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3300 let val = (self.0 >> offs) & 0x01;
3301 val != 0
3302 }
3303 #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
3304 pub fn set_teif(&mut self, n: usize, val: bool) {
3305 assert!(n < 4usize);
3306 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3307 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3308 }
3309 #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
3310 pub fn htif(&self, n: usize) -> bool {
3311 assert!(n < 4usize);
3312 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3313 let val = (self.0 >> offs) & 0x01;
3314 val != 0
3315 }
3316 #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
3317 pub fn set_htif(&mut self, n: usize, val: bool) {
3318 assert!(n < 4usize);
3319 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3320 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3321 }
3322 #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
3323 pub fn tcif(&self, n: usize) -> bool {
3324 assert!(n < 4usize);
3325 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3326 let val = (self.0 >> offs) & 0x01;
3327 val != 0
3328 }
3329 #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
3330 pub fn set_tcif(&mut self, n: usize, val: bool) {
3331 assert!(n < 4usize);
3332 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3333 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3334 }
3335 }
3336 impl Default for Isr {
3337 fn default() -> Isr {
3338 Isr(0)
3339 } 2999 }
3340 } 3000 }
3341 #[doc = "low interrupt flag clear register"] 3001 #[doc = "SKR"]
3342 #[repr(transparent)] 3002 #[repr(transparent)]
3343 #[derive(Copy, Clone, Eq, PartialEq)] 3003 #[derive(Copy, Clone, Eq, PartialEq)]
3344 pub struct Ifcr(pub u32); 3004 pub struct Skr(pub u32);
3345 impl Ifcr { 3005 impl Skr {
3346 #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"] 3006 #[doc = "SRAM2 write protection key for software erase"]
3347 pub fn cfeif(&self, n: usize) -> bool { 3007 pub const fn key(&self) -> u8 {
3348 assert!(n < 4usize); 3008 let val = (self.0 >> 0usize) & 0xff;
3349 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); 3009 val as u8
3350 let val = (self.0 >> offs) & 0x01;
3351 val != 0
3352 }
3353 #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"]
3354 pub fn set_cfeif(&mut self, n: usize, val: bool) {
3355 assert!(n < 4usize);
3356 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3357 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3358 }
3359 #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"]
3360 pub fn cdmeif(&self, n: usize) -> bool {
3361 assert!(n < 4usize);
3362 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3363 let val = (self.0 >> offs) & 0x01;
3364 val != 0
3365 }
3366 #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"]
3367 pub fn set_cdmeif(&mut self, n: usize, val: bool) {
3368 assert!(n < 4usize);
3369 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3370 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3371 }
3372 #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"]
3373 pub fn cteif(&self, n: usize) -> bool {
3374 assert!(n < 4usize);
3375 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3376 let val = (self.0 >> offs) & 0x01;
3377 val != 0
3378 }
3379 #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"]
3380 pub fn set_cteif(&mut self, n: usize, val: bool) {
3381 assert!(n < 4usize);
3382 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3383 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3384 }
3385 #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"]
3386 pub fn chtif(&self, n: usize) -> bool {
3387 assert!(n < 4usize);
3388 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3389 let val = (self.0 >> offs) & 0x01;
3390 val != 0
3391 }
3392 #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"]
3393 pub fn set_chtif(&mut self, n: usize, val: bool) {
3394 assert!(n < 4usize);
3395 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3396 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3397 }
3398 #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"]
3399 pub fn ctcif(&self, n: usize) -> bool {
3400 assert!(n < 4usize);
3401 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3402 let val = (self.0 >> offs) & 0x01;
3403 val != 0
3404 } 3010 }
3405 #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"] 3011 #[doc = "SRAM2 write protection key for software erase"]
3406 pub fn set_ctcif(&mut self, n: usize, val: bool) { 3012 pub fn set_key(&mut self, val: u8) {
3407 assert!(n < 4usize); 3013 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
3408 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
3409 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3410 } 3014 }
3411 } 3015 }
3412 impl Default for Ifcr { 3016 impl Default for Skr {
3413 fn default() -> Ifcr { 3017 fn default() -> Skr {
3414 Ifcr(0) 3018 Skr(0)
3415 } 3019 }
3416 } 3020 }
3417 } 3021 #[doc = "memory remap register"]
3418 pub mod vals {
3419 use crate::generic::*;
3420 #[repr(transparent)]
3421 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3422 pub struct Inc(pub u8);
3423 impl Inc {
3424 #[doc = "Address pointer is fixed"]
3425 pub const FIXED: Self = Self(0);
3426 #[doc = "Address pointer is incremented after each data transfer"]
3427 pub const INCREMENTED: Self = Self(0x01);
3428 }
3429 #[repr(transparent)]
3430 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3431 pub struct Pfctrl(pub u8);
3432 impl Pfctrl {
3433 #[doc = "The DMA is the flow controller"]
3434 pub const DMA: Self = Self(0);
3435 #[doc = "The peripheral is the flow controller"]
3436 pub const PERIPHERAL: Self = Self(0x01);
3437 }
3438 #[repr(transparent)]
3439 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3440 pub struct Fth(pub u8);
3441 impl Fth {
3442 #[doc = "1/4 full FIFO"]
3443 pub const QUARTER: Self = Self(0);
3444 #[doc = "1/2 full FIFO"]
3445 pub const HALF: Self = Self(0x01);
3446 #[doc = "3/4 full FIFO"]
3447 pub const THREEQUARTERS: Self = Self(0x02);
3448 #[doc = "Full FIFO"]
3449 pub const FULL: Self = Self(0x03);
3450 }
3451 #[repr(transparent)]
3452 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3453 pub struct Fs(pub u8);
3454 impl Fs {
3455 #[doc = "0 < fifo_level < 1/4"]
3456 pub const QUARTER1: Self = Self(0);
3457 #[doc = "1/4 <= fifo_level < 1/2"]
3458 pub const QUARTER2: Self = Self(0x01);
3459 #[doc = "1/2 <= fifo_level < 3/4"]
3460 pub const QUARTER3: Self = Self(0x02);
3461 #[doc = "3/4 <= fifo_level < full"]
3462 pub const QUARTER4: Self = Self(0x03);
3463 #[doc = "FIFO is empty"]
3464 pub const EMPTY: Self = Self(0x04);
3465 #[doc = "FIFO is full"]
3466 pub const FULL: Self = Self(0x05);
3467 }
3468 #[repr(transparent)]
3469 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3470 pub struct Circ(pub u8);
3471 impl Circ {
3472 #[doc = "Circular mode disabled"]
3473 pub const DISABLED: Self = Self(0);
3474 #[doc = "Circular mode enabled"]
3475 pub const ENABLED: Self = Self(0x01);
3476 }
3477 #[repr(transparent)]
3478 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3479 pub struct Dbm(pub u8);
3480 impl Dbm {
3481 #[doc = "No buffer switching at the end of transfer"]
3482 pub const DISABLED: Self = Self(0);
3483 #[doc = "Memory target switched at the end of the DMA transfer"]
3484 pub const ENABLED: Self = Self(0x01);
3485 }
3486 #[repr(transparent)]
3487 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3488 pub struct Size(pub u8);
3489 impl Size {
3490 #[doc = "Byte (8-bit)"]
3491 pub const BITS8: Self = Self(0);
3492 #[doc = "Half-word (16-bit)"]
3493 pub const BITS16: Self = Self(0x01);
3494 #[doc = "Word (32-bit)"]
3495 pub const BITS32: Self = Self(0x02);
3496 }
3497 #[repr(transparent)]
3498 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3499 pub struct Dmdis(pub u8);
3500 impl Dmdis {
3501 #[doc = "Direct mode is enabled"]
3502 pub const ENABLED: Self = Self(0);
3503 #[doc = "Direct mode is disabled"]
3504 pub const DISABLED: Self = Self(0x01);
3505 }
3506 #[repr(transparent)]
3507 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3508 pub struct Pincos(pub u8);
3509 impl Pincos {
3510 #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"]
3511 pub const PSIZE: Self = Self(0);
3512 #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"]
3513 pub const FIXED4: Self = Self(0x01);
3514 }
3515 #[repr(transparent)]
3516 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3517 pub struct Burst(pub u8);
3518 impl Burst {
3519 #[doc = "Single transfer"]
3520 pub const SINGLE: Self = Self(0);
3521 #[doc = "Incremental burst of 4 beats"]
3522 pub const INCR4: Self = Self(0x01);
3523 #[doc = "Incremental burst of 8 beats"]
3524 pub const INCR8: Self = Self(0x02);
3525 #[doc = "Incremental burst of 16 beats"]
3526 pub const INCR16: Self = Self(0x03);
3527 }
3528 #[repr(transparent)]
3529 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3530 pub struct Pl(pub u8);
3531 impl Pl {
3532 #[doc = "Low"]
3533 pub const LOW: Self = Self(0);
3534 #[doc = "Medium"]
3535 pub const MEDIUM: Self = Self(0x01);
3536 #[doc = "High"]
3537 pub const HIGH: Self = Self(0x02);
3538 #[doc = "Very high"]
3539 pub const VERYHIGH: Self = Self(0x03);
3540 }
3541 #[repr(transparent)]
3542 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3543 pub struct Dir(pub u8);
3544 impl Dir {
3545 #[doc = "Peripheral-to-memory"]
3546 pub const PERIPHERALTOMEMORY: Self = Self(0);
3547 #[doc = "Memory-to-peripheral"]
3548 pub const MEMORYTOPERIPHERAL: Self = Self(0x01);
3549 #[doc = "Memory-to-memory"]
3550 pub const MEMORYTOMEMORY: Self = Self(0x02);
3551 }
3552 #[repr(transparent)]
3553 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3554 pub struct Ct(pub u8);
3555 impl Ct {
3556 #[doc = "The current target memory is Memory 0"]
3557 pub const MEMORY0: Self = Self(0);
3558 #[doc = "The current target memory is Memory 1"]
3559 pub const MEMORY1: Self = Self(0x01);
3560 }
3561 }
3562}
3563pub mod dma_v1 {
3564 use crate::generic::*;
3565 #[doc = "DMA controller"]
3566 #[derive(Copy, Clone)]
3567 pub struct Dma(pub *mut u8);
3568 unsafe impl Send for Dma {}
3569 unsafe impl Sync for Dma {}
3570 impl Dma {
3571 #[doc = "DMA interrupt status register (DMA_ISR)"]
3572 pub fn isr(self) -> Reg<regs::Isr, R> {
3573 unsafe { Reg::from_ptr(self.0.add(0usize)) }
3574 }
3575 #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
3576 pub fn ifcr(self) -> Reg<regs::Ifcr, W> {
3577 unsafe { Reg::from_ptr(self.0.add(4usize)) }
3578 }
3579 #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
3580 pub fn ch(self, n: usize) -> Ch {
3581 assert!(n < 7usize);
3582 unsafe { Ch(self.0.add(8usize + n * 20usize)) }
3583 }
3584 }
3585 #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
3586 #[derive(Copy, Clone)]
3587 pub struct Ch(pub *mut u8);
3588 unsafe impl Send for Ch {}
3589 unsafe impl Sync for Ch {}
3590 impl Ch {
3591 #[doc = "DMA channel configuration register (DMA_CCR)"]
3592 pub fn cr(self) -> Reg<regs::Cr, RW> {
3593 unsafe { Reg::from_ptr(self.0.add(0usize)) }
3594 }
3595 #[doc = "DMA channel 1 number of data register"]
3596 pub fn ndtr(self) -> Reg<regs::Ndtr, RW> {
3597 unsafe { Reg::from_ptr(self.0.add(4usize)) }
3598 }
3599 #[doc = "DMA channel 1 peripheral address register"]
3600 pub fn par(self) -> Reg<u32, RW> {
3601 unsafe { Reg::from_ptr(self.0.add(8usize)) }
3602 }
3603 #[doc = "DMA channel 1 memory address register"]
3604 pub fn mar(self) -> Reg<u32, RW> {
3605 unsafe { Reg::from_ptr(self.0.add(12usize)) }
3606 }
3607 }
3608 pub mod vals {
3609 use crate::generic::*;
3610 #[repr(transparent)]
3611 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3612 pub struct Circ(pub u8);
3613 impl Circ {
3614 #[doc = "Circular buffer disabled"]
3615 pub const DISABLED: Self = Self(0);
3616 #[doc = "Circular buffer enabled"]
3617 pub const ENABLED: Self = Self(0x01);
3618 }
3619 #[repr(transparent)]
3620 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3621 pub struct Pl(pub u8);
3622 impl Pl {
3623 #[doc = "Low priority"]
3624 pub const LOW: Self = Self(0);
3625 #[doc = "Medium priority"]
3626 pub const MEDIUM: Self = Self(0x01);
3627 #[doc = "High priority"]
3628 pub const HIGH: Self = Self(0x02);
3629 #[doc = "Very high priority"]
3630 pub const VERYHIGH: Self = Self(0x03);
3631 }
3632 #[repr(transparent)]
3633 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3634 pub struct Inc(pub u8);
3635 impl Inc {
3636 #[doc = "Increment mode disabled"]
3637 pub const DISABLED: Self = Self(0);
3638 #[doc = "Increment mode enabled"]
3639 pub const ENABLED: Self = Self(0x01);
3640 }
3641 #[repr(transparent)]
3642 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3643 pub struct Memmem(pub u8);
3644 impl Memmem {
3645 #[doc = "Memory to memory mode disabled"]
3646 pub const DISABLED: Self = Self(0);
3647 #[doc = "Memory to memory mode enabled"]
3648 pub const ENABLED: Self = Self(0x01);
3649 }
3650 #[repr(transparent)]
3651 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3652 pub struct Dir(pub u8);
3653 impl Dir {
3654 #[doc = "Read from peripheral"]
3655 pub const FROMPERIPHERAL: Self = Self(0);
3656 #[doc = "Read from memory"]
3657 pub const FROMMEMORY: Self = Self(0x01);
3658 }
3659 #[repr(transparent)]
3660 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3661 pub struct Size(pub u8);
3662 impl Size {
3663 #[doc = "8-bit size"]
3664 pub const BITS8: Self = Self(0);
3665 #[doc = "16-bit size"]
3666 pub const BITS16: Self = Self(0x01);
3667 #[doc = "32-bit size"]
3668 pub const BITS32: Self = Self(0x02);
3669 }
3670 }
3671 pub mod regs {
3672 use crate::generic::*;
3673 #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
3674 #[repr(transparent)] 3022 #[repr(transparent)]
3675 #[derive(Copy, Clone, Eq, PartialEq)] 3023 #[derive(Copy, Clone, Eq, PartialEq)]
3676 pub struct Ifcr(pub u32); 3024 pub struct Memrmp(pub u32);
3677 impl Ifcr { 3025 impl Memrmp {
3678 #[doc = "Channel 1 Global interrupt clear"] 3026 #[doc = "Memory mapping selection"]
3679 pub fn cgif(&self, n: usize) -> bool { 3027 pub const fn mem_mode(&self) -> u8 {
3680 assert!(n < 7usize); 3028 let val = (self.0 >> 0usize) & 0x07;
3681 let offs = 0usize + n * 4usize; 3029 val as u8
3682 let val = (self.0 >> offs) & 0x01;
3683 val != 0
3684 }
3685 #[doc = "Channel 1 Global interrupt clear"]
3686 pub fn set_cgif(&mut self, n: usize, val: bool) {
3687 assert!(n < 7usize);
3688 let offs = 0usize + n * 4usize;
3689 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3690 }
3691 #[doc = "Channel 1 Transfer Complete clear"]
3692 pub fn ctcif(&self, n: usize) -> bool {
3693 assert!(n < 7usize);
3694 let offs = 1usize + n * 4usize;
3695 let val = (self.0 >> offs) & 0x01;
3696 val != 0
3697 } 3030 }
3698 #[doc = "Channel 1 Transfer Complete clear"] 3031 #[doc = "Memory mapping selection"]
3699 pub fn set_ctcif(&mut self, n: usize, val: bool) { 3032 pub fn set_mem_mode(&mut self, val: u8) {
3700 assert!(n < 7usize); 3033 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
3701 let offs = 1usize + n * 4usize;
3702 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3703 } 3034 }
3704 #[doc = "Channel 1 Half Transfer clear"] 3035 #[doc = "QUADSPI memory mapping swap"]
3705 pub fn chtif(&self, n: usize) -> bool { 3036 pub const fn qfs(&self) -> bool {
3706 assert!(n < 7usize); 3037 let val = (self.0 >> 3usize) & 0x01;
3707 let offs = 2usize + n * 4usize;
3708 let val = (self.0 >> offs) & 0x01;
3709 val != 0 3038 val != 0
3710 } 3039 }
3711 #[doc = "Channel 1 Half Transfer clear"] 3040 #[doc = "QUADSPI memory mapping swap"]
3712 pub fn set_chtif(&mut self, n: usize, val: bool) { 3041 pub fn set_qfs(&mut self, val: bool) {
3713 assert!(n < 7usize); 3042 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
3714 let offs = 2usize + n * 4usize;
3715 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3716 } 3043 }
3717 #[doc = "Channel 1 Transfer Error clear"] 3044 #[doc = "Flash Bank mode selection"]
3718 pub fn cteif(&self, n: usize) -> bool { 3045 pub const fn fb_mode(&self) -> bool {
3719 assert!(n < 7usize); 3046 let val = (self.0 >> 8usize) & 0x01;
3720 let offs = 3usize + n * 4usize;
3721 let val = (self.0 >> offs) & 0x01;
3722 val != 0 3047 val != 0
3723 } 3048 }
3724 #[doc = "Channel 1 Transfer Error clear"] 3049 #[doc = "Flash Bank mode selection"]
3725 pub fn set_cteif(&mut self, n: usize, val: bool) { 3050 pub fn set_fb_mode(&mut self, val: bool) {
3726 assert!(n < 7usize); 3051 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
3727 let offs = 3usize + n * 4usize;
3728 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3729 } 3052 }
3730 } 3053 }
3731 impl Default for Ifcr { 3054 impl Default for Memrmp {
3732 fn default() -> Ifcr { 3055 fn default() -> Memrmp {
3733 Ifcr(0) 3056 Memrmp(0)
3734 } 3057 }
3735 } 3058 }
3736 #[doc = "DMA channel configuration register (DMA_CCR)"] 3059 #[doc = "configuration register 1"]
3737 #[repr(transparent)] 3060 #[repr(transparent)]
3738 #[derive(Copy, Clone, Eq, PartialEq)] 3061 #[derive(Copy, Clone, Eq, PartialEq)]
3739 pub struct Cr(pub u32); 3062 pub struct Cfgr1(pub u32);
3740 impl Cr { 3063 impl Cfgr1 {
3741 #[doc = "Channel enable"] 3064 #[doc = "Firewall disable"]
3742 pub const fn en(&self) -> bool { 3065 pub const fn fwdis(&self) -> bool {
3743 let val = (self.0 >> 0usize) & 0x01; 3066 let val = (self.0 >> 0usize) & 0x01;
3744 val != 0 3067 val != 0
3745 } 3068 }
3746 #[doc = "Channel enable"] 3069 #[doc = "Firewall disable"]
3747 pub fn set_en(&mut self, val: bool) { 3070 pub fn set_fwdis(&mut self, val: bool) {
3748 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 3071 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3749 } 3072 }
3750 #[doc = "Transfer complete interrupt enable"] 3073 #[doc = "I/O analog switch voltage booster enable"]
3751 pub const fn tcie(&self) -> bool { 3074 pub const fn boosten(&self) -> bool {
3752 let val = (self.0 >> 1usize) & 0x01; 3075 let val = (self.0 >> 8usize) & 0x01;
3753 val != 0 3076 val != 0
3754 } 3077 }
3755 #[doc = "Transfer complete interrupt enable"] 3078 #[doc = "I/O analog switch voltage booster enable"]
3756 pub fn set_tcie(&mut self, val: bool) { 3079 pub fn set_boosten(&mut self, val: bool) {
3757 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); 3080 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
3758 } 3081 }
3759 #[doc = "Half Transfer interrupt enable"] 3082 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
3760 pub const fn htie(&self) -> bool { 3083 pub const fn i2c_pb6_fmp(&self) -> bool {
3761 let val = (self.0 >> 2usize) & 0x01; 3084 let val = (self.0 >> 16usize) & 0x01;
3762 val != 0 3085 val != 0
3763 } 3086 }
3764 #[doc = "Half Transfer interrupt enable"] 3087 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
3765 pub fn set_htie(&mut self, val: bool) { 3088 pub fn set_i2c_pb6_fmp(&mut self, val: bool) {
3766 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); 3089 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
3767 } 3090 }
3768 #[doc = "Transfer error interrupt enable"] 3091 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
3769 pub const fn teie(&self) -> bool { 3092 pub const fn i2c_pb7_fmp(&self) -> bool {
3770 let val = (self.0 >> 3usize) & 0x01; 3093 let val = (self.0 >> 17usize) & 0x01;
3771 val != 0 3094 val != 0
3772 } 3095 }
3773 #[doc = "Transfer error interrupt enable"] 3096 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
3774 pub fn set_teie(&mut self, val: bool) { 3097 pub fn set_i2c_pb7_fmp(&mut self, val: bool) {
3775 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); 3098 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
3776 }
3777 #[doc = "Data transfer direction"]
3778 pub const fn dir(&self) -> super::vals::Dir {
3779 let val = (self.0 >> 4usize) & 0x01;
3780 super::vals::Dir(val as u8)
3781 }
3782 #[doc = "Data transfer direction"]
3783 pub fn set_dir(&mut self, val: super::vals::Dir) {
3784 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
3785 }
3786 #[doc = "Circular mode"]
3787 pub const fn circ(&self) -> super::vals::Circ {
3788 let val = (self.0 >> 5usize) & 0x01;
3789 super::vals::Circ(val as u8)
3790 }
3791 #[doc = "Circular mode"]
3792 pub fn set_circ(&mut self, val: super::vals::Circ) {
3793 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
3794 }
3795 #[doc = "Peripheral increment mode"]
3796 pub const fn pinc(&self) -> super::vals::Inc {
3797 let val = (self.0 >> 6usize) & 0x01;
3798 super::vals::Inc(val as u8)
3799 }
3800 #[doc = "Peripheral increment mode"]
3801 pub fn set_pinc(&mut self, val: super::vals::Inc) {
3802 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
3803 }
3804 #[doc = "Memory increment mode"]
3805 pub const fn minc(&self) -> super::vals::Inc {
3806 let val = (self.0 >> 7usize) & 0x01;
3807 super::vals::Inc(val as u8)
3808 }
3809 #[doc = "Memory increment mode"]
3810 pub fn set_minc(&mut self, val: super::vals::Inc) {
3811 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
3812 }
3813 #[doc = "Peripheral size"]
3814 pub const fn psize(&self) -> super::vals::Size {
3815 let val = (self.0 >> 8usize) & 0x03;
3816 super::vals::Size(val as u8)
3817 }
3818 #[doc = "Peripheral size"]
3819 pub fn set_psize(&mut self, val: super::vals::Size) {
3820 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
3821 }
3822 #[doc = "Memory size"]
3823 pub const fn msize(&self) -> super::vals::Size {
3824 let val = (self.0 >> 10usize) & 0x03;
3825 super::vals::Size(val as u8)
3826 }
3827 #[doc = "Memory size"]
3828 pub fn set_msize(&mut self, val: super::vals::Size) {
3829 self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize);
3830 }
3831 #[doc = "Channel Priority level"]
3832 pub const fn pl(&self) -> super::vals::Pl {
3833 let val = (self.0 >> 12usize) & 0x03;
3834 super::vals::Pl(val as u8)
3835 }
3836 #[doc = "Channel Priority level"]
3837 pub fn set_pl(&mut self, val: super::vals::Pl) {
3838 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
3839 }
3840 #[doc = "Memory to memory mode"]
3841 pub const fn mem2mem(&self) -> super::vals::Memmem {
3842 let val = (self.0 >> 14usize) & 0x01;
3843 super::vals::Memmem(val as u8)
3844 }
3845 #[doc = "Memory to memory mode"]
3846 pub fn set_mem2mem(&mut self, val: super::vals::Memmem) {
3847 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
3848 } 3099 }
3849 } 3100 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
3850 impl Default for Cr { 3101 pub const fn i2c_pb8_fmp(&self) -> bool {
3851 fn default() -> Cr { 3102 let val = (self.0 >> 18usize) & 0x01;
3852 Cr(0) 3103 val != 0
3853 } 3104 }
3854 } 3105 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
3855 #[doc = "DMA channel 1 number of data register"] 3106 pub fn set_i2c_pb8_fmp(&mut self, val: bool) {
3856 #[repr(transparent)] 3107 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
3857 #[derive(Copy, Clone, Eq, PartialEq)]
3858 pub struct Ndtr(pub u32);
3859 impl Ndtr {
3860 #[doc = "Number of data to transfer"]
3861 pub const fn ndt(&self) -> u16 {
3862 let val = (self.0 >> 0usize) & 0xffff;
3863 val as u16
3864 } 3108 }
3865 #[doc = "Number of data to transfer"] 3109 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
3866 pub fn set_ndt(&mut self, val: u16) { 3110 pub const fn i2c_pb9_fmp(&self) -> bool {
3867 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); 3111 let val = (self.0 >> 19usize) & 0x01;
3112 val != 0
3868 } 3113 }
3869 } 3114 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
3870 impl Default for Ndtr { 3115 pub fn set_i2c_pb9_fmp(&mut self, val: bool) {
3871 fn default() -> Ndtr { 3116 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
3872 Ndtr(0)
3873 } 3117 }
3874 } 3118 #[doc = "I2C1 Fast-mode Plus driving capability activation"]
3875 #[doc = "DMA interrupt status register (DMA_ISR)"] 3119 pub const fn i2c1_fmp(&self) -> bool {
3876 #[repr(transparent)] 3120 let val = (self.0 >> 20usize) & 0x01;
3877 #[derive(Copy, Clone, Eq, PartialEq)]
3878 pub struct Isr(pub u32);
3879 impl Isr {
3880 #[doc = "Channel 1 Global interrupt flag"]
3881 pub fn gif(&self, n: usize) -> bool {
3882 assert!(n < 7usize);
3883 let offs = 0usize + n * 4usize;
3884 let val = (self.0 >> offs) & 0x01;
3885 val != 0 3121 val != 0
3886 } 3122 }
3887 #[doc = "Channel 1 Global interrupt flag"] 3123 #[doc = "I2C1 Fast-mode Plus driving capability activation"]
3888 pub fn set_gif(&mut self, n: usize, val: bool) { 3124 pub fn set_i2c1_fmp(&mut self, val: bool) {
3889 assert!(n < 7usize); 3125 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
3890 let offs = 0usize + n * 4usize;
3891 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3892 } 3126 }
3893 #[doc = "Channel 1 Transfer Complete flag"] 3127 #[doc = "I2C2 Fast-mode Plus driving capability activation"]
3894 pub fn tcif(&self, n: usize) -> bool { 3128 pub const fn i2c2_fmp(&self) -> bool {
3895 assert!(n < 7usize); 3129 let val = (self.0 >> 21usize) & 0x01;
3896 let offs = 1usize + n * 4usize;
3897 let val = (self.0 >> offs) & 0x01;
3898 val != 0 3130 val != 0
3899 } 3131 }
3900 #[doc = "Channel 1 Transfer Complete flag"] 3132 #[doc = "I2C2 Fast-mode Plus driving capability activation"]
3901 pub fn set_tcif(&mut self, n: usize, val: bool) { 3133 pub fn set_i2c2_fmp(&mut self, val: bool) {
3902 assert!(n < 7usize); 3134 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
3903 let offs = 1usize + n * 4usize;
3904 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3905 } 3135 }
3906 #[doc = "Channel 1 Half Transfer Complete flag"] 3136 #[doc = "I2C3 Fast-mode Plus driving capability activation"]
3907 pub fn htif(&self, n: usize) -> bool { 3137 pub const fn i2c3_fmp(&self) -> bool {
3908 assert!(n < 7usize); 3138 let val = (self.0 >> 22usize) & 0x01;
3909 let offs = 2usize + n * 4usize;
3910 let val = (self.0 >> offs) & 0x01;
3911 val != 0 3139 val != 0
3912 } 3140 }
3913 #[doc = "Channel 1 Half Transfer Complete flag"] 3141 #[doc = "I2C3 Fast-mode Plus driving capability activation"]
3914 pub fn set_htif(&mut self, n: usize, val: bool) { 3142 pub fn set_i2c3_fmp(&mut self, val: bool) {
3915 assert!(n < 7usize); 3143 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
3916 let offs = 2usize + n * 4usize;
3917 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3918 } 3144 }
3919 #[doc = "Channel 1 Transfer Error flag"] 3145 #[doc = "Floating Point Unit interrupts enable bits"]
3920 pub fn teif(&self, n: usize) -> bool { 3146 pub const fn fpu_ie(&self) -> u8 {
3921 assert!(n < 7usize); 3147 let val = (self.0 >> 26usize) & 0x3f;
3922 let offs = 3usize + n * 4usize; 3148 val as u8
3923 let val = (self.0 >> offs) & 0x01;
3924 val != 0
3925 } 3149 }
3926 #[doc = "Channel 1 Transfer Error flag"] 3150 #[doc = "Floating Point Unit interrupts enable bits"]
3927 pub fn set_teif(&mut self, n: usize, val: bool) { 3151 pub fn set_fpu_ie(&mut self, val: u8) {
3928 assert!(n < 7usize); 3152 self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize);
3929 let offs = 3usize + n * 4usize;
3930 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3931 } 3153 }
3932 } 3154 }
3933 impl Default for Isr { 3155 impl Default for Cfgr1 {
3934 fn default() -> Isr { 3156 fn default() -> Cfgr1 {
3935 Isr(0) 3157 Cfgr1(0)
3936 } 3158 }
3937 } 3159 }
3938 } 3160 #[doc = "CFGR2"]
3939}
3940pub mod rng_v1 {
3941 use crate::generic::*;
3942 #[doc = "Random number generator"]
3943 #[derive(Copy, Clone)]
3944 pub struct Rng(pub *mut u8);
3945 unsafe impl Send for Rng {}
3946 unsafe impl Sync for Rng {}
3947 impl Rng {
3948 #[doc = "control register"]
3949 pub fn cr(self) -> Reg<regs::Cr, RW> {
3950 unsafe { Reg::from_ptr(self.0.add(0usize)) }
3951 }
3952 #[doc = "status register"]
3953 pub fn sr(self) -> Reg<regs::Sr, RW> {
3954 unsafe { Reg::from_ptr(self.0.add(4usize)) }
3955 }
3956 #[doc = "data register"]
3957 pub fn dr(self) -> Reg<u32, R> {
3958 unsafe { Reg::from_ptr(self.0.add(8usize)) }
3959 }
3960 }
3961 pub mod regs {
3962 use crate::generic::*;
3963 #[doc = "status register"]
3964 #[repr(transparent)] 3161 #[repr(transparent)]
3965 #[derive(Copy, Clone, Eq, PartialEq)] 3162 #[derive(Copy, Clone, Eq, PartialEq)]
3966 pub struct Sr(pub u32); 3163 pub struct Cfgr2(pub u32);
3967 impl Sr { 3164 impl Cfgr2 {
3968 #[doc = "Data ready"] 3165 #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
3969 pub const fn drdy(&self) -> bool { 3166 pub const fn cll(&self) -> bool {
3970 let val = (self.0 >> 0usize) & 0x01; 3167 let val = (self.0 >> 0usize) & 0x01;
3971 val != 0 3168 val != 0
3972 } 3169 }
3973 #[doc = "Data ready"] 3170 #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
3974 pub fn set_drdy(&mut self, val: bool) { 3171 pub fn set_cll(&mut self, val: bool) {
3975 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 3172 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3976 } 3173 }
3977 #[doc = "Clock error current status"] 3174 #[doc = "SRAM2 parity lock bit"]
3978 pub const fn cecs(&self) -> bool { 3175 pub const fn spl(&self) -> bool {
3979 let val = (self.0 >> 1usize) & 0x01; 3176 let val = (self.0 >> 1usize) & 0x01;
3980 val != 0 3177 val != 0
3981 } 3178 }
3982 #[doc = "Clock error current status"] 3179 #[doc = "SRAM2 parity lock bit"]
3983 pub fn set_cecs(&mut self, val: bool) { 3180 pub fn set_spl(&mut self, val: bool) {
3984 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); 3181 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3985 } 3182 }
3986 #[doc = "Seed error current status"] 3183 #[doc = "PVD lock enable bit"]
3987 pub const fn secs(&self) -> bool { 3184 pub const fn pvdl(&self) -> bool {
3988 let val = (self.0 >> 2usize) & 0x01; 3185 let val = (self.0 >> 2usize) & 0x01;
3989 val != 0 3186 val != 0
3990 } 3187 }
3991 #[doc = "Seed error current status"] 3188 #[doc = "PVD lock enable bit"]
3992 pub fn set_secs(&mut self, val: bool) { 3189 pub fn set_pvdl(&mut self, val: bool) {
3993 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); 3190 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3994 } 3191 }
3995 #[doc = "Clock error interrupt status"] 3192 #[doc = "ECC Lock"]
3996 pub const fn ceis(&self) -> bool { 3193 pub const fn eccl(&self) -> bool {
3997 let val = (self.0 >> 5usize) & 0x01; 3194 let val = (self.0 >> 3usize) & 0x01;
3998 val != 0
3999 }
4000 #[doc = "Clock error interrupt status"]
4001 pub fn set_ceis(&mut self, val: bool) {
4002 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
4003 }
4004 #[doc = "Seed error interrupt status"]
4005 pub const fn seis(&self) -> bool {
4006 let val = (self.0 >> 6usize) & 0x01;
4007 val != 0
4008 }
4009 #[doc = "Seed error interrupt status"]
4010 pub fn set_seis(&mut self, val: bool) {
4011 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
4012 }
4013 }
4014 impl Default for Sr {
4015 fn default() -> Sr {
4016 Sr(0)
4017 }
4018 }
4019 #[doc = "control register"]
4020 #[repr(transparent)]
4021 #[derive(Copy, Clone, Eq, PartialEq)]
4022 pub struct Cr(pub u32);
4023 impl Cr {
4024 #[doc = "Random number generator enable"]
4025 pub const fn rngen(&self) -> bool {
4026 let val = (self.0 >> 2usize) & 0x01;
4027 val != 0 3195 val != 0
4028 } 3196 }
4029 #[doc = "Random number generator enable"] 3197 #[doc = "ECC Lock"]
4030 pub fn set_rngen(&mut self, val: bool) { 3198 pub fn set_eccl(&mut self, val: bool) {
4031 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); 3199 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
4032 } 3200 }
4033 #[doc = "Interrupt enable"] 3201 #[doc = "SRAM2 parity error flag"]
4034 pub const fn ie(&self) -> bool { 3202 pub const fn spf(&self) -> bool {
4035 let val = (self.0 >> 3usize) & 0x01; 3203 let val = (self.0 >> 8usize) & 0x01;
4036 val != 0 3204 val != 0
4037 } 3205 }
4038 #[doc = "Interrupt enable"] 3206 #[doc = "SRAM2 parity error flag"]
4039 pub fn set_ie(&mut self, val: bool) { 3207 pub fn set_spf(&mut self, val: bool) {
4040 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); 3208 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
4041 } 3209 }
4042 } 3210 }
4043 impl Default for Cr { 3211 impl Default for Cfgr2 {
4044 fn default() -> Cr { 3212 fn default() -> Cfgr2 {
4045 Cr(0) 3213 Cfgr2(0)
4046 } 3214 }
4047 } 3215 }
4048 } 3216 }
4049} 3217}
4050pub mod exti_v1 { 3218pub mod gpio_v1 {
4051 use crate::generic::*; 3219 use crate::generic::*;
4052 #[doc = "External interrupt/event controller"] 3220 #[doc = "General purpose I/O"]
4053 #[derive(Copy, Clone)] 3221 #[derive(Copy, Clone)]
4054 pub struct Exti(pub *mut u8); 3222 pub struct Gpio(pub *mut u8);
4055 unsafe impl Send for Exti {} 3223 unsafe impl Send for Gpio {}
4056 unsafe impl Sync for Exti {} 3224 unsafe impl Sync for Gpio {}
4057 impl Exti { 3225 impl Gpio {
4058 #[doc = "Interrupt mask register (EXTI_IMR)"] 3226 #[doc = "Port configuration register low (GPIOn_CRL)"]
4059 pub fn imr(self) -> Reg<regs::Imr, RW> { 3227 pub fn cr(self, n: usize) -> Reg<regs::Cr, RW> {
4060 unsafe { Reg::from_ptr(self.0.add(0usize)) } 3228 assert!(n < 2usize);
4061 } 3229 unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
4062 #[doc = "Event mask register (EXTI_EMR)"]
4063 pub fn emr(self) -> Reg<regs::Emr, RW> {
4064 unsafe { Reg::from_ptr(self.0.add(4usize)) }
4065 } 3230 }
4066 #[doc = "Rising Trigger selection register (EXTI_RTSR)"] 3231 #[doc = "Port input data register (GPIOn_IDR)"]
4067 pub fn rtsr(self) -> Reg<regs::Rtsr, RW> { 3232 pub fn idr(self) -> Reg<regs::Idr, R> {
4068 unsafe { Reg::from_ptr(self.0.add(8usize)) } 3233 unsafe { Reg::from_ptr(self.0.add(8usize)) }
4069 } 3234 }
4070 #[doc = "Falling Trigger selection register (EXTI_FTSR)"] 3235 #[doc = "Port output data register (GPIOn_ODR)"]
4071 pub fn ftsr(self) -> Reg<regs::Ftsr, RW> { 3236 pub fn odr(self) -> Reg<regs::Odr, RW> {
4072 unsafe { Reg::from_ptr(self.0.add(12usize)) } 3237 unsafe { Reg::from_ptr(self.0.add(12usize)) }
4073 } 3238 }
4074 #[doc = "Software interrupt event register (EXTI_SWIER)"] 3239 #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
4075 pub fn swier(self) -> Reg<regs::Swier, RW> { 3240 pub fn bsrr(self) -> Reg<regs::Bsrr, W> {
4076 unsafe { Reg::from_ptr(self.0.add(16usize)) } 3241 unsafe { Reg::from_ptr(self.0.add(16usize)) }
4077 } 3242 }
4078 #[doc = "Pending register (EXTI_PR)"] 3243 #[doc = "Port bit reset register (GPIOn_BRR)"]
4079 pub fn pr(self) -> Reg<regs::Pr, RW> { 3244 pub fn brr(self) -> Reg<regs::Brr, W> {
4080 unsafe { Reg::from_ptr(self.0.add(20usize)) } 3245 unsafe { Reg::from_ptr(self.0.add(20usize)) }
4081 } 3246 }
3247 #[doc = "Port configuration lock register"]
3248 pub fn lckr(self) -> Reg<regs::Lckr, RW> {
3249 unsafe { Reg::from_ptr(self.0.add(24usize)) }
3250 }
4082 } 3251 }
4083 pub mod regs { 3252 pub mod regs {
4084 use crate::generic::*; 3253 use crate::generic::*;
4085 #[doc = "Software interrupt event register (EXTI_SWIER)"] 3254 #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
4086 #[repr(transparent)] 3255 #[repr(transparent)]
4087 #[derive(Copy, Clone, Eq, PartialEq)] 3256 #[derive(Copy, Clone, Eq, PartialEq)]
4088 pub struct Swier(pub u32); 3257 pub struct Bsrr(pub u32);
4089 impl Swier { 3258 impl Bsrr {
4090 #[doc = "Software Interrupt on line 0"] 3259 #[doc = "Set bit"]
4091 pub fn swier(&self, n: usize) -> bool { 3260 pub fn bs(&self, n: usize) -> bool {
4092 assert!(n < 23usize); 3261 assert!(n < 16usize);
4093 let offs = 0usize + n * 1usize; 3262 let offs = 0usize + n * 1usize;
4094 let val = (self.0 >> offs) & 0x01; 3263 let val = (self.0 >> offs) & 0x01;
4095 val != 0 3264 val != 0
4096 } 3265 }
4097 #[doc = "Software Interrupt on line 0"] 3266 #[doc = "Set bit"]
4098 pub fn set_swier(&mut self, n: usize, val: bool) { 3267 pub fn set_bs(&mut self, n: usize, val: bool) {
4099 assert!(n < 23usize); 3268 assert!(n < 16usize);
4100 let offs = 0usize + n * 1usize; 3269 let offs = 0usize + n * 1usize;
4101 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); 3270 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4102 } 3271 }
3272 #[doc = "Reset bit"]
3273 pub fn br(&self, n: usize) -> bool {
3274 assert!(n < 16usize);
3275 let offs = 16usize + n * 1usize;
3276 let val = (self.0 >> offs) & 0x01;
3277 val != 0
3278 }
3279 #[doc = "Reset bit"]
3280 pub fn set_br(&mut self, n: usize, val: bool) {
3281 assert!(n < 16usize);
3282 let offs = 16usize + n * 1usize;
3283 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3284 }
4103 } 3285 }
4104 impl Default for Swier { 3286 impl Default for Bsrr {
4105 fn default() -> Swier { 3287 fn default() -> Bsrr {
4106 Swier(0) 3288 Bsrr(0)
4107 } 3289 }
4108 } 3290 }
4109 #[doc = "Pending register (EXTI_PR)"] 3291 #[doc = "Port configuration lock register"]
4110 #[repr(transparent)] 3292 #[repr(transparent)]
4111 #[derive(Copy, Clone, Eq, PartialEq)] 3293 #[derive(Copy, Clone, Eq, PartialEq)]
4112 pub struct Pr(pub u32); 3294 pub struct Lckr(pub u32);
4113 impl Pr { 3295 impl Lckr {
4114 #[doc = "Pending bit 0"] 3296 #[doc = "Port A Lock bit"]
4115 pub fn pr(&self, n: usize) -> bool { 3297 pub fn lck(&self, n: usize) -> super::vals::Lck {
4116 assert!(n < 23usize); 3298 assert!(n < 16usize);
4117 let offs = 0usize + n * 1usize; 3299 let offs = 0usize + n * 1usize;
4118 let val = (self.0 >> offs) & 0x01; 3300 let val = (self.0 >> offs) & 0x01;
4119 val != 0 3301 super::vals::Lck(val as u8)
4120 } 3302 }
4121 #[doc = "Pending bit 0"] 3303 #[doc = "Port A Lock bit"]
4122 pub fn set_pr(&mut self, n: usize, val: bool) { 3304 pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) {
4123 assert!(n < 23usize); 3305 assert!(n < 16usize);
4124 let offs = 0usize + n * 1usize; 3306 let offs = 0usize + n * 1usize;
4125 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); 3307 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
3308 }
3309 #[doc = "Lock key"]
3310 pub const fn lckk(&self) -> super::vals::Lckk {
3311 let val = (self.0 >> 16usize) & 0x01;
3312 super::vals::Lckk(val as u8)
3313 }
3314 #[doc = "Lock key"]
3315 pub fn set_lckk(&mut self, val: super::vals::Lckk) {
3316 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
4126 } 3317 }
4127 } 3318 }
4128 impl Default for Pr { 3319 impl Default for Lckr {
4129 fn default() -> Pr { 3320 fn default() -> Lckr {
4130 Pr(0) 3321 Lckr(0)
4131 } 3322 }
4132 } 3323 }
4133 #[doc = "Falling Trigger selection register (EXTI_FTSR)"] 3324 #[doc = "Port output data register (GPIOn_ODR)"]
4134 #[repr(transparent)] 3325 #[repr(transparent)]
4135 #[derive(Copy, Clone, Eq, PartialEq)] 3326 #[derive(Copy, Clone, Eq, PartialEq)]
4136 pub struct Ftsr(pub u32); 3327 pub struct Odr(pub u32);
4137 impl Ftsr { 3328 impl Odr {
4138 #[doc = "Falling trigger event configuration of line 0"] 3329 #[doc = "Port output data"]
4139 pub fn tr(&self, n: usize) -> super::vals::Tr { 3330 pub fn odr(&self, n: usize) -> super::vals::Odr {
4140 assert!(n < 23usize); 3331 assert!(n < 16usize);
4141 let offs = 0usize + n * 1usize; 3332 let offs = 0usize + n * 1usize;
4142 let val = (self.0 >> offs) & 0x01; 3333 let val = (self.0 >> offs) & 0x01;
4143 super::vals::Tr(val as u8) 3334 super::vals::Odr(val as u8)
4144 } 3335 }
4145 #[doc = "Falling trigger event configuration of line 0"] 3336 #[doc = "Port output data"]
4146 pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { 3337 pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) {
4147 assert!(n < 23usize); 3338 assert!(n < 16usize);
4148 let offs = 0usize + n * 1usize; 3339 let offs = 0usize + n * 1usize;
4149 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); 3340 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
4150 } 3341 }
4151 } 3342 }
4152 impl Default for Ftsr { 3343 impl Default for Odr {
4153 fn default() -> Ftsr { 3344 fn default() -> Odr {
4154 Ftsr(0) 3345 Odr(0)
4155 } 3346 }
4156 } 3347 }
4157 #[doc = "Event mask register (EXTI_EMR)"] 3348 #[doc = "Port configuration register (GPIOn_CRx)"]
4158 #[repr(transparent)] 3349 #[repr(transparent)]
4159 #[derive(Copy, Clone, Eq, PartialEq)] 3350 #[derive(Copy, Clone, Eq, PartialEq)]
4160 pub struct Emr(pub u32); 3351 pub struct Cr(pub u32);
4161 impl Emr { 3352 impl Cr {
4162 #[doc = "Event Mask on line 0"] 3353 #[doc = "Port n mode bits"]
4163 pub fn mr(&self, n: usize) -> super::vals::Mr { 3354 pub fn mode(&self, n: usize) -> super::vals::Mode {
4164 assert!(n < 23usize); 3355 assert!(n < 8usize);
4165 let offs = 0usize + n * 1usize; 3356 let offs = 0usize + n * 4usize;
4166 let val = (self.0 >> offs) & 0x01; 3357 let val = (self.0 >> offs) & 0x03;
4167 super::vals::Mr(val as u8) 3358 super::vals::Mode(val as u8)
4168 } 3359 }
4169 #[doc = "Event Mask on line 0"] 3360 #[doc = "Port n mode bits"]
4170 pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { 3361 pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) {
4171 assert!(n < 23usize); 3362 assert!(n < 8usize);
4172 let offs = 0usize + n * 1usize; 3363 let offs = 0usize + n * 4usize;
4173 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); 3364 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
3365 }
3366 #[doc = "Port n configuration bits"]
3367 pub fn cnf(&self, n: usize) -> super::vals::Cnf {
3368 assert!(n < 8usize);
3369 let offs = 2usize + n * 4usize;
3370 let val = (self.0 >> offs) & 0x03;
3371 super::vals::Cnf(val as u8)
3372 }
3373 #[doc = "Port n configuration bits"]
3374 pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) {
3375 assert!(n < 8usize);
3376 let offs = 2usize + n * 4usize;
3377 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
4174 } 3378 }
4175 } 3379 }
4176 impl Default for Emr { 3380 impl Default for Cr {
4177 fn default() -> Emr { 3381 fn default() -> Cr {
4178 Emr(0) 3382 Cr(0)
4179 } 3383 }
4180 } 3384 }
4181 #[doc = "Interrupt mask register (EXTI_IMR)"] 3385 #[doc = "Port bit reset register (GPIOn_BRR)"]
4182 #[repr(transparent)] 3386 #[repr(transparent)]
4183 #[derive(Copy, Clone, Eq, PartialEq)] 3387 #[derive(Copy, Clone, Eq, PartialEq)]
4184 pub struct Imr(pub u32); 3388 pub struct Brr(pub u32);
4185 impl Imr { 3389 impl Brr {
4186 #[doc = "Interrupt Mask on line 0"] 3390 #[doc = "Reset bit"]
4187 pub fn mr(&self, n: usize) -> super::vals::Mr { 3391 pub fn br(&self, n: usize) -> bool {
4188 assert!(n < 23usize); 3392 assert!(n < 16usize);
4189 let offs = 0usize + n * 1usize; 3393 let offs = 0usize + n * 1usize;
4190 let val = (self.0 >> offs) & 0x01; 3394 let val = (self.0 >> offs) & 0x01;
4191 super::vals::Mr(val as u8) 3395 val != 0
4192 } 3396 }
4193 #[doc = "Interrupt Mask on line 0"] 3397 #[doc = "Reset bit"]
4194 pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { 3398 pub fn set_br(&mut self, n: usize, val: bool) {
4195 assert!(n < 23usize); 3399 assert!(n < 16usize);
4196 let offs = 0usize + n * 1usize; 3400 let offs = 0usize + n * 1usize;
4197 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); 3401 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4198 } 3402 }
4199 } 3403 }
4200 impl Default for Imr { 3404 impl Default for Brr {
4201 fn default() -> Imr { 3405 fn default() -> Brr {
4202 Imr(0) 3406 Brr(0)
4203 } 3407 }
4204 } 3408 }
4205 #[doc = "Rising Trigger selection register (EXTI_RTSR)"] 3409 #[doc = "Port input data register (GPIOn_IDR)"]
4206 #[repr(transparent)] 3410 #[repr(transparent)]
4207 #[derive(Copy, Clone, Eq, PartialEq)] 3411 #[derive(Copy, Clone, Eq, PartialEq)]
4208 pub struct Rtsr(pub u32); 3412 pub struct Idr(pub u32);
4209 impl Rtsr { 3413 impl Idr {
4210 #[doc = "Rising trigger event configuration of line 0"] 3414 #[doc = "Port input data"]
4211 pub fn tr(&self, n: usize) -> super::vals::Tr { 3415 pub fn idr(&self, n: usize) -> super::vals::Idr {
4212 assert!(n < 23usize); 3416 assert!(n < 16usize);
4213 let offs = 0usize + n * 1usize; 3417 let offs = 0usize + n * 1usize;
4214 let val = (self.0 >> offs) & 0x01; 3418 let val = (self.0 >> offs) & 0x01;
4215 super::vals::Tr(val as u8) 3419 super::vals::Idr(val as u8)
4216 } 3420 }
4217 #[doc = "Rising trigger event configuration of line 0"] 3421 #[doc = "Port input data"]
4218 pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { 3422 pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) {
4219 assert!(n < 23usize); 3423 assert!(n < 16usize);
4220 let offs = 0usize + n * 1usize; 3424 let offs = 0usize + n * 1usize;
4221 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); 3425 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
4222 } 3426 }
4223 } 3427 }
4224 impl Default for Rtsr { 3428 impl Default for Idr {
4225 fn default() -> Rtsr { 3429 fn default() -> Idr {
4226 Rtsr(0) 3430 Idr(0)
4227 } 3431 }
4228 } 3432 }
4229 } 3433 }
@@ -4231,389 +3435,94 @@ pub mod exti_v1 {
4231 use crate::generic::*; 3435 use crate::generic::*;
4232 #[repr(transparent)] 3436 #[repr(transparent)]
4233 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 3437 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4234 pub struct Prw(pub u8); 3438 pub struct Lckk(pub u8);
4235 impl Prw { 3439 impl Lckk {
4236 #[doc = "Clears pending bit"] 3440 #[doc = "Port configuration lock key not active"]
4237 pub const CLEAR: Self = Self(0x01); 3441 pub const NOTACTIVE: Self = Self(0);
3442 #[doc = "Port configuration lock key active"]
3443 pub const ACTIVE: Self = Self(0x01);
4238 } 3444 }
4239 #[repr(transparent)] 3445 #[repr(transparent)]
4240 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 3446 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4241 pub struct Swierw(pub u8); 3447 pub struct Odr(pub u8);
4242 impl Swierw { 3448 impl Odr {
4243 #[doc = "Generates an interrupt request"] 3449 #[doc = "Set output to logic low"]
4244 pub const PEND: Self = Self(0x01); 3450 pub const LOW: Self = Self(0);
3451 #[doc = "Set output to logic high"]
3452 pub const HIGH: Self = Self(0x01);
4245 } 3453 }
4246 #[repr(transparent)] 3454 #[repr(transparent)]
4247 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 3455 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4248 pub struct Mr(pub u8); 3456 pub struct Lck(pub u8);
4249 impl Mr { 3457 impl Lck {
4250 #[doc = "Interrupt request line is masked"] 3458 #[doc = "Port configuration not locked"]
4251 pub const MASKED: Self = Self(0); 3459 pub const UNLOCKED: Self = Self(0);
4252 #[doc = "Interrupt request line is unmasked"] 3460 #[doc = "Port configuration locked"]
4253 pub const UNMASKED: Self = Self(0x01); 3461 pub const LOCKED: Self = Self(0x01);
4254 } 3462 }
4255 #[repr(transparent)] 3463 #[repr(transparent)]
4256 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 3464 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4257 pub struct Prr(pub u8); 3465 pub struct Bsw(pub u8);
4258 impl Prr { 3466 impl Bsw {
4259 #[doc = "No trigger request occurred"] 3467 #[doc = "No action on the corresponding ODx bit"]
4260 pub const NOTPENDING: Self = Self(0); 3468 pub const NOACTION: Self = Self(0);
4261 #[doc = "Selected trigger request occurred"] 3469 #[doc = "Sets the corresponding ODRx bit"]
4262 pub const PENDING: Self = Self(0x01); 3470 pub const SET: Self = Self(0x01);
4263 } 3471 }
4264 #[repr(transparent)] 3472 #[repr(transparent)]
4265 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 3473 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4266 pub struct Tr(pub u8); 3474 pub struct Brw(pub u8);
4267 impl Tr { 3475 impl Brw {
4268 #[doc = "Falling edge trigger is disabled"] 3476 #[doc = "No action on the corresponding ODx bit"]
4269 pub const DISABLED: Self = Self(0); 3477 pub const NOACTION: Self = Self(0);
4270 #[doc = "Falling edge trigger is enabled"] 3478 #[doc = "Reset the ODx bit"]
4271 pub const ENABLED: Self = Self(0x01); 3479 pub const RESET: Self = Self(0x01);
4272 }
4273 }
4274}
4275pub mod syscfg_l4 {
4276 use crate::generic::*;
4277 #[doc = "System configuration controller"]
4278 #[derive(Copy, Clone)]
4279 pub struct Syscfg(pub *mut u8);
4280 unsafe impl Send for Syscfg {}
4281 unsafe impl Sync for Syscfg {}
4282 impl Syscfg {
4283 #[doc = "memory remap register"]
4284 pub fn memrmp(self) -> Reg<regs::Memrmp, RW> {
4285 unsafe { Reg::from_ptr(self.0.add(0usize)) }
4286 }
4287 #[doc = "configuration register 1"]
4288 pub fn cfgr1(self) -> Reg<regs::Cfgr1, RW> {
4289 unsafe { Reg::from_ptr(self.0.add(4usize)) }
4290 }
4291 #[doc = "external interrupt configuration register 1"]
4292 pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
4293 assert!(n < 4usize);
4294 unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
4295 }
4296 #[doc = "SCSR"]
4297 pub fn scsr(self) -> Reg<regs::Scsr, RW> {
4298 unsafe { Reg::from_ptr(self.0.add(24usize)) }
4299 }
4300 #[doc = "CFGR2"]
4301 pub fn cfgr2(self) -> Reg<regs::Cfgr2, RW> {
4302 unsafe { Reg::from_ptr(self.0.add(28usize)) }
4303 }
4304 #[doc = "SWPR"]
4305 pub fn swpr(self) -> Reg<regs::Swpr, W> {
4306 unsafe { Reg::from_ptr(self.0.add(32usize)) }
4307 }
4308 #[doc = "SKR"]
4309 pub fn skr(self) -> Reg<regs::Skr, W> {
4310 unsafe { Reg::from_ptr(self.0.add(36usize)) }
4311 }
4312 }
4313 pub mod regs {
4314 use crate::generic::*;
4315 #[doc = "CFGR2"]
4316 #[repr(transparent)]
4317 #[derive(Copy, Clone, Eq, PartialEq)]
4318 pub struct Cfgr2(pub u32);
4319 impl Cfgr2 {
4320 #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
4321 pub const fn cll(&self) -> bool {
4322 let val = (self.0 >> 0usize) & 0x01;
4323 val != 0
4324 }
4325 #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
4326 pub fn set_cll(&mut self, val: bool) {
4327 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4328 }
4329 #[doc = "SRAM2 parity lock bit"]
4330 pub const fn spl(&self) -> bool {
4331 let val = (self.0 >> 1usize) & 0x01;
4332 val != 0
4333 }
4334 #[doc = "SRAM2 parity lock bit"]
4335 pub fn set_spl(&mut self, val: bool) {
4336 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4337 }
4338 #[doc = "PVD lock enable bit"]
4339 pub const fn pvdl(&self) -> bool {
4340 let val = (self.0 >> 2usize) & 0x01;
4341 val != 0
4342 }
4343 #[doc = "PVD lock enable bit"]
4344 pub fn set_pvdl(&mut self, val: bool) {
4345 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4346 }
4347 #[doc = "ECC Lock"]
4348 pub const fn eccl(&self) -> bool {
4349 let val = (self.0 >> 3usize) & 0x01;
4350 val != 0
4351 }
4352 #[doc = "ECC Lock"]
4353 pub fn set_eccl(&mut self, val: bool) {
4354 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
4355 }
4356 #[doc = "SRAM2 parity error flag"]
4357 pub const fn spf(&self) -> bool {
4358 let val = (self.0 >> 8usize) & 0x01;
4359 val != 0
4360 }
4361 #[doc = "SRAM2 parity error flag"]
4362 pub fn set_spf(&mut self, val: bool) {
4363 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
4364 }
4365 }
4366 impl Default for Cfgr2 {
4367 fn default() -> Cfgr2 {
4368 Cfgr2(0)
4369 }
4370 }
4371 #[doc = "memory remap register"]
4372 #[repr(transparent)]
4373 #[derive(Copy, Clone, Eq, PartialEq)]
4374 pub struct Memrmp(pub u32);
4375 impl Memrmp {
4376 #[doc = "Memory mapping selection"]
4377 pub const fn mem_mode(&self) -> u8 {
4378 let val = (self.0 >> 0usize) & 0x07;
4379 val as u8
4380 }
4381 #[doc = "Memory mapping selection"]
4382 pub fn set_mem_mode(&mut self, val: u8) {
4383 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
4384 }
4385 #[doc = "QUADSPI memory mapping swap"]
4386 pub const fn qfs(&self) -> bool {
4387 let val = (self.0 >> 3usize) & 0x01;
4388 val != 0
4389 }
4390 #[doc = "QUADSPI memory mapping swap"]
4391 pub fn set_qfs(&mut self, val: bool) {
4392 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
4393 }
4394 #[doc = "Flash Bank mode selection"]
4395 pub const fn fb_mode(&self) -> bool {
4396 let val = (self.0 >> 8usize) & 0x01;
4397 val != 0
4398 }
4399 #[doc = "Flash Bank mode selection"]
4400 pub fn set_fb_mode(&mut self, val: bool) {
4401 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
4402 }
4403 }
4404 impl Default for Memrmp {
4405 fn default() -> Memrmp {
4406 Memrmp(0)
4407 }
4408 }
4409 #[doc = "SCSR"]
4410 #[repr(transparent)]
4411 #[derive(Copy, Clone, Eq, PartialEq)]
4412 pub struct Scsr(pub u32);
4413 impl Scsr {
4414 #[doc = "SRAM2 Erase"]
4415 pub const fn sram2er(&self) -> bool {
4416 let val = (self.0 >> 0usize) & 0x01;
4417 val != 0
4418 }
4419 #[doc = "SRAM2 Erase"]
4420 pub fn set_sram2er(&mut self, val: bool) {
4421 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4422 }
4423 #[doc = "SRAM2 busy by erase operation"]
4424 pub const fn sram2bsy(&self) -> bool {
4425 let val = (self.0 >> 1usize) & 0x01;
4426 val != 0
4427 }
4428 #[doc = "SRAM2 busy by erase operation"]
4429 pub fn set_sram2bsy(&mut self, val: bool) {
4430 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4431 }
4432 }
4433 impl Default for Scsr {
4434 fn default() -> Scsr {
4435 Scsr(0)
4436 }
4437 }
4438 #[doc = "external interrupt configuration register 4"]
4439 #[repr(transparent)]
4440 #[derive(Copy, Clone, Eq, PartialEq)]
4441 pub struct Exticr(pub u32);
4442 impl Exticr {
4443 #[doc = "EXTI12 configuration bits"]
4444 pub fn exti(&self, n: usize) -> u8 {
4445 assert!(n < 4usize);
4446 let offs = 0usize + n * 4usize;
4447 let val = (self.0 >> offs) & 0x0f;
4448 val as u8
4449 }
4450 #[doc = "EXTI12 configuration bits"]
4451 pub fn set_exti(&mut self, n: usize, val: u8) {
4452 assert!(n < 4usize);
4453 let offs = 0usize + n * 4usize;
4454 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
4455 }
4456 }
4457 impl Default for Exticr {
4458 fn default() -> Exticr {
4459 Exticr(0)
4460 }
4461 } 3480 }
4462 #[doc = "configuration register 1"]
4463 #[repr(transparent)] 3481 #[repr(transparent)]
4464 #[derive(Copy, Clone, Eq, PartialEq)] 3482 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4465 pub struct Cfgr1(pub u32); 3483 pub struct Idr(pub u8);
4466 impl Cfgr1 { 3484 impl Idr {
4467 #[doc = "Firewall disable"] 3485 #[doc = "Input is logic low"]
4468 pub const fn fwdis(&self) -> bool { 3486 pub const LOW: Self = Self(0);
4469 let val = (self.0 >> 0usize) & 0x01; 3487 #[doc = "Input is logic high"]
4470 val != 0 3488 pub const HIGH: Self = Self(0x01);
4471 }
4472 #[doc = "Firewall disable"]
4473 pub fn set_fwdis(&mut self, val: bool) {
4474 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4475 }
4476 #[doc = "I/O analog switch voltage booster enable"]
4477 pub const fn boosten(&self) -> bool {
4478 let val = (self.0 >> 8usize) & 0x01;
4479 val != 0
4480 }
4481 #[doc = "I/O analog switch voltage booster enable"]
4482 pub fn set_boosten(&mut self, val: bool) {
4483 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
4484 }
4485 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
4486 pub const fn i2c_pb6_fmp(&self) -> bool {
4487 let val = (self.0 >> 16usize) & 0x01;
4488 val != 0
4489 }
4490 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
4491 pub fn set_i2c_pb6_fmp(&mut self, val: bool) {
4492 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
4493 }
4494 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
4495 pub const fn i2c_pb7_fmp(&self) -> bool {
4496 let val = (self.0 >> 17usize) & 0x01;
4497 val != 0
4498 }
4499 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
4500 pub fn set_i2c_pb7_fmp(&mut self, val: bool) {
4501 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
4502 }
4503 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
4504 pub const fn i2c_pb8_fmp(&self) -> bool {
4505 let val = (self.0 >> 18usize) & 0x01;
4506 val != 0
4507 }
4508 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
4509 pub fn set_i2c_pb8_fmp(&mut self, val: bool) {
4510 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
4511 }
4512 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
4513 pub const fn i2c_pb9_fmp(&self) -> bool {
4514 let val = (self.0 >> 19usize) & 0x01;
4515 val != 0
4516 }
4517 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
4518 pub fn set_i2c_pb9_fmp(&mut self, val: bool) {
4519 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
4520 }
4521 #[doc = "I2C1 Fast-mode Plus driving capability activation"]
4522 pub const fn i2c1_fmp(&self) -> bool {
4523 let val = (self.0 >> 20usize) & 0x01;
4524 val != 0
4525 }
4526 #[doc = "I2C1 Fast-mode Plus driving capability activation"]
4527 pub fn set_i2c1_fmp(&mut self, val: bool) {
4528 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
4529 }
4530 #[doc = "I2C2 Fast-mode Plus driving capability activation"]
4531 pub const fn i2c2_fmp(&self) -> bool {
4532 let val = (self.0 >> 21usize) & 0x01;
4533 val != 0
4534 }
4535 #[doc = "I2C2 Fast-mode Plus driving capability activation"]
4536 pub fn set_i2c2_fmp(&mut self, val: bool) {
4537 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
4538 }
4539 #[doc = "I2C3 Fast-mode Plus driving capability activation"]
4540 pub const fn i2c3_fmp(&self) -> bool {
4541 let val = (self.0 >> 22usize) & 0x01;
4542 val != 0
4543 }
4544 #[doc = "I2C3 Fast-mode Plus driving capability activation"]
4545 pub fn set_i2c3_fmp(&mut self, val: bool) {
4546 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
4547 }
4548 #[doc = "Floating Point Unit interrupts enable bits"]
4549 pub const fn fpu_ie(&self) -> u8 {
4550 let val = (self.0 >> 26usize) & 0x3f;
4551 val as u8
4552 }
4553 #[doc = "Floating Point Unit interrupts enable bits"]
4554 pub fn set_fpu_ie(&mut self, val: u8) {
4555 self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize);
4556 }
4557 }
4558 impl Default for Cfgr1 {
4559 fn default() -> Cfgr1 {
4560 Cfgr1(0)
4561 }
4562 } 3489 }
4563 #[doc = "SWPR"]
4564 #[repr(transparent)] 3490 #[repr(transparent)]
4565 #[derive(Copy, Clone, Eq, PartialEq)] 3491 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4566 pub struct Swpr(pub u32); 3492 pub struct Mode(pub u8);
4567 impl Swpr { 3493 impl Mode {
4568 #[doc = "SRAWM2 write protection."] 3494 #[doc = "Input mode (reset state)"]
4569 pub fn pwp(&self, n: usize) -> bool { 3495 pub const INPUT: Self = Self(0);
4570 assert!(n < 32usize); 3496 #[doc = "Output mode 10 MHz"]
4571 let offs = 0usize + n * 1usize; 3497 pub const OUTPUT: Self = Self(0x01);
4572 let val = (self.0 >> offs) & 0x01; 3498 #[doc = "Output mode 2 MHz"]
4573 val != 0 3499 pub const OUTPUT2: Self = Self(0x02);
4574 } 3500 #[doc = "Output mode 50 MHz"]
4575 #[doc = "SRAWM2 write protection."] 3501 pub const OUTPUT50: Self = Self(0x03);
4576 pub fn set_pwp(&mut self, n: usize, val: bool) {
4577 assert!(n < 32usize);
4578 let offs = 0usize + n * 1usize;
4579 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4580 }
4581 }
4582 impl Default for Swpr {
4583 fn default() -> Swpr {
4584 Swpr(0)
4585 }
4586 } 3502 }
4587 #[doc = "SKR"]
4588 #[repr(transparent)] 3503 #[repr(transparent)]
4589 #[derive(Copy, Clone, Eq, PartialEq)] 3504 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4590 pub struct Skr(pub u32); 3505 pub struct Cnf(pub u8);
4591 impl Skr { 3506 impl Cnf {
4592 #[doc = "SRAM2 write protection key for software erase"] 3507 #[doc = "Analog mode / Push-Pull mode"]
4593 pub const fn key(&self) -> u8 { 3508 pub const PUSHPULL: Self = Self(0);
4594 let val = (self.0 >> 0usize) & 0xff; 3509 #[doc = "Floating input (reset state) / Open Drain-Mode"]
4595 val as u8 3510 pub const OPENDRAIN: Self = Self(0x01);
4596 } 3511 #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"]
4597 #[doc = "SRAM2 write protection key for software erase"] 3512 pub const ALTPUSHPULL: Self = Self(0x02);
4598 pub fn set_key(&mut self, val: u8) { 3513 #[doc = "Alternate Function Open-Drain Mode"]
4599 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); 3514 pub const ALTOPENDRAIN: Self = Self(0x03);
4600 }
4601 }
4602 impl Default for Skr {
4603 fn default() -> Skr {
4604 Skr(0)
4605 }
4606 } 3515 }
4607 } 3516 }
4608} 3517}
4609pub mod usart_v1 { 3518pub mod usart_v1 {
4610 use crate::generic::*; 3519 use crate::generic::*;
4611 #[doc = "Universal asynchronous receiver transmitter"] 3520 #[doc = "Universal synchronous asynchronous receiver transmitter"]
4612 #[derive(Copy, Clone)] 3521 #[derive(Copy, Clone)]
4613 pub struct Uart(pub *mut u8); 3522 pub struct Usart(pub *mut u8);
4614 unsafe impl Send for Uart {} 3523 unsafe impl Send for Usart {}
4615 unsafe impl Sync for Uart {} 3524 unsafe impl Sync for Usart {}
4616 impl Uart { 3525 impl Usart {
4617 #[doc = "Status register"] 3526 #[doc = "Status register"]
4618 pub fn sr(self) -> Reg<regs::Sr, RW> { 3527 pub fn sr(self) -> Reg<regs::Sr, RW> {
4619 unsafe { Reg::from_ptr(self.0.add(0usize)) } 3528 unsafe { Reg::from_ptr(self.0.add(0usize)) }
@@ -4631,20 +3540,24 @@ pub mod usart_v1 {
4631 unsafe { Reg::from_ptr(self.0.add(12usize)) } 3540 unsafe { Reg::from_ptr(self.0.add(12usize)) }
4632 } 3541 }
4633 #[doc = "Control register 2"] 3542 #[doc = "Control register 2"]
4634 pub fn cr2(self) -> Reg<regs::Cr2, RW> { 3543 pub fn cr2(self) -> Reg<regs::Cr2Usart, RW> {
4635 unsafe { Reg::from_ptr(self.0.add(16usize)) } 3544 unsafe { Reg::from_ptr(self.0.add(16usize)) }
4636 } 3545 }
4637 #[doc = "Control register 3"] 3546 #[doc = "Control register 3"]
4638 pub fn cr3(self) -> Reg<regs::Cr3, RW> { 3547 pub fn cr3(self) -> Reg<regs::Cr3Usart, RW> {
4639 unsafe { Reg::from_ptr(self.0.add(20usize)) } 3548 unsafe { Reg::from_ptr(self.0.add(20usize)) }
4640 } 3549 }
3550 #[doc = "Guard time and prescaler register"]
3551 pub fn gtpr(self) -> Reg<regs::Gtpr, RW> {
3552 unsafe { Reg::from_ptr(self.0.add(24usize)) }
3553 }
4641 } 3554 }
4642 #[doc = "Universal synchronous asynchronous receiver transmitter"] 3555 #[doc = "Universal asynchronous receiver transmitter"]
4643 #[derive(Copy, Clone)] 3556 #[derive(Copy, Clone)]
4644 pub struct Usart(pub *mut u8); 3557 pub struct Uart(pub *mut u8);
4645 unsafe impl Send for Usart {} 3558 unsafe impl Send for Uart {}
4646 unsafe impl Sync for Usart {} 3559 unsafe impl Sync for Uart {}
4647 impl Usart { 3560 impl Uart {
4648 #[doc = "Status register"] 3561 #[doc = "Status register"]
4649 pub fn sr(self) -> Reg<regs::Sr, RW> { 3562 pub fn sr(self) -> Reg<regs::Sr, RW> {
4650 unsafe { Reg::from_ptr(self.0.add(0usize)) } 3563 unsafe { Reg::from_ptr(self.0.add(0usize)) }
@@ -4662,20 +3575,130 @@ pub mod usart_v1 {
4662 unsafe { Reg::from_ptr(self.0.add(12usize)) } 3575 unsafe { Reg::from_ptr(self.0.add(12usize)) }
4663 } 3576 }
4664 #[doc = "Control register 2"] 3577 #[doc = "Control register 2"]
4665 pub fn cr2(self) -> Reg<regs::Cr2Usart, RW> { 3578 pub fn cr2(self) -> Reg<regs::Cr2, RW> {
4666 unsafe { Reg::from_ptr(self.0.add(16usize)) } 3579 unsafe { Reg::from_ptr(self.0.add(16usize)) }
4667 } 3580 }
4668 #[doc = "Control register 3"] 3581 #[doc = "Control register 3"]
4669 pub fn cr3(self) -> Reg<regs::Cr3Usart, RW> { 3582 pub fn cr3(self) -> Reg<regs::Cr3, RW> {
4670 unsafe { Reg::from_ptr(self.0.add(20usize)) } 3583 unsafe { Reg::from_ptr(self.0.add(20usize)) }
4671 } 3584 }
4672 #[doc = "Guard time and prescaler register"]
4673 pub fn gtpr(self) -> Reg<regs::Gtpr, RW> {
4674 unsafe { Reg::from_ptr(self.0.add(24usize)) }
4675 }
4676 } 3585 }
4677 pub mod regs { 3586 pub mod regs {
4678 use crate::generic::*; 3587 use crate::generic::*;
3588 #[doc = "Baud rate register"]
3589 #[repr(transparent)]
3590 #[derive(Copy, Clone, Eq, PartialEq)]
3591 pub struct Brr(pub u32);
3592 impl Brr {
3593 #[doc = "fraction of USARTDIV"]
3594 pub const fn div_fraction(&self) -> u8 {
3595 let val = (self.0 >> 0usize) & 0x0f;
3596 val as u8
3597 }
3598 #[doc = "fraction of USARTDIV"]
3599 pub fn set_div_fraction(&mut self, val: u8) {
3600 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
3601 }
3602 #[doc = "mantissa of USARTDIV"]
3603 pub const fn div_mantissa(&self) -> u16 {
3604 let val = (self.0 >> 4usize) & 0x0fff;
3605 val as u16
3606 }
3607 #[doc = "mantissa of USARTDIV"]
3608 pub fn set_div_mantissa(&mut self, val: u16) {
3609 self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize);
3610 }
3611 }
3612 impl Default for Brr {
3613 fn default() -> Brr {
3614 Brr(0)
3615 }
3616 }
3617 #[doc = "Data register"]
3618 #[repr(transparent)]
3619 #[derive(Copy, Clone, Eq, PartialEq)]
3620 pub struct Dr(pub u32);
3621 impl Dr {
3622 #[doc = "Data value"]
3623 pub const fn dr(&self) -> u16 {
3624 let val = (self.0 >> 0usize) & 0x01ff;
3625 val as u16
3626 }
3627 #[doc = "Data value"]
3628 pub fn set_dr(&mut self, val: u16) {
3629 self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
3630 }
3631 }
3632 impl Default for Dr {
3633 fn default() -> Dr {
3634 Dr(0)
3635 }
3636 }
3637 #[doc = "Control register 3"]
3638 #[repr(transparent)]
3639 #[derive(Copy, Clone, Eq, PartialEq)]
3640 pub struct Cr3(pub u32);
3641 impl Cr3 {
3642 #[doc = "Error interrupt enable"]
3643 pub const fn eie(&self) -> bool {
3644 let val = (self.0 >> 0usize) & 0x01;
3645 val != 0
3646 }
3647 #[doc = "Error interrupt enable"]
3648 pub fn set_eie(&mut self, val: bool) {
3649 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3650 }
3651 #[doc = "IrDA mode enable"]
3652 pub const fn iren(&self) -> bool {
3653 let val = (self.0 >> 1usize) & 0x01;
3654 val != 0
3655 }
3656 #[doc = "IrDA mode enable"]
3657 pub fn set_iren(&mut self, val: bool) {
3658 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3659 }
3660 #[doc = "IrDA low-power"]
3661 pub const fn irlp(&self) -> super::vals::Irlp {
3662 let val = (self.0 >> 2usize) & 0x01;
3663 super::vals::Irlp(val as u8)
3664 }
3665 #[doc = "IrDA low-power"]
3666 pub fn set_irlp(&mut self, val: super::vals::Irlp) {
3667 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
3668 }
3669 #[doc = "Half-duplex selection"]
3670 pub const fn hdsel(&self) -> super::vals::Hdsel {
3671 let val = (self.0 >> 3usize) & 0x01;
3672 super::vals::Hdsel(val as u8)
3673 }
3674 #[doc = "Half-duplex selection"]
3675 pub fn set_hdsel(&mut self, val: super::vals::Hdsel) {
3676 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
3677 }
3678 #[doc = "DMA enable receiver"]
3679 pub const fn dmar(&self) -> bool {
3680 let val = (self.0 >> 6usize) & 0x01;
3681 val != 0
3682 }
3683 #[doc = "DMA enable receiver"]
3684 pub fn set_dmar(&mut self, val: bool) {
3685 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
3686 }
3687 #[doc = "DMA enable transmitter"]
3688 pub const fn dmat(&self) -> bool {
3689 let val = (self.0 >> 7usize) & 0x01;
3690 val != 0
3691 }
3692 #[doc = "DMA enable transmitter"]
3693 pub fn set_dmat(&mut self, val: bool) {
3694 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
3695 }
3696 }
3697 impl Default for Cr3 {
3698 fn default() -> Cr3 {
3699 Cr3(0)
3700 }
3701 }
4679 #[doc = "Status register"] 3702 #[doc = "Status register"]
4680 #[repr(transparent)] 3703 #[repr(transparent)]
4681 #[derive(Copy, Clone, Eq, PartialEq)] 3704 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -4777,125 +3800,125 @@ pub mod usart_v1 {
4777 SrUsart(0) 3800 SrUsart(0)
4778 } 3801 }
4779 } 3802 }
4780 #[doc = "Baud rate register"] 3803 #[doc = "Guard time and prescaler register"]
4781 #[repr(transparent)] 3804 #[repr(transparent)]
4782 #[derive(Copy, Clone, Eq, PartialEq)] 3805 #[derive(Copy, Clone, Eq, PartialEq)]
4783 pub struct Brr(pub u32); 3806 pub struct Gtpr(pub u32);
4784 impl Brr { 3807 impl Gtpr {
4785 #[doc = "fraction of USARTDIV"] 3808 #[doc = "Prescaler value"]
4786 pub const fn div_fraction(&self) -> u8 { 3809 pub const fn psc(&self) -> u8 {
4787 let val = (self.0 >> 0usize) & 0x0f; 3810 let val = (self.0 >> 0usize) & 0xff;
4788 val as u8 3811 val as u8
4789 } 3812 }
4790 #[doc = "fraction of USARTDIV"] 3813 #[doc = "Prescaler value"]
4791 pub fn set_div_fraction(&mut self, val: u8) { 3814 pub fn set_psc(&mut self, val: u8) {
4792 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); 3815 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
4793 } 3816 }
4794 #[doc = "mantissa of USARTDIV"] 3817 #[doc = "Guard time value"]
4795 pub const fn div_mantissa(&self) -> u16 { 3818 pub const fn gt(&self) -> u8 {
4796 let val = (self.0 >> 4usize) & 0x0fff; 3819 let val = (self.0 >> 8usize) & 0xff;
4797 val as u16 3820 val as u8
4798 } 3821 }
4799 #[doc = "mantissa of USARTDIV"] 3822 #[doc = "Guard time value"]
4800 pub fn set_div_mantissa(&mut self, val: u16) { 3823 pub fn set_gt(&mut self, val: u8) {
4801 self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); 3824 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
4802 } 3825 }
4803 } 3826 }
4804 impl Default for Brr { 3827 impl Default for Gtpr {
4805 fn default() -> Brr { 3828 fn default() -> Gtpr {
4806 Brr(0) 3829 Gtpr(0)
4807 } 3830 }
4808 } 3831 }
4809 #[doc = "Status register"] 3832 #[doc = "Control register 2"]
4810 #[repr(transparent)] 3833 #[repr(transparent)]
4811 #[derive(Copy, Clone, Eq, PartialEq)] 3834 #[derive(Copy, Clone, Eq, PartialEq)]
4812 pub struct Sr(pub u32); 3835 pub struct Cr2Usart(pub u32);
4813 impl Sr { 3836 impl Cr2Usart {
4814 #[doc = "Parity error"] 3837 #[doc = "Address of the USART node"]
4815 pub const fn pe(&self) -> bool { 3838 pub const fn add(&self) -> u8 {
4816 let val = (self.0 >> 0usize) & 0x01; 3839 let val = (self.0 >> 0usize) & 0x0f;
4817 val != 0 3840 val as u8
4818 } 3841 }
4819 #[doc = "Parity error"] 3842 #[doc = "Address of the USART node"]
4820 pub fn set_pe(&mut self, val: bool) { 3843 pub fn set_add(&mut self, val: u8) {
4821 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 3844 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
4822 } 3845 }
4823 #[doc = "Framing error"] 3846 #[doc = "lin break detection length"]
4824 pub const fn fe(&self) -> bool { 3847 pub const fn lbdl(&self) -> super::vals::Lbdl {
4825 let val = (self.0 >> 1usize) & 0x01; 3848 let val = (self.0 >> 5usize) & 0x01;
4826 val != 0 3849 super::vals::Lbdl(val as u8)
4827 } 3850 }
4828 #[doc = "Framing error"] 3851 #[doc = "lin break detection length"]
4829 pub fn set_fe(&mut self, val: bool) { 3852 pub fn set_lbdl(&mut self, val: super::vals::Lbdl) {
4830 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); 3853 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
4831 } 3854 }
4832 #[doc = "Noise error flag"] 3855 #[doc = "LIN break detection interrupt enable"]
4833 pub const fn ne(&self) -> bool { 3856 pub const fn lbdie(&self) -> bool {
4834 let val = (self.0 >> 2usize) & 0x01; 3857 let val = (self.0 >> 6usize) & 0x01;
4835 val != 0 3858 val != 0
4836 } 3859 }
4837 #[doc = "Noise error flag"] 3860 #[doc = "LIN break detection interrupt enable"]
4838 pub fn set_ne(&mut self, val: bool) { 3861 pub fn set_lbdie(&mut self, val: bool) {
4839 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); 3862 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
4840 } 3863 }
4841 #[doc = "Overrun error"] 3864 #[doc = "Last bit clock pulse"]
4842 pub const fn ore(&self) -> bool { 3865 pub const fn lbcl(&self) -> bool {
4843 let val = (self.0 >> 3usize) & 0x01; 3866 let val = (self.0 >> 8usize) & 0x01;
4844 val != 0 3867 val != 0
4845 } 3868 }
4846 #[doc = "Overrun error"] 3869 #[doc = "Last bit clock pulse"]
4847 pub fn set_ore(&mut self, val: bool) { 3870 pub fn set_lbcl(&mut self, val: bool) {
4848 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); 3871 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
4849 } 3872 }
4850 #[doc = "IDLE line detected"] 3873 #[doc = "Clock phase"]
4851 pub const fn idle(&self) -> bool { 3874 pub const fn cpha(&self) -> super::vals::Cpha {
4852 let val = (self.0 >> 4usize) & 0x01; 3875 let val = (self.0 >> 9usize) & 0x01;
4853 val != 0 3876 super::vals::Cpha(val as u8)
4854 } 3877 }
4855 #[doc = "IDLE line detected"] 3878 #[doc = "Clock phase"]
4856 pub fn set_idle(&mut self, val: bool) { 3879 pub fn set_cpha(&mut self, val: super::vals::Cpha) {
4857 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); 3880 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
4858 } 3881 }
4859 #[doc = "Read data register not empty"] 3882 #[doc = "Clock polarity"]
4860 pub const fn rxne(&self) -> bool { 3883 pub const fn cpol(&self) -> super::vals::Cpol {
4861 let val = (self.0 >> 5usize) & 0x01; 3884 let val = (self.0 >> 10usize) & 0x01;
4862 val != 0 3885 super::vals::Cpol(val as u8)
4863 } 3886 }
4864 #[doc = "Read data register not empty"] 3887 #[doc = "Clock polarity"]
4865 pub fn set_rxne(&mut self, val: bool) { 3888 pub fn set_cpol(&mut self, val: super::vals::Cpol) {
4866 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); 3889 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
4867 } 3890 }
4868 #[doc = "Transmission complete"] 3891 #[doc = "Clock enable"]
4869 pub const fn tc(&self) -> bool { 3892 pub const fn clken(&self) -> bool {
4870 let val = (self.0 >> 6usize) & 0x01; 3893 let val = (self.0 >> 11usize) & 0x01;
4871 val != 0 3894 val != 0
4872 } 3895 }
4873 #[doc = "Transmission complete"] 3896 #[doc = "Clock enable"]
4874 pub fn set_tc(&mut self, val: bool) { 3897 pub fn set_clken(&mut self, val: bool) {
4875 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); 3898 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
4876 } 3899 }
4877 #[doc = "Transmit data register empty"] 3900 #[doc = "STOP bits"]
4878 pub const fn txe(&self) -> bool { 3901 pub const fn stop(&self) -> super::vals::Stop {
4879 let val = (self.0 >> 7usize) & 0x01; 3902 let val = (self.0 >> 12usize) & 0x03;
4880 val != 0 3903 super::vals::Stop(val as u8)
4881 } 3904 }
4882 #[doc = "Transmit data register empty"] 3905 #[doc = "STOP bits"]
4883 pub fn set_txe(&mut self, val: bool) { 3906 pub fn set_stop(&mut self, val: super::vals::Stop) {
4884 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); 3907 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
4885 } 3908 }
4886 #[doc = "LIN break detection flag"] 3909 #[doc = "LIN mode enable"]
4887 pub const fn lbd(&self) -> bool { 3910 pub const fn linen(&self) -> bool {
4888 let val = (self.0 >> 8usize) & 0x01; 3911 let val = (self.0 >> 14usize) & 0x01;
4889 val != 0 3912 val != 0
4890 } 3913 }
4891 #[doc = "LIN break detection flag"] 3914 #[doc = "LIN mode enable"]
4892 pub fn set_lbd(&mut self, val: bool) { 3915 pub fn set_linen(&mut self, val: bool) {
4893 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); 3916 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
4894 } 3917 }
4895 } 3918 }
4896 impl Default for Sr { 3919 impl Default for Cr2Usart {
4897 fn default() -> Sr { 3920 fn default() -> Cr2Usart {
4898 Sr(0) 3921 Cr2Usart(0)
4899 } 3922 }
4900 } 3923 }
4901 #[doc = "Control register 1"] 3924 #[doc = "Control register 1"]
@@ -5148,8 +4171,8 @@ pub mod usart_v1 {
5148 #[doc = "Control register 2"] 4171 #[doc = "Control register 2"]
5149 #[repr(transparent)] 4172 #[repr(transparent)]
5150 #[derive(Copy, Clone, Eq, PartialEq)] 4173 #[derive(Copy, Clone, Eq, PartialEq)]
5151 pub struct Cr2Usart(pub u32); 4174 pub struct Cr2(pub u32);
5152 impl Cr2Usart { 4175 impl Cr2 {
5153 #[doc = "Address of the USART node"] 4176 #[doc = "Address of the USART node"]
5154 pub const fn add(&self) -> u8 { 4177 pub const fn add(&self) -> u8 {
5155 let val = (self.0 >> 0usize) & 0x0f; 4178 let val = (self.0 >> 0usize) & 0x0f;
@@ -5177,42 +4200,6 @@ pub mod usart_v1 {
5177 pub fn set_lbdie(&mut self, val: bool) { 4200 pub fn set_lbdie(&mut self, val: bool) {
5178 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); 4201 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
5179 } 4202 }
5180 #[doc = "Last bit clock pulse"]
5181 pub const fn lbcl(&self) -> bool {
5182 let val = (self.0 >> 8usize) & 0x01;
5183 val != 0
5184 }
5185 #[doc = "Last bit clock pulse"]
5186 pub fn set_lbcl(&mut self, val: bool) {
5187 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
5188 }
5189 #[doc = "Clock phase"]
5190 pub const fn cpha(&self) -> super::vals::Cpha {
5191 let val = (self.0 >> 9usize) & 0x01;
5192 super::vals::Cpha(val as u8)
5193 }
5194 #[doc = "Clock phase"]
5195 pub fn set_cpha(&mut self, val: super::vals::Cpha) {
5196 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
5197 }
5198 #[doc = "Clock polarity"]
5199 pub const fn cpol(&self) -> super::vals::Cpol {
5200 let val = (self.0 >> 10usize) & 0x01;
5201 super::vals::Cpol(val as u8)
5202 }
5203 #[doc = "Clock polarity"]
5204 pub fn set_cpol(&mut self, val: super::vals::Cpol) {
5205 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
5206 }
5207 #[doc = "Clock enable"]
5208 pub const fn clken(&self) -> bool {
5209 let val = (self.0 >> 11usize) & 0x01;
5210 val != 0
5211 }
5212 #[doc = "Clock enable"]
5213 pub fn set_clken(&mut self, val: bool) {
5214 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
5215 }
5216 #[doc = "STOP bits"] 4203 #[doc = "STOP bits"]
5217 pub const fn stop(&self) -> super::vals::Stop { 4204 pub const fn stop(&self) -> super::vals::Stop {
5218 let val = (self.0 >> 12usize) & 0x03; 4205 let val = (self.0 >> 12usize) & 0x03;
@@ -5232,179 +4219,1154 @@ pub mod usart_v1 {
5232 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); 4219 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
5233 } 4220 }
5234 } 4221 }
5235 impl Default for Cr2Usart { 4222 impl Default for Cr2 {
5236 fn default() -> Cr2Usart { 4223 fn default() -> Cr2 {
5237 Cr2Usart(0) 4224 Cr2(0)
5238 } 4225 }
5239 } 4226 }
5240 #[doc = "Control register 3"] 4227 #[doc = "Status register"]
5241 #[repr(transparent)] 4228 #[repr(transparent)]
5242 #[derive(Copy, Clone, Eq, PartialEq)] 4229 #[derive(Copy, Clone, Eq, PartialEq)]
5243 pub struct Cr3(pub u32); 4230 pub struct Sr(pub u32);
5244 impl Cr3 { 4231 impl Sr {
5245 #[doc = "Error interrupt enable"] 4232 #[doc = "Parity error"]
5246 pub const fn eie(&self) -> bool { 4233 pub const fn pe(&self) -> bool {
5247 let val = (self.0 >> 0usize) & 0x01; 4234 let val = (self.0 >> 0usize) & 0x01;
5248 val != 0 4235 val != 0
5249 } 4236 }
5250 #[doc = "Error interrupt enable"] 4237 #[doc = "Parity error"]
5251 pub fn set_eie(&mut self, val: bool) { 4238 pub fn set_pe(&mut self, val: bool) {
5252 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 4239 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5253 } 4240 }
5254 #[doc = "IrDA mode enable"] 4241 #[doc = "Framing error"]
5255 pub const fn iren(&self) -> bool { 4242 pub const fn fe(&self) -> bool {
5256 let val = (self.0 >> 1usize) & 0x01; 4243 let val = (self.0 >> 1usize) & 0x01;
5257 val != 0 4244 val != 0
5258 } 4245 }
5259 #[doc = "IrDA mode enable"] 4246 #[doc = "Framing error"]
5260 pub fn set_iren(&mut self, val: bool) { 4247 pub fn set_fe(&mut self, val: bool) {
5261 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); 4248 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
5262 } 4249 }
5263 #[doc = "IrDA low-power"] 4250 #[doc = "Noise error flag"]
5264 pub const fn irlp(&self) -> super::vals::Irlp { 4251 pub const fn ne(&self) -> bool {
5265 let val = (self.0 >> 2usize) & 0x01; 4252 let val = (self.0 >> 2usize) & 0x01;
5266 super::vals::Irlp(val as u8) 4253 val != 0
5267 } 4254 }
5268 #[doc = "IrDA low-power"] 4255 #[doc = "Noise error flag"]
5269 pub fn set_irlp(&mut self, val: super::vals::Irlp) { 4256 pub fn set_ne(&mut self, val: bool) {
5270 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); 4257 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
5271 } 4258 }
5272 #[doc = "Half-duplex selection"] 4259 #[doc = "Overrun error"]
5273 pub const fn hdsel(&self) -> super::vals::Hdsel { 4260 pub const fn ore(&self) -> bool {
5274 let val = (self.0 >> 3usize) & 0x01; 4261 let val = (self.0 >> 3usize) & 0x01;
5275 super::vals::Hdsel(val as u8) 4262 val != 0
5276 } 4263 }
5277 #[doc = "Half-duplex selection"] 4264 #[doc = "Overrun error"]
5278 pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { 4265 pub fn set_ore(&mut self, val: bool) {
5279 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); 4266 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
5280 } 4267 }
5281 #[doc = "DMA enable receiver"] 4268 #[doc = "IDLE line detected"]
5282 pub const fn dmar(&self) -> bool { 4269 pub const fn idle(&self) -> bool {
4270 let val = (self.0 >> 4usize) & 0x01;
4271 val != 0
4272 }
4273 #[doc = "IDLE line detected"]
4274 pub fn set_idle(&mut self, val: bool) {
4275 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
4276 }
4277 #[doc = "Read data register not empty"]
4278 pub const fn rxne(&self) -> bool {
4279 let val = (self.0 >> 5usize) & 0x01;
4280 val != 0
4281 }
4282 #[doc = "Read data register not empty"]
4283 pub fn set_rxne(&mut self, val: bool) {
4284 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
4285 }
4286 #[doc = "Transmission complete"]
4287 pub const fn tc(&self) -> bool {
5283 let val = (self.0 >> 6usize) & 0x01; 4288 let val = (self.0 >> 6usize) & 0x01;
5284 val != 0 4289 val != 0
5285 } 4290 }
5286 #[doc = "DMA enable receiver"] 4291 #[doc = "Transmission complete"]
5287 pub fn set_dmar(&mut self, val: bool) { 4292 pub fn set_tc(&mut self, val: bool) {
5288 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); 4293 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
5289 } 4294 }
5290 #[doc = "DMA enable transmitter"] 4295 #[doc = "Transmit data register empty"]
5291 pub const fn dmat(&self) -> bool { 4296 pub const fn txe(&self) -> bool {
5292 let val = (self.0 >> 7usize) & 0x01; 4297 let val = (self.0 >> 7usize) & 0x01;
5293 val != 0 4298 val != 0
5294 } 4299 }
5295 #[doc = "DMA enable transmitter"] 4300 #[doc = "Transmit data register empty"]
5296 pub fn set_dmat(&mut self, val: bool) { 4301 pub fn set_txe(&mut self, val: bool) {
5297 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); 4302 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
5298 } 4303 }
4304 #[doc = "LIN break detection flag"]
4305 pub const fn lbd(&self) -> bool {
4306 let val = (self.0 >> 8usize) & 0x01;
4307 val != 0
4308 }
4309 #[doc = "LIN break detection flag"]
4310 pub fn set_lbd(&mut self, val: bool) {
4311 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
4312 }
5299 } 4313 }
5300 impl Default for Cr3 { 4314 impl Default for Sr {
5301 fn default() -> Cr3 { 4315 fn default() -> Sr {
5302 Cr3(0) 4316 Sr(0)
5303 } 4317 }
5304 } 4318 }
5305 #[doc = "Guard time and prescaler register"] 4319 }
4320 pub mod vals {
4321 use crate::generic::*;
4322 #[repr(transparent)]
4323 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4324 pub struct Stop(pub u8);
4325 impl Stop {
4326 #[doc = "1 stop bit"]
4327 pub const STOP1: Self = Self(0);
4328 #[doc = "0.5 stop bits"]
4329 pub const STOP0P5: Self = Self(0x01);
4330 #[doc = "2 stop bits"]
4331 pub const STOP2: Self = Self(0x02);
4332 #[doc = "1.5 stop bits"]
4333 pub const STOP1P5: Self = Self(0x03);
4334 }
4335 #[repr(transparent)]
4336 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4337 pub struct Irlp(pub u8);
4338 impl Irlp {
4339 #[doc = "Normal mode"]
4340 pub const NORMAL: Self = Self(0);
4341 #[doc = "Low-power mode"]
4342 pub const LOWPOWER: Self = Self(0x01);
4343 }
4344 #[repr(transparent)]
4345 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4346 pub struct Hdsel(pub u8);
4347 impl Hdsel {
4348 #[doc = "Half duplex mode is not selected"]
4349 pub const FULLDUPLEX: Self = Self(0);
4350 #[doc = "Half duplex mode is selected"]
4351 pub const HALFDUPLEX: Self = Self(0x01);
4352 }
4353 #[repr(transparent)]
4354 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4355 pub struct Lbdl(pub u8);
4356 impl Lbdl {
4357 #[doc = "10-bit break detection"]
4358 pub const LBDL10: Self = Self(0);
4359 #[doc = "11-bit break detection"]
4360 pub const LBDL11: Self = Self(0x01);
4361 }
4362 #[repr(transparent)]
4363 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4364 pub struct M(pub u8);
4365 impl M {
4366 #[doc = "8 data bits"]
4367 pub const M8: Self = Self(0);
4368 #[doc = "9 data bits"]
4369 pub const M9: Self = Self(0x01);
4370 }
4371 #[repr(transparent)]
4372 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4373 pub struct Cpha(pub u8);
4374 impl Cpha {
4375 #[doc = "The first clock transition is the first data capture edge"]
4376 pub const FIRST: Self = Self(0);
4377 #[doc = "The second clock transition is the first data capture edge"]
4378 pub const SECOND: Self = Self(0x01);
4379 }
4380 #[repr(transparent)]
4381 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4382 pub struct Rwu(pub u8);
4383 impl Rwu {
4384 #[doc = "Receiver in active mode"]
4385 pub const ACTIVE: Self = Self(0);
4386 #[doc = "Receiver in mute mode"]
4387 pub const MUTE: Self = Self(0x01);
4388 }
4389 #[repr(transparent)]
4390 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4391 pub struct Cpol(pub u8);
4392 impl Cpol {
4393 #[doc = "Steady low value on CK pin outside transmission window"]
4394 pub const LOW: Self = Self(0);
4395 #[doc = "Steady high value on CK pin outside transmission window"]
4396 pub const HIGH: Self = Self(0x01);
4397 }
4398 #[repr(transparent)]
4399 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4400 pub struct Wake(pub u8);
4401 impl Wake {
4402 #[doc = "USART wakeup on idle line"]
4403 pub const IDLELINE: Self = Self(0);
4404 #[doc = "USART wakeup on address mark"]
4405 pub const ADDRESSMARK: Self = Self(0x01);
4406 }
4407 #[repr(transparent)]
4408 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4409 pub struct Sbk(pub u8);
4410 impl Sbk {
4411 #[doc = "No break character is transmitted"]
4412 pub const NOBREAK: Self = Self(0);
4413 #[doc = "Break character transmitted"]
4414 pub const BREAK: Self = Self(0x01);
4415 }
4416 #[repr(transparent)]
4417 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4418 pub struct Ps(pub u8);
4419 impl Ps {
4420 #[doc = "Even parity"]
4421 pub const EVEN: Self = Self(0);
4422 #[doc = "Odd parity"]
4423 pub const ODD: Self = Self(0x01);
4424 }
4425 }
4426}
4427pub mod dma_v1 {
4428 use crate::generic::*;
4429 #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
4430 #[derive(Copy, Clone)]
4431 pub struct Ch(pub *mut u8);
4432 unsafe impl Send for Ch {}
4433 unsafe impl Sync for Ch {}
4434 impl Ch {
4435 #[doc = "DMA channel configuration register (DMA_CCR)"]
4436 pub fn cr(self) -> Reg<regs::Cr, RW> {
4437 unsafe { Reg::from_ptr(self.0.add(0usize)) }
4438 }
4439 #[doc = "DMA channel 1 number of data register"]
4440 pub fn ndtr(self) -> Reg<regs::Ndtr, RW> {
4441 unsafe { Reg::from_ptr(self.0.add(4usize)) }
4442 }
4443 #[doc = "DMA channel 1 peripheral address register"]
4444 pub fn par(self) -> Reg<u32, RW> {
4445 unsafe { Reg::from_ptr(self.0.add(8usize)) }
4446 }
4447 #[doc = "DMA channel 1 memory address register"]
4448 pub fn mar(self) -> Reg<u32, RW> {
4449 unsafe { Reg::from_ptr(self.0.add(12usize)) }
4450 }
4451 }
4452 #[doc = "DMA controller"]
4453 #[derive(Copy, Clone)]
4454 pub struct Dma(pub *mut u8);
4455 unsafe impl Send for Dma {}
4456 unsafe impl Sync for Dma {}
4457 impl Dma {
4458 #[doc = "DMA interrupt status register (DMA_ISR)"]
4459 pub fn isr(self) -> Reg<regs::Isr, R> {
4460 unsafe { Reg::from_ptr(self.0.add(0usize)) }
4461 }
4462 #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
4463 pub fn ifcr(self) -> Reg<regs::Ifcr, W> {
4464 unsafe { Reg::from_ptr(self.0.add(4usize)) }
4465 }
4466 #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
4467 pub fn ch(self, n: usize) -> Ch {
4468 assert!(n < 7usize);
4469 unsafe { Ch(self.0.add(8usize + n * 20usize)) }
4470 }
4471 }
4472 pub mod vals {
4473 use crate::generic::*;
4474 #[repr(transparent)]
4475 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4476 pub struct Memmem(pub u8);
4477 impl Memmem {
4478 #[doc = "Memory to memory mode disabled"]
4479 pub const DISABLED: Self = Self(0);
4480 #[doc = "Memory to memory mode enabled"]
4481 pub const ENABLED: Self = Self(0x01);
4482 }
4483 #[repr(transparent)]
4484 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4485 pub struct Inc(pub u8);
4486 impl Inc {
4487 #[doc = "Increment mode disabled"]
4488 pub const DISABLED: Self = Self(0);
4489 #[doc = "Increment mode enabled"]
4490 pub const ENABLED: Self = Self(0x01);
4491 }
4492 #[repr(transparent)]
4493 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4494 pub struct Dir(pub u8);
4495 impl Dir {
4496 #[doc = "Read from peripheral"]
4497 pub const FROMPERIPHERAL: Self = Self(0);
4498 #[doc = "Read from memory"]
4499 pub const FROMMEMORY: Self = Self(0x01);
4500 }
4501 #[repr(transparent)]
4502 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4503 pub struct Circ(pub u8);
4504 impl Circ {
4505 #[doc = "Circular buffer disabled"]
4506 pub const DISABLED: Self = Self(0);
4507 #[doc = "Circular buffer enabled"]
4508 pub const ENABLED: Self = Self(0x01);
4509 }
4510 #[repr(transparent)]
4511 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4512 pub struct Size(pub u8);
4513 impl Size {
4514 #[doc = "8-bit size"]
4515 pub const BITS8: Self = Self(0);
4516 #[doc = "16-bit size"]
4517 pub const BITS16: Self = Self(0x01);
4518 #[doc = "32-bit size"]
4519 pub const BITS32: Self = Self(0x02);
4520 }
4521 #[repr(transparent)]
4522 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4523 pub struct Pl(pub u8);
4524 impl Pl {
4525 #[doc = "Low priority"]
4526 pub const LOW: Self = Self(0);
4527 #[doc = "Medium priority"]
4528 pub const MEDIUM: Self = Self(0x01);
4529 #[doc = "High priority"]
4530 pub const HIGH: Self = Self(0x02);
4531 #[doc = "Very high priority"]
4532 pub const VERYHIGH: Self = Self(0x03);
4533 }
4534 }
4535 pub mod regs {
4536 use crate::generic::*;
4537 #[doc = "DMA channel configuration register (DMA_CCR)"]
5306 #[repr(transparent)] 4538 #[repr(transparent)]
5307 #[derive(Copy, Clone, Eq, PartialEq)] 4539 #[derive(Copy, Clone, Eq, PartialEq)]
5308 pub struct Gtpr(pub u32); 4540 pub struct Cr(pub u32);
5309 impl Gtpr { 4541 impl Cr {
5310 #[doc = "Prescaler value"] 4542 #[doc = "Channel enable"]
5311 pub const fn psc(&self) -> u8 { 4543 pub const fn en(&self) -> bool {
5312 let val = (self.0 >> 0usize) & 0xff; 4544 let val = (self.0 >> 0usize) & 0x01;
5313 val as u8 4545 val != 0
5314 } 4546 }
5315 #[doc = "Prescaler value"] 4547 #[doc = "Channel enable"]
5316 pub fn set_psc(&mut self, val: u8) { 4548 pub fn set_en(&mut self, val: bool) {
5317 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); 4549 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5318 } 4550 }
5319 #[doc = "Guard time value"] 4551 #[doc = "Transfer complete interrupt enable"]
5320 pub const fn gt(&self) -> u8 { 4552 pub const fn tcie(&self) -> bool {
5321 let val = (self.0 >> 8usize) & 0xff; 4553 let val = (self.0 >> 1usize) & 0x01;
5322 val as u8 4554 val != 0
5323 } 4555 }
5324 #[doc = "Guard time value"] 4556 #[doc = "Transfer complete interrupt enable"]
5325 pub fn set_gt(&mut self, val: u8) { 4557 pub fn set_tcie(&mut self, val: bool) {
5326 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); 4558 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4559 }
4560 #[doc = "Half Transfer interrupt enable"]
4561 pub const fn htie(&self) -> bool {
4562 let val = (self.0 >> 2usize) & 0x01;
4563 val != 0
4564 }
4565 #[doc = "Half Transfer interrupt enable"]
4566 pub fn set_htie(&mut self, val: bool) {
4567 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4568 }
4569 #[doc = "Transfer error interrupt enable"]
4570 pub const fn teie(&self) -> bool {
4571 let val = (self.0 >> 3usize) & 0x01;
4572 val != 0
4573 }
4574 #[doc = "Transfer error interrupt enable"]
4575 pub fn set_teie(&mut self, val: bool) {
4576 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
4577 }
4578 #[doc = "Data transfer direction"]
4579 pub const fn dir(&self) -> super::vals::Dir {
4580 let val = (self.0 >> 4usize) & 0x01;
4581 super::vals::Dir(val as u8)
4582 }
4583 #[doc = "Data transfer direction"]
4584 pub fn set_dir(&mut self, val: super::vals::Dir) {
4585 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
4586 }
4587 #[doc = "Circular mode"]
4588 pub const fn circ(&self) -> super::vals::Circ {
4589 let val = (self.0 >> 5usize) & 0x01;
4590 super::vals::Circ(val as u8)
4591 }
4592 #[doc = "Circular mode"]
4593 pub fn set_circ(&mut self, val: super::vals::Circ) {
4594 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
4595 }
4596 #[doc = "Peripheral increment mode"]
4597 pub const fn pinc(&self) -> super::vals::Inc {
4598 let val = (self.0 >> 6usize) & 0x01;
4599 super::vals::Inc(val as u8)
4600 }
4601 #[doc = "Peripheral increment mode"]
4602 pub fn set_pinc(&mut self, val: super::vals::Inc) {
4603 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
4604 }
4605 #[doc = "Memory increment mode"]
4606 pub const fn minc(&self) -> super::vals::Inc {
4607 let val = (self.0 >> 7usize) & 0x01;
4608 super::vals::Inc(val as u8)
4609 }
4610 #[doc = "Memory increment mode"]
4611 pub fn set_minc(&mut self, val: super::vals::Inc) {
4612 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
4613 }
4614 #[doc = "Peripheral size"]
4615 pub const fn psize(&self) -> super::vals::Size {
4616 let val = (self.0 >> 8usize) & 0x03;
4617 super::vals::Size(val as u8)
4618 }
4619 #[doc = "Peripheral size"]
4620 pub fn set_psize(&mut self, val: super::vals::Size) {
4621 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
4622 }
4623 #[doc = "Memory size"]
4624 pub const fn msize(&self) -> super::vals::Size {
4625 let val = (self.0 >> 10usize) & 0x03;
4626 super::vals::Size(val as u8)
4627 }
4628 #[doc = "Memory size"]
4629 pub fn set_msize(&mut self, val: super::vals::Size) {
4630 self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize);
4631 }
4632 #[doc = "Channel Priority level"]
4633 pub const fn pl(&self) -> super::vals::Pl {
4634 let val = (self.0 >> 12usize) & 0x03;
4635 super::vals::Pl(val as u8)
4636 }
4637 #[doc = "Channel Priority level"]
4638 pub fn set_pl(&mut self, val: super::vals::Pl) {
4639 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
4640 }
4641 #[doc = "Memory to memory mode"]
4642 pub const fn mem2mem(&self) -> super::vals::Memmem {
4643 let val = (self.0 >> 14usize) & 0x01;
4644 super::vals::Memmem(val as u8)
4645 }
4646 #[doc = "Memory to memory mode"]
4647 pub fn set_mem2mem(&mut self, val: super::vals::Memmem) {
4648 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
5327 } 4649 }
5328 } 4650 }
5329 impl Default for Gtpr { 4651 impl Default for Cr {
5330 fn default() -> Gtpr { 4652 fn default() -> Cr {
5331 Gtpr(0) 4653 Cr(0)
5332 } 4654 }
5333 } 4655 }
5334 #[doc = "Data register"] 4656 #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
5335 #[repr(transparent)] 4657 #[repr(transparent)]
5336 #[derive(Copy, Clone, Eq, PartialEq)] 4658 #[derive(Copy, Clone, Eq, PartialEq)]
5337 pub struct Dr(pub u32); 4659 pub struct Ifcr(pub u32);
5338 impl Dr { 4660 impl Ifcr {
5339 #[doc = "Data value"] 4661 #[doc = "Channel 1 Global interrupt clear"]
5340 pub const fn dr(&self) -> u16 { 4662 pub fn cgif(&self, n: usize) -> bool {
5341 let val = (self.0 >> 0usize) & 0x01ff; 4663 assert!(n < 7usize);
4664 let offs = 0usize + n * 4usize;
4665 let val = (self.0 >> offs) & 0x01;
4666 val != 0
4667 }
4668 #[doc = "Channel 1 Global interrupt clear"]
4669 pub fn set_cgif(&mut self, n: usize, val: bool) {
4670 assert!(n < 7usize);
4671 let offs = 0usize + n * 4usize;
4672 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4673 }
4674 #[doc = "Channel 1 Transfer Complete clear"]
4675 pub fn ctcif(&self, n: usize) -> bool {
4676 assert!(n < 7usize);
4677 let offs = 1usize + n * 4usize;
4678 let val = (self.0 >> offs) & 0x01;
4679 val != 0
4680 }
4681 #[doc = "Channel 1 Transfer Complete clear"]
4682 pub fn set_ctcif(&mut self, n: usize, val: bool) {
4683 assert!(n < 7usize);
4684 let offs = 1usize + n * 4usize;
4685 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4686 }
4687 #[doc = "Channel 1 Half Transfer clear"]
4688 pub fn chtif(&self, n: usize) -> bool {
4689 assert!(n < 7usize);
4690 let offs = 2usize + n * 4usize;
4691 let val = (self.0 >> offs) & 0x01;
4692 val != 0
4693 }
4694 #[doc = "Channel 1 Half Transfer clear"]
4695 pub fn set_chtif(&mut self, n: usize, val: bool) {
4696 assert!(n < 7usize);
4697 let offs = 2usize + n * 4usize;
4698 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4699 }
4700 #[doc = "Channel 1 Transfer Error clear"]
4701 pub fn cteif(&self, n: usize) -> bool {
4702 assert!(n < 7usize);
4703 let offs = 3usize + n * 4usize;
4704 let val = (self.0 >> offs) & 0x01;
4705 val != 0
4706 }
4707 #[doc = "Channel 1 Transfer Error clear"]
4708 pub fn set_cteif(&mut self, n: usize, val: bool) {
4709 assert!(n < 7usize);
4710 let offs = 3usize + n * 4usize;
4711 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4712 }
4713 }
4714 impl Default for Ifcr {
4715 fn default() -> Ifcr {
4716 Ifcr(0)
4717 }
4718 }
4719 #[doc = "DMA channel 1 number of data register"]
4720 #[repr(transparent)]
4721 #[derive(Copy, Clone, Eq, PartialEq)]
4722 pub struct Ndtr(pub u32);
4723 impl Ndtr {
4724 #[doc = "Number of data to transfer"]
4725 pub const fn ndt(&self) -> u16 {
4726 let val = (self.0 >> 0usize) & 0xffff;
5342 val as u16 4727 val as u16
5343 } 4728 }
5344 #[doc = "Data value"] 4729 #[doc = "Number of data to transfer"]
5345 pub fn set_dr(&mut self, val: u16) { 4730 pub fn set_ndt(&mut self, val: u16) {
5346 self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); 4731 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
5347 } 4732 }
5348 } 4733 }
5349 impl Default for Dr { 4734 impl Default for Ndtr {
5350 fn default() -> Dr { 4735 fn default() -> Ndtr {
5351 Dr(0) 4736 Ndtr(0)
5352 } 4737 }
5353 } 4738 }
5354 #[doc = "Control register 2"] 4739 #[doc = "DMA interrupt status register (DMA_ISR)"]
5355 #[repr(transparent)] 4740 #[repr(transparent)]
5356 #[derive(Copy, Clone, Eq, PartialEq)] 4741 #[derive(Copy, Clone, Eq, PartialEq)]
5357 pub struct Cr2(pub u32); 4742 pub struct Isr(pub u32);
5358 impl Cr2 { 4743 impl Isr {
5359 #[doc = "Address of the USART node"] 4744 #[doc = "Channel 1 Global interrupt flag"]
5360 pub const fn add(&self) -> u8 { 4745 pub fn gif(&self, n: usize) -> bool {
5361 let val = (self.0 >> 0usize) & 0x0f; 4746 assert!(n < 7usize);
5362 val as u8 4747 let offs = 0usize + n * 4usize;
4748 let val = (self.0 >> offs) & 0x01;
4749 val != 0
5363 } 4750 }
5364 #[doc = "Address of the USART node"] 4751 #[doc = "Channel 1 Global interrupt flag"]
5365 pub fn set_add(&mut self, val: u8) { 4752 pub fn set_gif(&mut self, n: usize, val: bool) {
5366 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); 4753 assert!(n < 7usize);
4754 let offs = 0usize + n * 4usize;
4755 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5367 } 4756 }
5368 #[doc = "lin break detection length"] 4757 #[doc = "Channel 1 Transfer Complete flag"]
5369 pub const fn lbdl(&self) -> super::vals::Lbdl { 4758 pub fn tcif(&self, n: usize) -> bool {
4759 assert!(n < 7usize);
4760 let offs = 1usize + n * 4usize;
4761 let val = (self.0 >> offs) & 0x01;
4762 val != 0
4763 }
4764 #[doc = "Channel 1 Transfer Complete flag"]
4765 pub fn set_tcif(&mut self, n: usize, val: bool) {
4766 assert!(n < 7usize);
4767 let offs = 1usize + n * 4usize;
4768 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4769 }
4770 #[doc = "Channel 1 Half Transfer Complete flag"]
4771 pub fn htif(&self, n: usize) -> bool {
4772 assert!(n < 7usize);
4773 let offs = 2usize + n * 4usize;
4774 let val = (self.0 >> offs) & 0x01;
4775 val != 0
4776 }
4777 #[doc = "Channel 1 Half Transfer Complete flag"]
4778 pub fn set_htif(&mut self, n: usize, val: bool) {
4779 assert!(n < 7usize);
4780 let offs = 2usize + n * 4usize;
4781 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4782 }
4783 #[doc = "Channel 1 Transfer Error flag"]
4784 pub fn teif(&self, n: usize) -> bool {
4785 assert!(n < 7usize);
4786 let offs = 3usize + n * 4usize;
4787 let val = (self.0 >> offs) & 0x01;
4788 val != 0
4789 }
4790 #[doc = "Channel 1 Transfer Error flag"]
4791 pub fn set_teif(&mut self, n: usize, val: bool) {
4792 assert!(n < 7usize);
4793 let offs = 3usize + n * 4usize;
4794 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4795 }
4796 }
4797 impl Default for Isr {
4798 fn default() -> Isr {
4799 Isr(0)
4800 }
4801 }
4802 }
4803}
4804pub mod rng_v1 {
4805 use crate::generic::*;
4806 #[doc = "Random number generator"]
4807 #[derive(Copy, Clone)]
4808 pub struct Rng(pub *mut u8);
4809 unsafe impl Send for Rng {}
4810 unsafe impl Sync for Rng {}
4811 impl Rng {
4812 #[doc = "control register"]
4813 pub fn cr(self) -> Reg<regs::Cr, RW> {
4814 unsafe { Reg::from_ptr(self.0.add(0usize)) }
4815 }
4816 #[doc = "status register"]
4817 pub fn sr(self) -> Reg<regs::Sr, RW> {
4818 unsafe { Reg::from_ptr(self.0.add(4usize)) }
4819 }
4820 #[doc = "data register"]
4821 pub fn dr(self) -> Reg<u32, R> {
4822 unsafe { Reg::from_ptr(self.0.add(8usize)) }
4823 }
4824 }
4825 pub mod regs {
4826 use crate::generic::*;
4827 #[doc = "status register"]
4828 #[repr(transparent)]
4829 #[derive(Copy, Clone, Eq, PartialEq)]
4830 pub struct Sr(pub u32);
4831 impl Sr {
4832 #[doc = "Data ready"]
4833 pub const fn drdy(&self) -> bool {
4834 let val = (self.0 >> 0usize) & 0x01;
4835 val != 0
4836 }
4837 #[doc = "Data ready"]
4838 pub fn set_drdy(&mut self, val: bool) {
4839 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4840 }
4841 #[doc = "Clock error current status"]
4842 pub const fn cecs(&self) -> bool {
4843 let val = (self.0 >> 1usize) & 0x01;
4844 val != 0
4845 }
4846 #[doc = "Clock error current status"]
4847 pub fn set_cecs(&mut self, val: bool) {
4848 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4849 }
4850 #[doc = "Seed error current status"]
4851 pub const fn secs(&self) -> bool {
4852 let val = (self.0 >> 2usize) & 0x01;
4853 val != 0
4854 }
4855 #[doc = "Seed error current status"]
4856 pub fn set_secs(&mut self, val: bool) {
4857 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4858 }
4859 #[doc = "Clock error interrupt status"]
4860 pub const fn ceis(&self) -> bool {
5370 let val = (self.0 >> 5usize) & 0x01; 4861 let val = (self.0 >> 5usize) & 0x01;
5371 super::vals::Lbdl(val as u8) 4862 val != 0
5372 } 4863 }
5373 #[doc = "lin break detection length"] 4864 #[doc = "Clock error interrupt status"]
5374 pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { 4865 pub fn set_ceis(&mut self, val: bool) {
5375 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); 4866 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
5376 } 4867 }
5377 #[doc = "LIN break detection interrupt enable"] 4868 #[doc = "Seed error interrupt status"]
5378 pub const fn lbdie(&self) -> bool { 4869 pub const fn seis(&self) -> bool {
5379 let val = (self.0 >> 6usize) & 0x01; 4870 let val = (self.0 >> 6usize) & 0x01;
5380 val != 0 4871 val != 0
5381 } 4872 }
5382 #[doc = "LIN break detection interrupt enable"] 4873 #[doc = "Seed error interrupt status"]
5383 pub fn set_lbdie(&mut self, val: bool) { 4874 pub fn set_seis(&mut self, val: bool) {
5384 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); 4875 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
5385 } 4876 }
5386 #[doc = "STOP bits"] 4877 }
5387 pub const fn stop(&self) -> super::vals::Stop { 4878 impl Default for Sr {
5388 let val = (self.0 >> 12usize) & 0x03; 4879 fn default() -> Sr {
5389 super::vals::Stop(val as u8) 4880 Sr(0)
5390 } 4881 }
5391 #[doc = "STOP bits"] 4882 }
5392 pub fn set_stop(&mut self, val: super::vals::Stop) { 4883 #[doc = "control register"]
5393 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); 4884 #[repr(transparent)]
4885 #[derive(Copy, Clone, Eq, PartialEq)]
4886 pub struct Cr(pub u32);
4887 impl Cr {
4888 #[doc = "Random number generator enable"]
4889 pub const fn rngen(&self) -> bool {
4890 let val = (self.0 >> 2usize) & 0x01;
4891 val != 0
5394 } 4892 }
5395 #[doc = "LIN mode enable"] 4893 #[doc = "Random number generator enable"]
5396 pub const fn linen(&self) -> bool { 4894 pub fn set_rngen(&mut self, val: bool) {
5397 let val = (self.0 >> 14usize) & 0x01; 4895 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4896 }
4897 #[doc = "Interrupt enable"]
4898 pub const fn ie(&self) -> bool {
4899 let val = (self.0 >> 3usize) & 0x01;
5398 val != 0 4900 val != 0
5399 } 4901 }
5400 #[doc = "LIN mode enable"] 4902 #[doc = "Interrupt enable"]
5401 pub fn set_linen(&mut self, val: bool) { 4903 pub fn set_ie(&mut self, val: bool) {
5402 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); 4904 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
5403 } 4905 }
5404 } 4906 }
5405 impl Default for Cr2 { 4907 impl Default for Cr {
5406 fn default() -> Cr2 { 4908 fn default() -> Cr {
5407 Cr2(0) 4909 Cr(0)
4910 }
4911 }
4912 }
4913}
4914pub mod dma_v2 {
4915 use crate::generic::*;
4916 #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
4917 #[derive(Copy, Clone)]
4918 pub struct St(pub *mut u8);
4919 unsafe impl Send for St {}
4920 unsafe impl Sync for St {}
4921 impl St {
4922 #[doc = "stream x configuration register"]
4923 pub fn cr(self) -> Reg<regs::Cr, RW> {
4924 unsafe { Reg::from_ptr(self.0.add(0usize)) }
4925 }
4926 #[doc = "stream x number of data register"]
4927 pub fn ndtr(self) -> Reg<regs::Ndtr, RW> {
4928 unsafe { Reg::from_ptr(self.0.add(4usize)) }
4929 }
4930 #[doc = "stream x peripheral address register"]
4931 pub fn par(self) -> Reg<u32, RW> {
4932 unsafe { Reg::from_ptr(self.0.add(8usize)) }
4933 }
4934 #[doc = "stream x memory 0 address register"]
4935 pub fn m0ar(self) -> Reg<u32, RW> {
4936 unsafe { Reg::from_ptr(self.0.add(12usize)) }
4937 }
4938 #[doc = "stream x memory 1 address register"]
4939 pub fn m1ar(self) -> Reg<u32, RW> {
4940 unsafe { Reg::from_ptr(self.0.add(16usize)) }
4941 }
4942 #[doc = "stream x FIFO control register"]
4943 pub fn fcr(self) -> Reg<regs::Fcr, RW> {
4944 unsafe { Reg::from_ptr(self.0.add(20usize)) }
4945 }
4946 }
4947 #[doc = "DMA controller"]
4948 #[derive(Copy, Clone)]
4949 pub struct Dma(pub *mut u8);
4950 unsafe impl Send for Dma {}
4951 unsafe impl Sync for Dma {}
4952 impl Dma {
4953 #[doc = "low interrupt status register"]
4954 pub fn isr(self, n: usize) -> Reg<regs::Isr, R> {
4955 assert!(n < 2usize);
4956 unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
4957 }
4958 #[doc = "low interrupt flag clear register"]
4959 pub fn ifcr(self, n: usize) -> Reg<regs::Ifcr, W> {
4960 assert!(n < 2usize);
4961 unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
4962 }
4963 #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
4964 pub fn st(self, n: usize) -> St {
4965 assert!(n < 8usize);
4966 unsafe { St(self.0.add(16usize + n * 24usize)) }
4967 }
4968 }
4969 pub mod regs {
4970 use crate::generic::*;
4971 #[doc = "stream x FIFO control register"]
4972 #[repr(transparent)]
4973 #[derive(Copy, Clone, Eq, PartialEq)]
4974 pub struct Fcr(pub u32);
4975 impl Fcr {
4976 #[doc = "FIFO threshold selection"]
4977 pub const fn fth(&self) -> super::vals::Fth {
4978 let val = (self.0 >> 0usize) & 0x03;
4979 super::vals::Fth(val as u8)
4980 }
4981 #[doc = "FIFO threshold selection"]
4982 pub fn set_fth(&mut self, val: super::vals::Fth) {
4983 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
4984 }
4985 #[doc = "Direct mode disable"]
4986 pub const fn dmdis(&self) -> super::vals::Dmdis {
4987 let val = (self.0 >> 2usize) & 0x01;
4988 super::vals::Dmdis(val as u8)
4989 }
4990 #[doc = "Direct mode disable"]
4991 pub fn set_dmdis(&mut self, val: super::vals::Dmdis) {
4992 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
4993 }
4994 #[doc = "FIFO status"]
4995 pub const fn fs(&self) -> super::vals::Fs {
4996 let val = (self.0 >> 3usize) & 0x07;
4997 super::vals::Fs(val as u8)
4998 }
4999 #[doc = "FIFO status"]
5000 pub fn set_fs(&mut self, val: super::vals::Fs) {
5001 self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
5002 }
5003 #[doc = "FIFO error interrupt enable"]
5004 pub const fn feie(&self) -> bool {
5005 let val = (self.0 >> 7usize) & 0x01;
5006 val != 0
5007 }
5008 #[doc = "FIFO error interrupt enable"]
5009 pub fn set_feie(&mut self, val: bool) {
5010 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
5011 }
5012 }
5013 impl Default for Fcr {
5014 fn default() -> Fcr {
5015 Fcr(0)
5016 }
5017 }
5018 #[doc = "low interrupt status register"]
5019 #[repr(transparent)]
5020 #[derive(Copy, Clone, Eq, PartialEq)]
5021 pub struct Isr(pub u32);
5022 impl Isr {
5023 #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
5024 pub fn feif(&self, n: usize) -> bool {
5025 assert!(n < 4usize);
5026 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5027 let val = (self.0 >> offs) & 0x01;
5028 val != 0
5029 }
5030 #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
5031 pub fn set_feif(&mut self, n: usize, val: bool) {
5032 assert!(n < 4usize);
5033 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5034 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5035 }
5036 #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
5037 pub fn dmeif(&self, n: usize) -> bool {
5038 assert!(n < 4usize);
5039 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5040 let val = (self.0 >> offs) & 0x01;
5041 val != 0
5042 }
5043 #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
5044 pub fn set_dmeif(&mut self, n: usize, val: bool) {
5045 assert!(n < 4usize);
5046 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5047 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5048 }
5049 #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
5050 pub fn teif(&self, n: usize) -> bool {
5051 assert!(n < 4usize);
5052 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5053 let val = (self.0 >> offs) & 0x01;
5054 val != 0
5055 }
5056 #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
5057 pub fn set_teif(&mut self, n: usize, val: bool) {
5058 assert!(n < 4usize);
5059 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5060 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5061 }
5062 #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
5063 pub fn htif(&self, n: usize) -> bool {
5064 assert!(n < 4usize);
5065 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5066 let val = (self.0 >> offs) & 0x01;
5067 val != 0
5068 }
5069 #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
5070 pub fn set_htif(&mut self, n: usize, val: bool) {
5071 assert!(n < 4usize);
5072 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5073 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5074 }
5075 #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
5076 pub fn tcif(&self, n: usize) -> bool {
5077 assert!(n < 4usize);
5078 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5079 let val = (self.0 >> offs) & 0x01;
5080 val != 0
5081 }
5082 #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
5083 pub fn set_tcif(&mut self, n: usize, val: bool) {
5084 assert!(n < 4usize);
5085 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5086 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5087 }
5088 }
5089 impl Default for Isr {
5090 fn default() -> Isr {
5091 Isr(0)
5092 }
5093 }
5094 #[doc = "stream x number of data register"]
5095 #[repr(transparent)]
5096 #[derive(Copy, Clone, Eq, PartialEq)]
5097 pub struct Ndtr(pub u32);
5098 impl Ndtr {
5099 #[doc = "Number of data items to transfer"]
5100 pub const fn ndt(&self) -> u16 {
5101 let val = (self.0 >> 0usize) & 0xffff;
5102 val as u16
5103 }
5104 #[doc = "Number of data items to transfer"]
5105 pub fn set_ndt(&mut self, val: u16) {
5106 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
5107 }
5108 }
5109 impl Default for Ndtr {
5110 fn default() -> Ndtr {
5111 Ndtr(0)
5112 }
5113 }
5114 #[doc = "stream x configuration register"]
5115 #[repr(transparent)]
5116 #[derive(Copy, Clone, Eq, PartialEq)]
5117 pub struct Cr(pub u32);
5118 impl Cr {
5119 #[doc = "Stream enable / flag stream ready when read low"]
5120 pub const fn en(&self) -> bool {
5121 let val = (self.0 >> 0usize) & 0x01;
5122 val != 0
5123 }
5124 #[doc = "Stream enable / flag stream ready when read low"]
5125 pub fn set_en(&mut self, val: bool) {
5126 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5127 }
5128 #[doc = "Direct mode error interrupt enable"]
5129 pub const fn dmeie(&self) -> bool {
5130 let val = (self.0 >> 1usize) & 0x01;
5131 val != 0
5132 }
5133 #[doc = "Direct mode error interrupt enable"]
5134 pub fn set_dmeie(&mut self, val: bool) {
5135 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
5136 }
5137 #[doc = "Transfer error interrupt enable"]
5138 pub const fn teie(&self) -> bool {
5139 let val = (self.0 >> 2usize) & 0x01;
5140 val != 0
5141 }
5142 #[doc = "Transfer error interrupt enable"]
5143 pub fn set_teie(&mut self, val: bool) {
5144 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
5145 }
5146 #[doc = "Half transfer interrupt enable"]
5147 pub const fn htie(&self) -> bool {
5148 let val = (self.0 >> 3usize) & 0x01;
5149 val != 0
5150 }
5151 #[doc = "Half transfer interrupt enable"]
5152 pub fn set_htie(&mut self, val: bool) {
5153 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
5154 }
5155 #[doc = "Transfer complete interrupt enable"]
5156 pub const fn tcie(&self) -> bool {
5157 let val = (self.0 >> 4usize) & 0x01;
5158 val != 0
5159 }
5160 #[doc = "Transfer complete interrupt enable"]
5161 pub fn set_tcie(&mut self, val: bool) {
5162 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
5163 }
5164 #[doc = "Peripheral flow controller"]
5165 pub const fn pfctrl(&self) -> super::vals::Pfctrl {
5166 let val = (self.0 >> 5usize) & 0x01;
5167 super::vals::Pfctrl(val as u8)
5168 }
5169 #[doc = "Peripheral flow controller"]
5170 pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) {
5171 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
5172 }
5173 #[doc = "Data transfer direction"]
5174 pub const fn dir(&self) -> super::vals::Dir {
5175 let val = (self.0 >> 6usize) & 0x03;
5176 super::vals::Dir(val as u8)
5177 }
5178 #[doc = "Data transfer direction"]
5179 pub fn set_dir(&mut self, val: super::vals::Dir) {
5180 self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize);
5181 }
5182 #[doc = "Circular mode"]
5183 pub const fn circ(&self) -> super::vals::Circ {
5184 let val = (self.0 >> 8usize) & 0x01;
5185 super::vals::Circ(val as u8)
5186 }
5187 #[doc = "Circular mode"]
5188 pub fn set_circ(&mut self, val: super::vals::Circ) {
5189 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
5190 }
5191 #[doc = "Peripheral increment mode"]
5192 pub const fn pinc(&self) -> super::vals::Inc {
5193 let val = (self.0 >> 9usize) & 0x01;
5194 super::vals::Inc(val as u8)
5195 }
5196 #[doc = "Peripheral increment mode"]
5197 pub fn set_pinc(&mut self, val: super::vals::Inc) {
5198 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
5199 }
5200 #[doc = "Memory increment mode"]
5201 pub const fn minc(&self) -> super::vals::Inc {
5202 let val = (self.0 >> 10usize) & 0x01;
5203 super::vals::Inc(val as u8)
5204 }
5205 #[doc = "Memory increment mode"]
5206 pub fn set_minc(&mut self, val: super::vals::Inc) {
5207 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
5208 }
5209 #[doc = "Peripheral data size"]
5210 pub const fn psize(&self) -> super::vals::Size {
5211 let val = (self.0 >> 11usize) & 0x03;
5212 super::vals::Size(val as u8)
5213 }
5214 #[doc = "Peripheral data size"]
5215 pub fn set_psize(&mut self, val: super::vals::Size) {
5216 self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize);
5217 }
5218 #[doc = "Memory data size"]
5219 pub const fn msize(&self) -> super::vals::Size {
5220 let val = (self.0 >> 13usize) & 0x03;
5221 super::vals::Size(val as u8)
5222 }
5223 #[doc = "Memory data size"]
5224 pub fn set_msize(&mut self, val: super::vals::Size) {
5225 self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize);
5226 }
5227 #[doc = "Peripheral increment offset size"]
5228 pub const fn pincos(&self) -> super::vals::Pincos {
5229 let val = (self.0 >> 15usize) & 0x01;
5230 super::vals::Pincos(val as u8)
5231 }
5232 #[doc = "Peripheral increment offset size"]
5233 pub fn set_pincos(&mut self, val: super::vals::Pincos) {
5234 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
5235 }
5236 #[doc = "Priority level"]
5237 pub const fn pl(&self) -> super::vals::Pl {
5238 let val = (self.0 >> 16usize) & 0x03;
5239 super::vals::Pl(val as u8)
5240 }
5241 #[doc = "Priority level"]
5242 pub fn set_pl(&mut self, val: super::vals::Pl) {
5243 self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize);
5244 }
5245 #[doc = "Double buffer mode"]
5246 pub const fn dbm(&self) -> super::vals::Dbm {
5247 let val = (self.0 >> 18usize) & 0x01;
5248 super::vals::Dbm(val as u8)
5249 }
5250 #[doc = "Double buffer mode"]
5251 pub fn set_dbm(&mut self, val: super::vals::Dbm) {
5252 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
5253 }
5254 #[doc = "Current target (only in double buffer mode)"]
5255 pub const fn ct(&self) -> super::vals::Ct {
5256 let val = (self.0 >> 19usize) & 0x01;
5257 super::vals::Ct(val as u8)
5258 }
5259 #[doc = "Current target (only in double buffer mode)"]
5260 pub fn set_ct(&mut self, val: super::vals::Ct) {
5261 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
5262 }
5263 #[doc = "Peripheral burst transfer configuration"]
5264 pub const fn pburst(&self) -> super::vals::Burst {
5265 let val = (self.0 >> 21usize) & 0x03;
5266 super::vals::Burst(val as u8)
5267 }
5268 #[doc = "Peripheral burst transfer configuration"]
5269 pub fn set_pburst(&mut self, val: super::vals::Burst) {
5270 self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize);
5271 }
5272 #[doc = "Memory burst transfer configuration"]
5273 pub const fn mburst(&self) -> super::vals::Burst {
5274 let val = (self.0 >> 23usize) & 0x03;
5275 super::vals::Burst(val as u8)
5276 }
5277 #[doc = "Memory burst transfer configuration"]
5278 pub fn set_mburst(&mut self, val: super::vals::Burst) {
5279 self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize);
5280 }
5281 #[doc = "Channel selection"]
5282 pub const fn chsel(&self) -> u8 {
5283 let val = (self.0 >> 25usize) & 0x0f;
5284 val as u8
5285 }
5286 #[doc = "Channel selection"]
5287 pub fn set_chsel(&mut self, val: u8) {
5288 self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize);
5289 }
5290 }
5291 impl Default for Cr {
5292 fn default() -> Cr {
5293 Cr(0)
5294 }
5295 }
5296 #[doc = "low interrupt flag clear register"]
5297 #[repr(transparent)]
5298 #[derive(Copy, Clone, Eq, PartialEq)]
5299 pub struct Ifcr(pub u32);
5300 impl Ifcr {
5301 #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"]
5302 pub fn cfeif(&self, n: usize) -> bool {
5303 assert!(n < 4usize);
5304 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5305 let val = (self.0 >> offs) & 0x01;
5306 val != 0
5307 }
5308 #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"]
5309 pub fn set_cfeif(&mut self, n: usize, val: bool) {
5310 assert!(n < 4usize);
5311 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5312 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5313 }
5314 #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"]
5315 pub fn cdmeif(&self, n: usize) -> bool {
5316 assert!(n < 4usize);
5317 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5318 let val = (self.0 >> offs) & 0x01;
5319 val != 0
5320 }
5321 #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"]
5322 pub fn set_cdmeif(&mut self, n: usize, val: bool) {
5323 assert!(n < 4usize);
5324 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5325 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5326 }
5327 #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"]
5328 pub fn cteif(&self, n: usize) -> bool {
5329 assert!(n < 4usize);
5330 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5331 let val = (self.0 >> offs) & 0x01;
5332 val != 0
5333 }
5334 #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"]
5335 pub fn set_cteif(&mut self, n: usize, val: bool) {
5336 assert!(n < 4usize);
5337 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5338 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5339 }
5340 #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"]
5341 pub fn chtif(&self, n: usize) -> bool {
5342 assert!(n < 4usize);
5343 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5344 let val = (self.0 >> offs) & 0x01;
5345 val != 0
5346 }
5347 #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"]
5348 pub fn set_chtif(&mut self, n: usize, val: bool) {
5349 assert!(n < 4usize);
5350 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5351 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5352 }
5353 #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"]
5354 pub fn ctcif(&self, n: usize) -> bool {
5355 assert!(n < 4usize);
5356 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5357 let val = (self.0 >> offs) & 0x01;
5358 val != 0
5359 }
5360 #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"]
5361 pub fn set_ctcif(&mut self, n: usize, val: bool) {
5362 assert!(n < 4usize);
5363 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
5364 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5365 }
5366 }
5367 impl Default for Ifcr {
5368 fn default() -> Ifcr {
5369 Ifcr(0)
5408 } 5370 }
5409 } 5371 }
5410 } 5372 }
@@ -5412,106 +5374,144 @@ pub mod usart_v1 {
5412 use crate::generic::*; 5374 use crate::generic::*;
5413 #[repr(transparent)] 5375 #[repr(transparent)]
5414 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 5376 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5415 pub struct Cpol(pub u8); 5377 pub struct Pfctrl(pub u8);
5416 impl Cpol { 5378 impl Pfctrl {
5417 #[doc = "Steady low value on CK pin outside transmission window"] 5379 #[doc = "The DMA is the flow controller"]
5418 pub const LOW: Self = Self(0); 5380 pub const DMA: Self = Self(0);
5419 #[doc = "Steady high value on CK pin outside transmission window"] 5381 #[doc = "The peripheral is the flow controller"]
5420 pub const HIGH: Self = Self(0x01); 5382 pub const PERIPHERAL: Self = Self(0x01);
5421 } 5383 }
5422 #[repr(transparent)] 5384 #[repr(transparent)]
5423 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 5385 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5424 pub struct Stop(pub u8); 5386 pub struct Size(pub u8);
5425 impl Stop { 5387 impl Size {
5426 #[doc = "1 stop bit"] 5388 #[doc = "Byte (8-bit)"]
5427 pub const STOP1: Self = Self(0); 5389 pub const BITS8: Self = Self(0);
5428 #[doc = "0.5 stop bits"] 5390 #[doc = "Half-word (16-bit)"]
5429 pub const STOP0P5: Self = Self(0x01); 5391 pub const BITS16: Self = Self(0x01);
5430 #[doc = "2 stop bits"] 5392 #[doc = "Word (32-bit)"]
5431 pub const STOP2: Self = Self(0x02); 5393 pub const BITS32: Self = Self(0x02);
5432 #[doc = "1.5 stop bits"]
5433 pub const STOP1P5: Self = Self(0x03);
5434 } 5394 }
5435 #[repr(transparent)] 5395 #[repr(transparent)]
5436 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 5396 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5437 pub struct Rwu(pub u8); 5397 pub struct Dbm(pub u8);
5438 impl Rwu { 5398 impl Dbm {
5439 #[doc = "Receiver in active mode"] 5399 #[doc = "No buffer switching at the end of transfer"]
5440 pub const ACTIVE: Self = Self(0); 5400 pub const DISABLED: Self = Self(0);
5441 #[doc = "Receiver in mute mode"] 5401 #[doc = "Memory target switched at the end of the DMA transfer"]
5442 pub const MUTE: Self = Self(0x01); 5402 pub const ENABLED: Self = Self(0x01);
5443 } 5403 }
5444 #[repr(transparent)] 5404 #[repr(transparent)]
5445 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 5405 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5446 pub struct Sbk(pub u8); 5406 pub struct Dir(pub u8);
5447 impl Sbk { 5407 impl Dir {
5448 #[doc = "No break character is transmitted"] 5408 #[doc = "Peripheral-to-memory"]
5449 pub const NOBREAK: Self = Self(0); 5409 pub const PERIPHERALTOMEMORY: Self = Self(0);
5450 #[doc = "Break character transmitted"] 5410 #[doc = "Memory-to-peripheral"]
5451 pub const BREAK: Self = Self(0x01); 5411 pub const MEMORYTOPERIPHERAL: Self = Self(0x01);
5412 #[doc = "Memory-to-memory"]
5413 pub const MEMORYTOMEMORY: Self = Self(0x02);
5452 } 5414 }
5453 #[repr(transparent)] 5415 #[repr(transparent)]
5454 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 5416 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5455 pub struct M(pub u8); 5417 pub struct Pincos(pub u8);
5456 impl M { 5418 impl Pincos {
5457 #[doc = "8 data bits"] 5419 #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"]
5458 pub const M8: Self = Self(0); 5420 pub const PSIZE: Self = Self(0);
5459 #[doc = "9 data bits"] 5421 #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"]
5460 pub const M9: Self = Self(0x01); 5422 pub const FIXED4: Self = Self(0x01);
5461 } 5423 }
5462 #[repr(transparent)] 5424 #[repr(transparent)]
5463 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 5425 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5464 pub struct Lbdl(pub u8); 5426 pub struct Burst(pub u8);
5465 impl Lbdl { 5427 impl Burst {
5466 #[doc = "10-bit break detection"] 5428 #[doc = "Single transfer"]
5467 pub const LBDL10: Self = Self(0); 5429 pub const SINGLE: Self = Self(0);
5468 #[doc = "11-bit break detection"] 5430 #[doc = "Incremental burst of 4 beats"]
5469 pub const LBDL11: Self = Self(0x01); 5431 pub const INCR4: Self = Self(0x01);
5432 #[doc = "Incremental burst of 8 beats"]
5433 pub const INCR8: Self = Self(0x02);
5434 #[doc = "Incremental burst of 16 beats"]
5435 pub const INCR16: Self = Self(0x03);
5470 } 5436 }
5471 #[repr(transparent)] 5437 #[repr(transparent)]
5472 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 5438 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5473 pub struct Cpha(pub u8); 5439 pub struct Ct(pub u8);
5474 impl Cpha { 5440 impl Ct {
5475 #[doc = "The first clock transition is the first data capture edge"] 5441 #[doc = "The current target memory is Memory 0"]
5476 pub const FIRST: Self = Self(0); 5442 pub const MEMORY0: Self = Self(0);
5477 #[doc = "The second clock transition is the first data capture edge"] 5443 #[doc = "The current target memory is Memory 1"]
5478 pub const SECOND: Self = Self(0x01); 5444 pub const MEMORY1: Self = Self(0x01);
5479 } 5445 }
5480 #[repr(transparent)] 5446 #[repr(transparent)]
5481 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 5447 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5482 pub struct Hdsel(pub u8); 5448 pub struct Fs(pub u8);
5483 impl Hdsel { 5449 impl Fs {
5484 #[doc = "Half duplex mode is not selected"] 5450 #[doc = "0 < fifo_level < 1/4"]
5485 pub const FULLDUPLEX: Self = Self(0); 5451 pub const QUARTER1: Self = Self(0);
5486 #[doc = "Half duplex mode is selected"] 5452 #[doc = "1/4 <= fifo_level < 1/2"]
5487 pub const HALFDUPLEX: Self = Self(0x01); 5453 pub const QUARTER2: Self = Self(0x01);
5454 #[doc = "1/2 <= fifo_level < 3/4"]
5455 pub const QUARTER3: Self = Self(0x02);
5456 #[doc = "3/4 <= fifo_level < full"]
5457 pub const QUARTER4: Self = Self(0x03);
5458 #[doc = "FIFO is empty"]
5459 pub const EMPTY: Self = Self(0x04);
5460 #[doc = "FIFO is full"]
5461 pub const FULL: Self = Self(0x05);
5488 } 5462 }
5489 #[repr(transparent)] 5463 #[repr(transparent)]
5490 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 5464 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5491 pub struct Wake(pub u8); 5465 pub struct Fth(pub u8);
5492 impl Wake { 5466 impl Fth {
5493 #[doc = "USART wakeup on idle line"] 5467 #[doc = "1/4 full FIFO"]
5494 pub const IDLELINE: Self = Self(0); 5468 pub const QUARTER: Self = Self(0);
5495 #[doc = "USART wakeup on address mark"] 5469 #[doc = "1/2 full FIFO"]
5496 pub const ADDRESSMARK: Self = Self(0x01); 5470 pub const HALF: Self = Self(0x01);
5471 #[doc = "3/4 full FIFO"]
5472 pub const THREEQUARTERS: Self = Self(0x02);
5473 #[doc = "Full FIFO"]
5474 pub const FULL: Self = Self(0x03);
5497 } 5475 }
5498 #[repr(transparent)] 5476 #[repr(transparent)]
5499 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 5477 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5500 pub struct Irlp(pub u8); 5478 pub struct Inc(pub u8);
5501 impl Irlp { 5479 impl Inc {
5502 #[doc = "Normal mode"] 5480 #[doc = "Address pointer is fixed"]
5503 pub const NORMAL: Self = Self(0); 5481 pub const FIXED: Self = Self(0);
5504 #[doc = "Low-power mode"] 5482 #[doc = "Address pointer is incremented after each data transfer"]
5505 pub const LOWPOWER: Self = Self(0x01); 5483 pub const INCREMENTED: Self = Self(0x01);
5506 } 5484 }
5507 #[repr(transparent)] 5485 #[repr(transparent)]
5508 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 5486 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5509 pub struct Ps(pub u8); 5487 pub struct Pl(pub u8);
5510 impl Ps { 5488 impl Pl {
5511 #[doc = "Even parity"] 5489 #[doc = "Low"]
5512 pub const EVEN: Self = Self(0); 5490 pub const LOW: Self = Self(0);
5513 #[doc = "Odd parity"] 5491 #[doc = "Medium"]
5514 pub const ODD: Self = Self(0x01); 5492 pub const MEDIUM: Self = Self(0x01);
5493 #[doc = "High"]
5494 pub const HIGH: Self = Self(0x02);
5495 #[doc = "Very high"]
5496 pub const VERYHIGH: Self = Self(0x03);
5497 }
5498 #[repr(transparent)]
5499 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5500 pub struct Circ(pub u8);
5501 impl Circ {
5502 #[doc = "Circular mode disabled"]
5503 pub const DISABLED: Self = Self(0);
5504 #[doc = "Circular mode enabled"]
5505 pub const ENABLED: Self = Self(0x01);
5506 }
5507 #[repr(transparent)]
5508 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
5509 pub struct Dmdis(pub u8);
5510 impl Dmdis {
5511 #[doc = "Direct mode is enabled"]
5512 pub const ENABLED: Self = Self(0);
5513 #[doc = "Direct mode is disabled"]
5514 pub const DISABLED: Self = Self(0x01);
5515 } 5515 }
5516 } 5516 }
5517} 5517}
diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs
index f3f0ce1fa..d1419dfd7 100644
--- a/embassy-stm32/src/rng.rs
+++ b/embassy-stm32/src/rng.rs
@@ -1,3 +1,4 @@
1#![macro_use]
1use crate::pac::rng::{regs, Rng}; 2use crate::pac::rng::{regs, Rng};
2use crate::peripherals; 3use crate::peripherals;
3use embassy::util::Unborrow; 4use embassy::util::Unborrow;
diff --git a/embassy-stm32/src/usart.rs b/embassy-stm32/src/usart.rs
index 2232ac57e..a49383bc9 100644
--- a/embassy-stm32/src/usart.rs
+++ b/embassy-stm32/src/usart.rs
@@ -1,3 +1,5 @@
1#![macro_use]
2
1use core::marker::PhantomData; 3use core::marker::PhantomData;
2 4
3use embassy::util::Unborrow; 5use embassy::util::Unborrow;
generated by cgit (git 2.34.1) at 2026-04-07 16:21:57 +0000