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| author | Ulf Lilleengen <[email protected]> | 2021-06-08 17:37:41 +0200 |
|---|---|---|
| committer | Ulf Lilleengen <[email protected]> | 2021-06-08 17:37:41 +0200 |
| commit | f7394e56ef6275ffc528e68ff6532dc14a976611 (patch) | |
| tree | b739b2a4809b113a54f5b273086a26d77dbc6462 | |
| parent | 6e63bf7e4462db75d88cc76b1bbf52cbbced320c (diff) | |
Handle other L4 variants
| -rw-r--r-- | stm32-metapac/build.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/stm32-metapac/build.rs b/stm32-metapac/build.rs index 72750267d..008c9eb37 100644 --- a/stm32-metapac/build.rs +++ b/stm32-metapac/build.rs | |||
| @@ -225,7 +225,7 @@ fn main() { | |||
| 225 | let (enable_reg, reset_reg) = if chip.family == "STM32H7" && clock == "APB1" | 225 | let (enable_reg, reset_reg) = if chip.family == "STM32H7" && clock == "APB1" |
| 226 | { | 226 | { |
| 227 | (format!("{}lenr", reg), format!("{}lrstr", reg)) | 227 | (format!("{}lenr", reg), format!("{}lrstr", reg)) |
| 228 | } else if chip.family == "STM32L4" && clock == "APB1" { | 228 | } else if chip.family.starts_with("STM32L4") && clock == "APB1" { |
| 229 | (format!("{}enr1", reg), format!("{}rstr1", reg)) | 229 | (format!("{}enr1", reg), format!("{}rstr1", reg)) |
| 230 | } else { | 230 | } else { |
| 231 | (format!("{}enr", reg), format!("{}rstr", reg)) | 231 | (format!("{}enr", reg), format!("{}rstr", reg)) |