Merge branch 'main' into i2c

44 files changed, 1478 insertions, 534 deletions

diff --git a/embassy-executor/CHANGELOG.md b/embassy-executor/CHANGELOG.md
index 47a8ae995..5fbb8cf13 100644
--- a/embassy-executor/CHANGELOG.md
+++ b/embassy-executor/CHANGELOG.md
@@ -13,7 +13,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Upgraded rtos-trace
 - Added optional "highest priority" scheduling
 - Added optional "earliest deadline first" EDF scheduling
-- Bump `cortex-ar` to v0.3
+- Migrate `cortex-ar` to `aarch32-cpu`. The feature name `arch-cortex-ar` remains the same and
+  legacy ARM architectures are not supported.
 
 ## 0.9.1 - 2025-08-31
 
diff --git a/embassy-executor/Cargo.toml b/embassy-executor/Cargo.toml
index e500833c0..d3e5b241a 100644
--- a/embassy-executor/Cargo.toml
+++ b/embassy-executor/Cargo.toml
@@ -102,7 +102,7 @@ portable-atomic = { version = "1.5", optional = true }
 cortex-m = { version = "0.7.6", optional = true }
 
 # arch-cortex-ar dependencies
-cortex-ar = { version = "0.3", optional = true }
+aarch32-cpu = { version = "0.1", optional = true }
 
 # arch-wasm dependencies
 wasm-bindgen = { version = "0.2.82", optional = true }
@@ -130,7 +130,7 @@ nightly = ["embassy-executor-macros/nightly"]
 ## Enable defmt logging
 defmt = ["dep:defmt"]
 
-## Enable log logging  
+## Enable log logging
 log = ["dep:log"]
 
 # Enables turbo wakers, which requires patching core. Not surfaced in the docs by default due to
@@ -145,7 +145,7 @@ arch-std = ["_arch"]
 ## Cortex-M
 arch-cortex-m = ["_arch", "dep:cortex-m"]
 ## Cortex-A/R
-arch-cortex-ar = ["_arch", "dep:cortex-ar"]
+arch-cortex-ar = ["_arch", "dep:aarch32-cpu", "dep:arm-targets"]
 ## RISC-V 32
 arch-riscv32 = ["_arch"]
 ## WASM
@@ -182,3 +182,6 @@ scheduler-priority = []
 ## Enable the embassy_time_driver dependency.
 ## This can unlock extra APIs, for example for the `sheduler-deadline`
 embassy-time-driver = ["dep:embassy-time-driver"]
+
+[build-dependencies]
+arm-targets = { version = "0.4", optional = true }
diff --git a/embassy-executor/build.rs b/embassy-executor/build.rs
index 37becde3e..36e23a632 100644
--- a/embassy-executor/build.rs
+++ b/embassy-executor/build.rs
@@ -4,4 +4,9 @@ mod common;
 fn main() {
     let mut rustc_cfgs = common::CfgSet::new();
     common::set_target_cfgs(&mut rustc_cfgs);
+
+    // This is used to exclude legacy architecture support. The raw executor needs to be used for
+    // those architectures because SEV/WFE are not supported.
+    #[cfg(feature = "arch-cortex-ar")]
+    arm_targets::process();
 }
diff --git a/embassy-executor/src/arch/cortex_ar.rs b/embassy-executor/src/arch/cortex_ar.rs
index a9be3d323..ce572738a 100644
--- a/embassy-executor/src/arch/cortex_ar.rs
+++ b/embassy-executor/src/arch/cortex_ar.rs
@@ -1,3 +1,6 @@
+#[cfg(arm_profile = "legacy")]
+compile_error!("`arch-cortex-ar` does not support the legacy ARM profile, WFE/SEV are not available.");
+
 #[cfg(feature = "executor-interrupt")]
 compile_error!("`executor-interrupt` is not supported with `arch-cortex-ar`.");
 
@@ -10,7 +13,7 @@ fn __pender(context: *mut ()) {
     #[cfg(feature = "executor-thread")]
     // Try to make Rust optimize the branching away if we only use thread mode.
     if !cfg!(feature = "executor-interrupt") || context == THREAD_PENDER {
-        cortex_ar::asm::sev();
+        aarch32_cpu::asm::sev();
         return;
     }
 }
@@ -23,7 +26,7 @@ mod thread {
 
     use core::marker::PhantomData;
 
-    use cortex_ar::asm::wfe;
+    use aarch32_cpu::asm::wfe;
     pub use embassy_executor_macros::main_cortex_ar as main;
 
     use crate::{Spawner, raw};
diff --git a/embassy-rp/CHANGELOG.md b/embassy-rp/CHANGELOG.md
index 57ec13658..3b3cb5351 100644
--- a/embassy-rp/CHANGELOG.md
+++ b/embassy-rp/CHANGELOG.md
@@ -15,6 +15,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - add `wait_for_alarm` and `alarm_scheduled` methods to rtc module ([#4216](https://github.com/embassy-rs/embassy/pull/4216))
 - rp235x: use msplim for stack guard instead of MPU
 - Add reset_to_usb_boot for rp235x ([#4705](https://github.com/embassy-rs/embassy/pull/4705))
+- Add fix #4822 in PIO onewire. Change to disable the state machine before setting y register ([#4824](https://github.com/embassy-rs/embassy/pull/4824))
+- Add PIO::Ws2812 color order support
 
 ## 0.8.0 - 2025-08-26
 
diff --git a/embassy-rp/src/pio_programs/onewire.rs b/embassy-rp/src/pio_programs/onewire.rs
index 09babc229..3adab3b79 100644
--- a/embassy-rp/src/pio_programs/onewire.rs
+++ b/embassy-rp/src/pio_programs/onewire.rs
@@ -163,7 +163,11 @@ impl<'d, PIO: Instance, const SM: usize> PioOneWire<'d, PIO, SM> {
 
     /// Write bytes to the onewire bus
     pub async fn write_bytes(&mut self, data: &[u8]) {
-        unsafe { self.sm.set_y(u32::MAX as u32) };
+        unsafe {
+            self.sm.set_enable(false);
+            self.sm.set_y(u32::MAX as u32);
+            self.sm.set_enable(true);
+        }
         let (rx, tx) = self.sm.rx_tx();
         for b in data {
             tx.wait_push(*b as u32).await;
@@ -175,7 +179,11 @@ impl<'d, PIO: Instance, const SM: usize> PioOneWire<'d, PIO, SM> {
 
     /// Write bytes to the onewire bus, then apply a strong pullup
     pub async fn write_bytes_pullup(&mut self, data: &[u8], pullup_time: embassy_time::Duration) {
-        unsafe { self.sm.set_y(data.len() as u32 * 8 - 1) };
+        unsafe {
+            self.sm.set_enable(false);
+            self.sm.set_y(data.len() as u32 * 8 - 1);
+            self.sm.set_enable(true);
+        };
         let (rx, tx) = self.sm.rx_tx();
         for b in data {
             tx.wait_push(*b as u32).await;
@@ -195,7 +203,11 @@ impl<'d, PIO: Instance, const SM: usize> PioOneWire<'d, PIO, SM> {
 
     /// Read bytes from the onewire bus
     pub async fn read_bytes(&mut self, data: &mut [u8]) {
-        unsafe { self.sm.set_y(u32::MAX as u32) };
+        unsafe {
+            self.sm.set_enable(false);
+            self.sm.set_y(u32::MAX as u32);
+            self.sm.set_enable(true);
+        };
         let (rx, tx) = self.sm.rx_tx();
         for b in data {
             // Write all 1's so that we can read what the device responds
diff --git a/embassy-rp/src/pio_programs/ws2812.rs b/embassy-rp/src/pio_programs/ws2812.rs
index e6851b1a6..0b6035316 100644
--- a/embassy-rp/src/pio_programs/ws2812.rs
+++ b/embassy-rp/src/pio_programs/ws2812.rs
@@ -1,4 +1,4 @@
-//! [ws2812](https://www.sparkfun.com/datasheets/LCD/HD44780.pdf)
+//! [ws2812](https://www.sparkfun.com/categories/tags/ws2812)
 
 use embassy_time::Timer;
 use fixed::types::U24F8;
@@ -16,6 +16,54 @@ const T2: u8 = 5; // data bit
 const T3: u8 = 3; // stop bit
 const CYCLES_PER_BIT: u32 = (T1 + T2 + T3) as u32;
 
+/// Color orders for WS2812B, type RGB8
+pub trait RgbColorOrder {
+    /// Pack an 8-bit RGB color into a u32
+    fn pack(color: RGB8) -> u32;
+}
+
+/// Green, Red, Blue order is the common default for WS2812B
+pub struct Grb;
+impl RgbColorOrder for Grb {
+    /// Pack an 8-bit RGB color into a u32 in GRB order
+    fn pack(color: RGB8) -> u32 {
+        (u32::from(color.g) << 24) | (u32::from(color.r) << 16) | (u32::from(color.b) << 8)
+    }
+}
+
+/// Red, Green, Blue is used by some WS2812B implementations
+pub struct Rgb;
+impl RgbColorOrder for Rgb {
+    /// Pack an 8-bit RGB color into a u32 in RGB order
+    fn pack(color: RGB8) -> u32 {
+        (u32::from(color.r) << 24) | (u32::from(color.g) << 16) | (u32::from(color.b) << 8)
+    }
+}
+
+/// Color orders RGBW strips
+pub trait RgbwColorOrder {
+    /// Pack an RGB+W color into a u32
+    fn pack(color: RGBW<u8>) -> u32;
+}
+
+/// Green, Red, Blue, White order is the common default for RGBW strips
+pub struct Grbw;
+impl RgbwColorOrder for Grbw {
+    /// Pack an RGB+W color into a u32 in GRBW order
+    fn pack(color: RGBW<u8>) -> u32 {
+        (u32::from(color.g) << 24) | (u32::from(color.r) << 16) | (u32::from(color.b) << 8) | u32::from(color.a.0)
+    }
+}
+
+/// Red, Green, Blue, White order
+pub struct Rgbw;
+impl RgbwColorOrder for Rgbw {
+    /// Pack an RGB+W color into a u32 in RGBW order
+    fn pack(color: RGBW<u8>) -> u32 {
+        (u32::from(color.r) << 24) | (u32::from(color.g) << 16) | (u32::from(color.b) << 8) | u32::from(color.a.0)
+    }
+}
+
 /// This struct represents a ws2812 program loaded into pio instruction memory.
 pub struct PioWs2812Program<'a, PIO: Instance> {
     prg: LoadedProgram<'a, PIO>,
@@ -52,15 +100,37 @@ impl<'a, PIO: Instance> PioWs2812Program<'a, PIO> {
 
 /// Pio backed RGB ws2812 driver
 /// Const N is the number of ws2812 leds attached to this pin
-pub struct PioWs2812<'d, P: Instance, const S: usize, const N: usize> {
+pub struct PioWs2812<'d, P: Instance, const S: usize, const N: usize, ORDER>
+where
+    ORDER: RgbColorOrder,
+{
     dma: Peri<'d, AnyChannel>,
     sm: StateMachine<'d, P, S>,
+    _order: core::marker::PhantomData<ORDER>,
 }
 
-impl<'d, P: Instance, const S: usize, const N: usize> PioWs2812<'d, P, S, N> {
+impl<'d, P: Instance, const S: usize, const N: usize> PioWs2812<'d, P, S, N, Grb> {
     /// Configure a pio state machine to use the loaded ws2812 program.
+    /// Uses the default GRB order.
     pub fn new(
         pio: &mut Common<'d, P>,
+        sm: StateMachine<'d, P, S>,
+        dma: Peri<'d, impl Channel>,
+        pin: Peri<'d, impl PioPin>,
+        program: &PioWs2812Program<'d, P>,
+    ) -> Self {
+        Self::with_color_order(pio, sm, dma, pin, program)
+    }
+}
+
+impl<'d, P: Instance, const S: usize, const N: usize, ORDER> PioWs2812<'d, P, S, N, ORDER>
+where
+    ORDER: RgbColorOrder,
+{
+    /// Configure a pio state machine to use the loaded ws2812 program.
+    /// Uses the specified color order.
+    pub fn with_color_order(
+        pio: &mut Common<'d, P>,
         mut sm: StateMachine<'d, P, S>,
         dma: Peri<'d, impl Channel>,
         pin: Peri<'d, impl PioPin>,
@@ -93,7 +163,11 @@ impl<'d, P: Instance, const S: usize, const N: usize> PioWs2812<'d, P, S, N> {
         sm.set_config(&cfg);
         sm.set_enable(true);
 
-        Self { dma: dma.into(), sm }
+        Self {
+            dma: dma.into(),
+            sm,
+            _order: core::marker::PhantomData,
+        }
     }
 
     /// Write a buffer of [smart_leds::RGB8] to the ws2812 string
@@ -101,8 +175,7 @@ impl<'d, P: Instance, const S: usize, const N: usize> PioWs2812<'d, P, S, N> {
         // Precompute the word bytes from the colors
         let mut words = [0u32; N];
         for i in 0..N {
-            let word = (u32::from(colors[i].g) << 24) | (u32::from(colors[i].r) << 16) | (u32::from(colors[i].b) << 8);
-            words[i] = word;
+            words[i] = ORDER::pack(colors[i]);
         }
 
         // DMA transfer
@@ -115,15 +188,37 @@ impl<'d, P: Instance, const S: usize, const N: usize> PioWs2812<'d, P, S, N> {
 /// Pio backed RGBW ws2812 driver
 /// This version is intended for ws2812 leds with 4 addressable lights
 /// Const N is the number of ws2812 leds attached to this pin
-pub struct RgbwPioWs2812<'d, P: Instance, const S: usize, const N: usize> {
+pub struct RgbwPioWs2812<'d, P: Instance, const S: usize, const N: usize, ORDER>
+where
+    ORDER: RgbwColorOrder,
+{
     dma: Peri<'d, AnyChannel>,
     sm: StateMachine<'d, P, S>,
+    _order: core::marker::PhantomData<ORDER>,
 }
 
-impl<'d, P: Instance, const S: usize, const N: usize> RgbwPioWs2812<'d, P, S, N> {
+impl<'d, P: Instance, const S: usize, const N: usize> RgbwPioWs2812<'d, P, S, N, Grbw> {
     /// Configure a pio state machine to use the loaded ws2812 program.
+    /// Uses the default GRBW color order
     pub fn new(
         pio: &mut Common<'d, P>,
+        sm: StateMachine<'d, P, S>,
+        dma: Peri<'d, impl Channel>,
+        pin: Peri<'d, impl PioPin>,
+        program: &PioWs2812Program<'d, P>,
+    ) -> Self {
+        Self::with_color_order(pio, sm, dma, pin, program)
+    }
+}
+
+impl<'d, P: Instance, const S: usize, const N: usize, ORDER> RgbwPioWs2812<'d, P, S, N, ORDER>
+where
+    ORDER: RgbwColorOrder,
+{
+    /// Configure a pio state machine to use the loaded ws2812 program.
+    /// Uses the specified color order
+    pub fn with_color_order(
+        pio: &mut Common<'d, P>,
         mut sm: StateMachine<'d, P, S>,
         dma: Peri<'d, impl Channel>,
         pin: Peri<'d, impl PioPin>,
@@ -156,7 +251,11 @@ impl<'d, P: Instance, const S: usize, const N: usize> RgbwPioWs2812<'d, P, S, N>
         sm.set_config(&cfg);
         sm.set_enable(true);
 
-        Self { dma: dma.into(), sm }
+        Self {
+            dma: dma.into(),
+            sm,
+            _order: core::marker::PhantomData,
+        }
     }
 
     /// Write a buffer of [smart_leds::RGBW] to the ws2812 string
@@ -164,11 +263,7 @@ impl<'d, P: Instance, const S: usize, const N: usize> RgbwPioWs2812<'d, P, S, N>
         // Precompute the word bytes from the colors
         let mut words = [0u32; N];
         for i in 0..N {
-            let word = (u32::from(colors[i].g) << 24)
-                | (u32::from(colors[i].r) << 16)
-                | (u32::from(colors[i].b) << 8)
-                | u32::from(colors[i].a.0);
-            words[i] = word;
+            words[i] = ORDER::pack(colors[i]);
         }
 
         // DMA transfer
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 8b215f13b..3d6a41f14 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -5,10 +5,6 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-<!-- next-header -->
-### [Unreleased]
-
-* **Fix(stm32h5):** Prevent a HardFault crash on STM32H5 devices by changing `uid()` to return `[u8; 12]` by value instead of a reference. (Fixes #2696)
 ## Unreleased - ReleaseDate
 
 - fix flash erase on L4 & L5
@@ -35,10 +31,17 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - feat: stm32/usart: add `eager_reads` option to control if buffered readers return as soon as possible or after more data is available ([#4668](https://github.com/embassy-rs/embassy/pull/4668))
 - feat: stm32/usart: add `de_assertion_time` and `de_deassertion_time` config options
 - change: stm32/uart: BufferedUartRx now returns all available bytes from the internal buffer
+- fix: Prevent a HardFault crash on STM32H5 devices by changing `uid()` to return `[u8; 12]` by value instead of a reference. (Fixes #2696)
 - change: timer: added output compare values
 - feat: timer: add ability to set master mode
+- fix: sdmmc: don't wait for DBCKEND flag on sdmmc_v2 devices as it never fires (Fixes #4723)
 - fix: usart: fix race condition in ringbuffered usart
 - feat: Add I2C MultiMaster (Slave) support for I2C v1
+- feat: stm32/fdcan: add ability to control automatic recovery from bus off ([#4821](https://github.com/embassy-rs/embassy/pull/4821))
+- low-power: update rtc api to allow reconfig
+- adc: consolidate ringbuffer
+- feat: Added RTC low-power support for STM32WLEx ([#4716](https://github.com/embassy-rs/embassy/pull/4716))
+- fix: Correct STM32WBA VREFBUFTRIM values
 
 ## 0.4.0 - 2025-08-26
 
@@ -51,6 +54,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - chore: Updated stm32-metapac and stm32-data dependencies
 - feat: stm32/adc/v3: allow DMA reads to loop through enable channels
 - fix: Fix XSPI not disabling alternate bytes when they were previously enabled
+- feat: stm32/adc/v3: added support for Continuous DMA configuration 
 - fix: Fix stm32h7rs init when using external flash via XSPI
 - feat: Add Adc::new_with_clock() to configure analog clock
 - feat: Add GPDMA linked-list + ringbuffer support ([#3923](https://github.com/embassy-rs/embassy/pull/3923))
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 22ed8295f..ea7341f75 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -87,14 +87,18 @@ pub(crate) trait SealedAdcChannel<T> {
 /// Performs a busy-wait delay for a specified number of microseconds.
 #[allow(unused)]
 pub(crate) fn blocking_delay_us(us: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(embassy_time::Duration::from_micros(us as u64));
-    #[cfg(not(feature = "time"))]
-    {
-        let freq = unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 as u64;
-        let us = us as u64;
-        let cycles = freq * us / 1_000_000;
-        cortex_m::asm::delay(cycles as u32);
+    cfg_if::cfg_if! {
+        // this does strange things on stm32wlx in low power mode depending on exactly when it's called
+        // as in sometimes 15 us (1 tick) would take > 20 seconds.
+        if #[cfg(all(feature = "time", all(not(feature = "low-power"), not(stm32wlex))))] {
+            let duration = embassy_time::Duration::from_micros(us as u64);
+            embassy_time::block_for(duration);
+        } else {
+            let freq = unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 as u64;
+            let us = us as u64;
+            let cycles = freq * us / 1_000_000;
+            cortex_m::asm::delay(cycles as u32);
+        }
     }
 }
 
diff --git a/embassy-stm32/src/adc/ringbuffered.rs b/embassy-stm32/src/adc/ringbuffered.rs
new file mode 100644
index 000000000..1f384efb5
--- /dev/null
+++ b/embassy-stm32/src/adc/ringbuffered.rs
@@ -0,0 +1,179 @@
+use core::marker::PhantomData;
+use core::sync::atomic::{Ordering, compiler_fence};
+
+#[allow(unused_imports)]
+use embassy_hal_internal::Peri;
+
+use crate::adc::Adc;
+#[allow(unused_imports)]
+use crate::adc::{Instance, RxDma};
+#[allow(unused_imports)]
+use crate::dma::{ReadableRingBuffer, TransferOptions};
+use crate::rcc;
+
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct OverrunError;
+
+pub struct RingBufferedAdc<'d, T: Instance> {
+    _phantom: PhantomData<T>,
+    ring_buf: ReadableRingBuffer<'d, u16>,
+}
+
+impl<'d, T: Instance> RingBufferedAdc<'d, T> {
+    pub(crate) fn new(dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> Self {
+        //dma side setup
+        let opts = TransferOptions {
+            half_transfer_ir: true,
+            circular: true,
+            ..Default::default()
+        };
+
+        // Safety: we forget the struct before this function returns.
+        let request = dma.request();
+
+        let ring_buf =
+            unsafe { ReadableRingBuffer::new(dma, request, T::regs().dr().as_ptr() as *mut u16, dma_buf, opts) };
+
+        Self {
+            _phantom: PhantomData,
+            ring_buf,
+        }
+    }
+
+    /// Turns on ADC if it is not already turned on and starts continuous DMA transfer.
+    pub fn start(&mut self) {
+        compiler_fence(Ordering::SeqCst);
+        self.ring_buf.start();
+
+        Adc::<T>::start();
+    }
+
+    pub fn stop(&mut self) {
+        Adc::<T>::stop();
+
+        self.ring_buf.request_pause();
+
+        compiler_fence(Ordering::SeqCst);
+    }
+
+    pub fn clear(&mut self) {
+        self.ring_buf.clear();
+    }
+
+    /// Reads measurements from the DMA ring buffer.
+    ///
+    /// This method fills the provided `measurements` array with ADC readings from the DMA buffer.
+    /// The length of the `measurements` array should be exactly half of the DMA buffer length. Because interrupts are only generated if half or full DMA transfer completes.
+    ///
+    /// Each call to `read` will populate the `measurements` array in the same order as the channels defined with `sequence`.
+    /// There will be many sequences worth of measurements in this array because it only returns if at least half of the DMA buffer is filled.
+    /// For example if 2 channels are sampled `measurements` contain: `[sq0 sq1 sq0 sq1 sq0 sq1 ..]`.
+    ///
+    /// Note that the ADC Datarate can be very fast, it is suggested to use DMA mode inside tightly running tasks
+    /// Otherwise, you'll see constant Overrun errors occuring, this means that you're sampling too quickly for the task to handle, and you may need to increase the buffer size.
+    /// Example:
+    /// ```rust,ignore
+    /// const DMA_BUF_LEN: usize = 120;
+    /// use embassy_stm32::adc::{Adc, AdcChannel}
+    ///
+    /// let mut adc = Adc::new(p.ADC1);
+    /// let mut adc_pin0 = p.PA0.degrade_adc();
+    /// let mut adc_pin1 = p.PA1.degrade_adc();
+    /// let adc_dma_buf = [0u16; DMA_BUF_LEN];
+    ///
+    /// let mut ring_buffered_adc: RingBufferedAdc<embassy_stm32::peripherals::ADC1> = adc.into_ring_buffered(
+    ///     p.DMA2_CH0,
+    ///      adc_dma_buf, [
+    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
+    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
+    ///     ].into_iter());
+    ///
+    ///
+    /// let mut measurements = [0u16; DMA_BUF_LEN / 2];
+    /// loop {
+    ///     match ring_buffered_adc.read(&mut measurements).await {
+    ///         Ok(_) => {
+    ///             defmt::info!("adc1: {}", measurements);
+    ///         }
+    ///         Err(e) => {
+    ///             defmt::warn!("Error: {:?}", e);
+    ///         }
+    ///     }
+    /// }
+    /// ```
+    ///
+    ///
+    /// [`teardown_adc`]: #method.teardown_adc
+    /// [`start_continuous_sampling`]: #method.start_continuous_sampling
+    pub async fn read(&mut self, measurements: &mut [u16]) -> Result<usize, OverrunError> {
+        assert_eq!(
+            self.ring_buf.capacity() / 2,
+            measurements.len(),
+            "Buffer size must be half the size of the ring buffer"
+        );
+
+        if !self.ring_buf.is_running() {
+            self.start();
+        }
+
+        #[cfg(adc_v2)]
+        {
+            // Clear overrun flag if set.
+            if T::regs().sr().read().ovr() {
+                self.stop();
+
+                return Err(OverrunError);
+            }
+        }
+
+        self.ring_buf.read_exact(measurements).await.map_err(|_| OverrunError)
+    }
+
+    /// Read bytes that are readily available in the ring buffer.
+    /// If no bytes are currently available in the buffer the call waits until the some
+    /// bytes are available (at least one byte and at most half the buffer size)
+    ///
+    /// Background receive is started if `start_continuous_sampling()` has not been previously called.
+    ///
+    /// Receive in the background is terminated if an error is returned.
+    /// It must then manually be started again by calling `start_continuous_sampling()` or by re-calling `blocking_read()`.
+    pub fn blocking_read(&mut self, buf: &mut [u16]) -> Result<usize, OverrunError> {
+        if !self.ring_buf.is_running() {
+            self.start();
+        }
+
+        #[cfg(adc_v2)]
+        {
+            // Clear overrun flag if set.
+            if T::regs().sr().read().ovr() {
+                self.stop();
+
+                return Err(OverrunError);
+            }
+        }
+        loop {
+            match self.ring_buf.read(buf) {
+                Ok((0, _)) => {}
+                Ok((len, _)) => {
+                    return Ok(len);
+                }
+                Err(_) => {
+                    self.stop();
+
+                    return Err(OverrunError);
+                }
+            }
+        }
+    }
+}
+
+impl<T: Instance> Drop for RingBufferedAdc<'_, T> {
+    fn drop(&mut self) {
+        Adc::<T>::teardown_adc();
+
+        compiler_fence(Ordering::SeqCst);
+
+        self.ring_buf.request_pause();
+        rcc::disable::<T>();
+    }
+}
diff --git a/embassy-stm32/src/adc/ringbuffered_v2.rs b/embassy-stm32/src/adc/ringbuffered_v2.rs
deleted file mode 100644
index 9b2e5b8fe..000000000
--- a/embassy-stm32/src/adc/ringbuffered_v2.rs
+++ /dev/null
@@ -1,432 +0,0 @@
-use core::marker::PhantomData;
-use core::mem;
-use core::sync::atomic::{Ordering, compiler_fence};
-
-use stm32_metapac::adc::vals::SampleTime;
-
-use crate::adc::{Adc, AdcChannel, Instance, RxDma};
-use crate::dma::{Priority, ReadableRingBuffer, TransferOptions};
-use crate::pac::adc::vals;
-use crate::{Peri, rcc};
-
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct OverrunError;
-
-fn clear_interrupt_flags(r: crate::pac::adc::Adc) {
-    r.sr().modify(|regs| {
-        regs.set_eoc(false);
-        regs.set_ovr(false);
-    });
-}
-
-#[derive(PartialOrd, PartialEq, Debug, Clone, Copy)]
-pub enum Sequence {
-    One,
-    Two,
-    Three,
-    Four,
-    Five,
-    Six,
-    Seven,
-    Eight,
-    Nine,
-    Ten,
-    Eleven,
-    Twelve,
-    Thirteen,
-    Fourteen,
-    Fifteen,
-    Sixteen,
-}
-
-impl From<Sequence> for u8 {
-    fn from(s: Sequence) -> u8 {
-        match s {
-            Sequence::One => 0,
-            Sequence::Two => 1,
-            Sequence::Three => 2,
-            Sequence::Four => 3,
-            Sequence::Five => 4,
-            Sequence::Six => 5,
-            Sequence::Seven => 6,
-            Sequence::Eight => 7,
-            Sequence::Nine => 8,
-            Sequence::Ten => 9,
-            Sequence::Eleven => 10,
-            Sequence::Twelve => 11,
-            Sequence::Thirteen => 12,
-            Sequence::Fourteen => 13,
-            Sequence::Fifteen => 14,
-            Sequence::Sixteen => 15,
-        }
-    }
-}
-
-impl From<u8> for Sequence {
-    fn from(val: u8) -> Self {
-        match val {
-            0 => Sequence::One,
-            1 => Sequence::Two,
-            2 => Sequence::Three,
-            3 => Sequence::Four,
-            4 => Sequence::Five,
-            5 => Sequence::Six,
-            6 => Sequence::Seven,
-            7 => Sequence::Eight,
-            8 => Sequence::Nine,
-            9 => Sequence::Ten,
-            10 => Sequence::Eleven,
-            11 => Sequence::Twelve,
-            12 => Sequence::Thirteen,
-            13 => Sequence::Fourteen,
-            14 => Sequence::Fifteen,
-            15 => Sequence::Sixteen,
-            _ => panic!("Invalid sequence number"),
-        }
-    }
-}
-
-pub struct RingBufferedAdc<'d, T: Instance> {
-    _phantom: PhantomData<T>,
-    ring_buf: ReadableRingBuffer<'d, u16>,
-}
-
-impl<'d, T: Instance> Adc<'d, T> {
-    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
-    ///
-    /// The `dma_buf` should be large enough to prevent DMA buffer overrun.
-    /// The length of the `dma_buf` should be a multiple of the ADC channel count.
-    /// For example, if 3 channels are measured, its length can be 3 * 40 = 120 measurements.
-    ///
-    /// `read` method is used to read out measurements from the DMA ring buffer, and its buffer should be exactly half of the `dma_buf` length.
-    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
-    ///
-    /// [`read`]: #method.read
-    pub fn into_ring_buffered(self, dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> RingBufferedAdc<'d, T> {
-        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
-
-        let opts: crate::dma::TransferOptions = TransferOptions {
-            half_transfer_ir: true,
-            priority: Priority::VeryHigh,
-            ..Default::default()
-        };
-
-        // Safety: we forget the struct before this function returns.
-        let rx_src = T::regs().dr().as_ptr() as *mut u16;
-        let request = dma.request();
-
-        let ring_buf = unsafe { ReadableRingBuffer::new(dma, request, rx_src, dma_buf, opts) };
-
-        // Don't disable the clock
-        mem::forget(self);
-
-        RingBufferedAdc {
-            _phantom: PhantomData,
-            ring_buf,
-        }
-    }
-}
-
-impl<'d, T: Instance> RingBufferedAdc<'d, T> {
-    fn is_on() -> bool {
-        T::regs().cr2().read().adon()
-    }
-
-    fn stop_adc() {
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(false);
-        });
-    }
-
-    fn start_adc() {
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(true);
-        });
-    }
-
-    /// Sets the channel sample time
-    ///
-    /// ## SAFETY:
-    /// - ADON == 0 i.e ADC must not be enabled when this is called.
-    unsafe fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
-        if ch <= 9 {
-            T::regs().smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
-        } else {
-            T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
-        }
-    }
-
-    fn set_channels_sample_time(&mut self, ch: &[u8], sample_time: SampleTime) {
-        let ch_iter = ch.iter();
-        for idx in ch_iter {
-            unsafe {
-                Self::set_channel_sample_time(*idx, sample_time);
-            }
-        }
-    }
-
-    pub fn set_sample_sequence(
-        &mut self,
-        sequence: Sequence,
-        channel: &mut impl AdcChannel<T>,
-        sample_time: SampleTime,
-    ) {
-        let was_on = Self::is_on();
-        if !was_on {
-            Self::start_adc();
-        }
-
-        // Check the sequence is long enough
-        T::regs().sqr1().modify(|r| {
-            let prev: Sequence = r.l().into();
-            if prev < sequence {
-                let new_l: Sequence = sequence;
-                trace!("Setting sequence length from {:?} to {:?}", prev as u8, new_l as u8);
-                r.set_l(sequence.into())
-            } else {
-                r.set_l(prev.into())
-            }
-        });
-
-        // Set this GPIO as an analog input.
-        channel.setup();
-
-        // Set the channel in the right sequence field.
-        match sequence {
-            Sequence::One => T::regs().sqr3().modify(|w| w.set_sq(0, channel.channel())),
-            Sequence::Two => T::regs().sqr3().modify(|w| w.set_sq(1, channel.channel())),
-            Sequence::Three => T::regs().sqr3().modify(|w| w.set_sq(2, channel.channel())),
-            Sequence::Four => T::regs().sqr3().modify(|w| w.set_sq(3, channel.channel())),
-            Sequence::Five => T::regs().sqr3().modify(|w| w.set_sq(4, channel.channel())),
-            Sequence::Six => T::regs().sqr3().modify(|w| w.set_sq(5, channel.channel())),
-            Sequence::Seven => T::regs().sqr2().modify(|w| w.set_sq(0, channel.channel())),
-            Sequence::Eight => T::regs().sqr2().modify(|w| w.set_sq(1, channel.channel())),
-            Sequence::Nine => T::regs().sqr2().modify(|w| w.set_sq(2, channel.channel())),
-            Sequence::Ten => T::regs().sqr2().modify(|w| w.set_sq(3, channel.channel())),
-            Sequence::Eleven => T::regs().sqr2().modify(|w| w.set_sq(4, channel.channel())),
-            Sequence::Twelve => T::regs().sqr2().modify(|w| w.set_sq(5, channel.channel())),
-            Sequence::Thirteen => T::regs().sqr1().modify(|w| w.set_sq(0, channel.channel())),
-            Sequence::Fourteen => T::regs().sqr1().modify(|w| w.set_sq(1, channel.channel())),
-            Sequence::Fifteen => T::regs().sqr1().modify(|w| w.set_sq(2, channel.channel())),
-            Sequence::Sixteen => T::regs().sqr1().modify(|w| w.set_sq(3, channel.channel())),
-        };
-
-        if !was_on {
-            Self::stop_adc();
-        }
-
-        self.set_channels_sample_time(&[channel.channel()], sample_time);
-
-        Self::start_adc();
-    }
-
-    /// Turns on ADC if it is not already turned on and starts continuous DMA transfer.
-    pub fn start(&mut self) -> Result<(), OverrunError> {
-        self.setup_adc();
-        self.ring_buf.clear();
-
-        Ok(())
-    }
-
-    fn stop(&mut self, err: OverrunError) -> Result<usize, OverrunError> {
-        self.teardown_adc();
-        Err(err)
-    }
-
-    /// Stops DMA transfer.
-    /// It does not turn off ADC.
-    /// Calling `start` restarts continuous DMA transfer.
-    ///
-    /// [`start`]: #method.start
-    pub fn teardown_adc(&mut self) {
-        // Stop the DMA transfer
-        self.ring_buf.request_pause();
-
-        let r = T::regs();
-
-        // Stop ADC
-        r.cr2().modify(|reg| {
-            // Stop ADC
-            reg.set_swstart(false);
-            // Stop DMA
-            reg.set_dma(false);
-        });
-
-        r.cr1().modify(|w| {
-            // Disable interrupt for end of conversion
-            w.set_eocie(false);
-            // Disable interrupt for overrun
-            w.set_ovrie(false);
-        });
-
-        clear_interrupt_flags(r);
-
-        compiler_fence(Ordering::SeqCst);
-    }
-
-    fn setup_adc(&mut self) {
-        compiler_fence(Ordering::SeqCst);
-
-        self.ring_buf.start();
-
-        let r = T::regs();
-
-        // Enable ADC
-        let was_on = Self::is_on();
-        if !was_on {
-            r.cr2().modify(|reg| {
-                reg.set_adon(false);
-                reg.set_swstart(false);
-            });
-        }
-
-        // Clear all interrupts
-        r.sr().modify(|regs| {
-            regs.set_eoc(false);
-            regs.set_ovr(false);
-            regs.set_strt(false);
-        });
-
-        r.cr1().modify(|w| {
-            // Enable interrupt for end of conversion
-            w.set_eocie(true);
-            // Enable interrupt for overrun
-            w.set_ovrie(true);
-            // Scanning converisons of multiple channels
-            w.set_scan(true);
-            // Continuous conversion mode
-            w.set_discen(false);
-        });
-
-        r.cr2().modify(|w| {
-            // Enable DMA mode
-            w.set_dma(true);
-            // Enable continuous conversions
-            w.set_cont(true);
-            // DMA requests are issues as long as DMA=1 and data are converted.
-            w.set_dds(vals::Dds::CONTINUOUS);
-            // EOC flag is set at the end of each conversion.
-            w.set_eocs(vals::Eocs::EACH_CONVERSION);
-        });
-
-        // Begin ADC conversions
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(true);
-            reg.set_swstart(true);
-        });
-
-        super::blocking_delay_us(3);
-    }
-
-    /// Read bytes that are readily available in the ring buffer.
-    /// If no bytes are currently available in the buffer the call waits until the some
-    /// bytes are available (at least one byte and at most half the buffer size)
-    ///
-    /// Background receive is started if `start()` has not been previously called.
-    ///
-    /// Receive in the background is terminated if an error is returned.
-    /// It must then manually be started again by calling `start()` or by re-calling `read()`.
-    pub fn blocking_read<const N: usize>(&mut self, buf: &mut [u16; N]) -> Result<usize, OverrunError> {
-        let r = T::regs();
-
-        // Start background receive if it was not already started
-        if !r.cr2().read().dma() {
-            self.start()?;
-        }
-
-        // Clear overrun flag if set.
-        if r.sr().read().ovr() {
-            return self.stop(OverrunError);
-        }
-
-        loop {
-            match self.ring_buf.read(buf) {
-                Ok((0, _)) => {}
-                Ok((len, _)) => {
-                    return Ok(len);
-                }
-                Err(_) => {
-                    return self.stop(OverrunError);
-                }
-            }
-        }
-    }
-
-    /// Reads measurements from the DMA ring buffer.
-    ///
-    /// This method fills the provided `measurements` array with ADC readings from the DMA buffer.
-    /// The length of the `measurements` array should be exactly half of the DMA buffer length. Because interrupts are only generated if half or full DMA transfer completes.
-    ///
-    /// Each call to `read` will populate the `measurements` array in the same order as the channels defined with `set_sample_sequence`.
-    /// There will be many sequences worth of measurements in this array because it only returns if at least half of the DMA buffer is filled.
-    /// For example if 3 channels are sampled `measurements` contain: `[sq0 sq1 sq3 sq0 sq1 sq3 sq0 sq1 sq3 sq0 sq1 sq3..]`.
-    ///
-    /// If an error is returned, it indicates a DMA overrun, and the process must be restarted by calling `start` or `read` again.
-    ///
-    /// By default, the ADC fills the DMA buffer as quickly as possible. To control the sample rate, call `teardown_adc` after each readout, and then start the DMA again at the desired interval.
-    /// Note that even if using `teardown_adc` to control the sample rate, with each call to `read`, measurements equivalent to half the size of the DMA buffer are still collected.
-    ///
-    /// Example:
-    /// ```rust,ignore
-    /// const DMA_BUF_LEN: usize = 120;
-    /// let adc_dma_buf = [0u16; DMA_BUF_LEN];
-    /// let mut adc: RingBufferedAdc<embassy_stm32::peripherals::ADC1> = adc.into_ring_buffered(p.DMA2_CH0, adc_dma_buf);
-    ///
-    /// adc.set_sample_sequence(Sequence::One, &mut p.PA0, SampleTime::CYCLES112);
-    /// adc.set_sample_sequence(Sequence::Two, &mut p.PA1, SampleTime::CYCLES112);
-    /// adc.set_sample_sequence(Sequence::Three, &mut p.PA2, SampleTime::CYCLES112);
-    ///
-    /// let mut measurements = [0u16; DMA_BUF_LEN / 2];
-    /// loop {
-    ///     match adc.read(&mut measurements).await {
-    ///         Ok(_) => {
-    ///             defmt::info!("adc1: {}", measurements);
-    ///             // Only needed to manually control sample rate.
-    ///             adc.teardown_adc();
-    ///         }
-    ///         Err(e) => {
-    ///             defmt::warn!("Error: {:?}", e);
-    ///             // DMA overrun, next call to `read` restarts ADC.
-    ///         }
-    ///     }
-    ///
-    ///     // Manually control sample rate.
-    ///     Timer::after_millis(100).await;
-    /// }
-    /// ```
-    ///
-    ///
-    /// [`set_sample_sequence`]: #method.set_sample_sequence
-    /// [`teardown_adc`]: #method.teardown_adc
-    /// [`start`]: #method.start
-    pub async fn read<const N: usize>(&mut self, measurements: &mut [u16; N]) -> Result<usize, OverrunError> {
-        assert_eq!(
-            self.ring_buf.capacity() / 2,
-            N,
-            "Buffer size must be half the size of the ring buffer"
-        );
-
-        let r = T::regs();
-
-        // Start background receive if it was not already started
-        if !r.cr2().read().dma() {
-            self.start()?;
-        }
-
-        // Clear overrun flag if set.
-        if r.sr().read().ovr() {
-            return self.stop(OverrunError);
-        }
-        match self.ring_buf.read_exact(measurements).await {
-            Ok(len) => Ok(len),
-            Err(_) => self.stop(OverrunError),
-        }
-    }
-}
-
-impl<T: Instance> Drop for RingBufferedAdc<'_, T> {
-    fn drop(&mut self) {
-        self.teardown_adc();
-        rcc::disable::<T>();
-    }
-}
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index 93ec78548..90c6294d2 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -1,11 +1,22 @@
+use core::mem;
+use core::sync::atomic::{Ordering, compiler_fence};
+
 use super::blocking_delay_us;
-use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
+use crate::adc::{Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel};
+use crate::pac::adc::vals;
 use crate::peripherals::ADC1;
 use crate::time::Hertz;
 use crate::{Peri, rcc};
 
-mod ringbuffered_v2;
-pub use ringbuffered_v2::{RingBufferedAdc, Sequence};
+mod ringbuffered;
+pub use ringbuffered::RingBufferedAdc;
+
+fn clear_interrupt_flags(r: crate::pac::adc::Adc) {
+    r.sr().modify(|regs| {
+        regs.set_eoc(false);
+        regs.set_ovr(false);
+    });
+}
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -112,6 +123,98 @@ where
         }
     }
 
+    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+    ///
+    /// The `dma_buf` should be large enough to prevent DMA buffer overrun.
+    /// The length of the `dma_buf` should be a multiple of the ADC channel count.
+    /// For example, if 3 channels are measured, its length can be 3 * 40 = 120 measurements.
+    ///
+    /// `read` method is used to read out measurements from the DMA ring buffer, and its buffer should be exactly half of the `dma_buf` length.
+    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
+    ///
+    /// [`read`]: #method.read
+    pub fn into_ring_buffered<'a>(
+        self,
+        dma: Peri<'d, impl RxDma<T>>,
+        dma_buf: &'d mut [u16],
+        sequence: impl ExactSizeIterator<Item = (&'a mut AnyAdcChannel<T>, SampleTime)>,
+    ) -> RingBufferedAdc<'d, T> {
+        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
+
+        T::regs().cr2().modify(|reg| {
+            reg.set_adon(true);
+        });
+
+        // Check the sequence is long enough
+        T::regs().sqr1().modify(|r| {
+            r.set_l((sequence.len() - 1).try_into().unwrap());
+        });
+
+        for (i, (channel, sample_time)) in sequence.enumerate() {
+            // Set this GPIO as an analog input.
+            channel.setup();
+
+            // Set the channel in the right sequence field.
+            T::regs().sqr3().modify(|w| w.set_sq(i, channel.channel()));
+
+            Self::set_channel_sample_time(channel.channel(), sample_time);
+        }
+
+        compiler_fence(Ordering::SeqCst);
+
+        let r = T::regs();
+
+        // Clear all interrupts
+        r.sr().modify(|regs| {
+            regs.set_eoc(false);
+            regs.set_ovr(false);
+            regs.set_strt(false);
+        });
+
+        r.cr1().modify(|w| {
+            // Enable interrupt for end of conversion
+            w.set_eocie(true);
+            // Enable interrupt for overrun
+            w.set_ovrie(true);
+            // Scanning converisons of multiple channels
+            w.set_scan(true);
+            // Continuous conversion mode
+            w.set_discen(false);
+        });
+
+        r.cr2().modify(|w| {
+            // Enable DMA mode
+            w.set_dma(true);
+            // Enable continuous conversions
+            w.set_cont(true);
+            // DMA requests are issues as long as DMA=1 and data are converted.
+            w.set_dds(vals::Dds::CONTINUOUS);
+            // EOC flag is set at the end of each conversion.
+            w.set_eocs(vals::Eocs::EACH_CONVERSION);
+        });
+
+        // Don't disable the clock
+        mem::forget(self);
+
+        RingBufferedAdc::new(dma, dma_buf)
+    }
+
+    pub(super) fn start() {
+        // Begin ADC conversions
+        T::regs().cr2().modify(|reg| {
+            reg.set_adon(true);
+            reg.set_swstart(true);
+        });
+    }
+
+    pub(super) fn stop() {
+        // Stop ADC
+        T::regs().cr2().modify(|reg| {
+            // Stop ADC
+            reg.set_swstart(false);
+        });
+    }
+
     pub fn set_sample_time(&mut self, sample_time: SampleTime) {
         self.sample_time = sample_time;
     }
@@ -198,6 +301,31 @@ where
             T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
         }
     }
+
+    pub(super) fn teardown_adc() {
+        let r = T::regs();
+
+        // Stop ADC
+        r.cr2().modify(|reg| {
+            // Stop ADC
+            reg.set_swstart(false);
+            // Stop ADC
+            reg.set_adon(false);
+            // Stop DMA
+            reg.set_dma(false);
+        });
+
+        r.cr1().modify(|w| {
+            // Disable interrupt for end of conversion
+            w.set_eocie(false);
+            // Disable interrupt for overrun
+            w.set_ovrie(false);
+        });
+
+        clear_interrupt_flags(r);
+
+        compiler_fence(Ordering::SeqCst);
+    }
 }
 
 impl<'d, T: Instance> Drop for Adc<'d, T> {
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 47632263b..62c2da557 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -12,6 +12,13 @@ pub use pac::adc::vals::{Ovsr, Ovss, Presc};
 use super::{
     Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel, blocking_delay_us,
 };
+
+#[cfg(any(adc_v3, adc_g0, adc_u0))]
+mod ringbuffered;
+
+#[cfg(any(adc_v3, adc_g0, adc_u0))]
+use ringbuffered::RingBufferedAdc;
+
 use crate::dma::Transfer;
 use crate::{Peri, pac, rcc};
 
@@ -174,6 +181,38 @@ impl<'d, T: Instance> Adc<'d, T> {
         blocking_delay_us(1);
     }
 
+    #[cfg(any(adc_v3, adc_g0, adc_u0))]
+    pub(super) fn start() {
+        // Start adc conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
+
+    #[cfg(any(adc_v3, adc_g0, adc_u0))]
+    pub(super) fn stop() {
+        // Stop adc conversion
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(true);
+            });
+            while T::regs().cr().read().adstart() {}
+        }
+    }
+
+    #[cfg(any(adc_v3, adc_g0, adc_u0))]
+    pub(super) fn teardown_adc() {
+        //disable dma control
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::regs().cfgr().modify(|reg| {
+            reg.set_dmaen(false);
+        });
+        #[cfg(any(adc_g0, adc_u0))]
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_dmaen(false);
+        });
+    }
+
     /// Initialize the ADC leaving any analog clock at reset value.
     /// For G0 and WL, this is the async clock without prescaler.
     pub fn new(adc: Peri<'d, T>) -> Self {
@@ -423,6 +462,9 @@ impl<'d, T: Instance> Adc<'d, T> {
             "Asynchronous read sequence cannot be more than 16 in length"
         );
 
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new();
+
         // Ensure no conversions are ongoing and ADC is enabled.
         Self::cancel_conversions();
         self.enable();
@@ -559,6 +601,137 @@ impl<'d, T: Instance> Adc<'d, T> {
         });
     }
 
+    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+    ///
+    /// The `dma_buf` should be large enough to prevent DMA buffer overrun.
+    /// The length of the `dma_buf` should be a multiple of the ADC channel count.
+    /// For example, if 3 channels are measured, its length can be 3 * 40 = 120 measurements.
+    ///
+    /// `read` method is used to read out measurements from the DMA ring buffer, and its buffer should be exactly half of the `dma_buf` length.
+    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
+    ///
+    /// [`read`]: #method.read
+    #[cfg(any(adc_v3, adc_g0, adc_u0))]
+    pub fn into_ring_buffered<'a>(
+        &mut self,
+        dma: Peri<'a, impl RxDma<T>>,
+        dma_buf: &'a mut [u16],
+        sequence: impl ExactSizeIterator<Item = (&'a mut AnyAdcChannel<T>, SampleTime)>,
+    ) -> RingBufferedAdc<'a, T> {
+        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+        // reset conversions and enable the adc
+        Self::cancel_conversions();
+        self.enable();
+
+        //adc side setup
+
+        // Set sequence length
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::regs().sqr1().modify(|w| {
+            w.set_l(sequence.len() as u8 - 1);
+        });
+
+        #[cfg(adc_g0)]
+        {
+            let mut sample_times = Vec::<SampleTime, SAMPLE_TIMES_CAPACITY>::new();
+
+            T::regs().chselr().write(|chselr| {
+                T::regs().smpr().write(|smpr| {
+                    for (channel, sample_time) in sequence {
+                        chselr.set_chsel(channel.channel.into(), true);
+                        if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
+                            smpr.set_smpsel(channel.channel.into(), (i as u8).into());
+                        } else {
+                            smpr.set_sample_time(sample_times.len(), sample_time);
+                            if let Err(_) = sample_times.push(sample_time) {
+                                panic!(
+                                    "Implementation is limited to {} unique sample times among all channels.",
+                                    SAMPLE_TIMES_CAPACITY
+                                );
+                            }
+                        }
+                    }
+                })
+            });
+        }
+        #[cfg(not(adc_g0))]
+        {
+            #[cfg(adc_u0)]
+            let mut channel_mask = 0;
+
+            // Configure channels and ranks
+            for (_i, (channel, sample_time)) in sequence.enumerate() {
+                Self::configure_channel(channel, sample_time);
+
+                // Each channel is sampled according to sequence
+                #[cfg(not(any(adc_g0, adc_u0)))]
+                match _i {
+                    0..=3 => {
+                        T::regs().sqr1().modify(|w| {
+                            w.set_sq(_i, channel.channel());
+                        });
+                    }
+                    4..=8 => {
+                        T::regs().sqr2().modify(|w| {
+                            w.set_sq(_i - 4, channel.channel());
+                        });
+                    }
+                    9..=13 => {
+                        T::regs().sqr3().modify(|w| {
+                            w.set_sq(_i - 9, channel.channel());
+                        });
+                    }
+                    14..=15 => {
+                        T::regs().sqr4().modify(|w| {
+                            w.set_sq(_i - 14, channel.channel());
+                        });
+                    }
+                    _ => unreachable!(),
+                }
+
+                #[cfg(adc_u0)]
+                {
+                    channel_mask |= 1 << channel.channel();
+                }
+            }
+
+            // On G0 and U0 enabled channels are sampled from 0 to last channel.
+            // It is possible to add up to 8 sequences if CHSELRMOD = 1.
+            // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
+            #[cfg(adc_u0)]
+            T::regs().chselr().modify(|reg| {
+                reg.set_chsel(channel_mask);
+            });
+        }
+        // Set continuous mode with Circular dma.
+        // Clear overrun flag before starting transfer.
+        T::regs().isr().modify(|reg| {
+            reg.set_ovr(true);
+        });
+
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::regs().cfgr().modify(|reg| {
+            reg.set_discen(false);
+            reg.set_cont(true);
+            reg.set_dmacfg(Dmacfg::CIRCULAR);
+            reg.set_dmaen(true);
+        });
+        #[cfg(any(adc_g0, adc_u0))]
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_discen(false);
+            reg.set_cont(true);
+            reg.set_dmacfg(Dmacfg::CIRCULAR);
+            reg.set_dmaen(true);
+        });
+
+        RingBufferedAdc::new(dma, dma_buf)
+    }
+
     #[cfg(not(adc_g0))]
     fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
         // RM0492, RM0481, etc.
diff --git a/embassy-stm32/src/can/fd/config.rs b/embassy-stm32/src/can/fd/config.rs
index e08349f02..4fe634ce4 100644
--- a/embassy-stm32/src/can/fd/config.rs
+++ b/embassy-stm32/src/can/fd/config.rs
@@ -360,6 +360,8 @@ pub struct FdCanConfig {
     pub global_filter: GlobalFilter,
     /// TX buffer mode (FIFO or priority queue)
     pub tx_buffer_mode: TxBufferMode,
+    /// Automatic recovery from bus off state
+    pub automatic_bus_off_recovery: bool,
 }
 
 impl FdCanConfig {
@@ -456,6 +458,16 @@ impl FdCanConfig {
         self.tx_buffer_mode = txbm;
         self
     }
+
+    /// Enables or disables automatic recovery from bus off state
+    ///
+    /// Automatic recovery is performed by clearing the INIT bit in the CCCR register if
+    /// the BO bit is active in the IR register in the IT0 interrupt.
+    #[inline]
+    pub const fn set_automatic_bus_off_recovery(mut self, enabled: bool) -> Self {
+        self.automatic_bus_off_recovery = enabled;
+        self
+    }
 }
 
 impl Default for FdCanConfig {
@@ -474,6 +486,7 @@ impl Default for FdCanConfig {
             timestamp_source: TimestampSource::None,
             global_filter: GlobalFilter::default(),
             tx_buffer_mode: TxBufferMode::Priority,
+            automatic_bus_off_recovery: true,
         }
     }
 }
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index a142a6d63..9883aff57 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -53,7 +53,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
             regs.ir().write(|w| w.set_tefn(true));
         }
 
-        T::info().state.lock(|s| {
+        let recover_from_bo = T::info().state.lock(|s| {
             let state = s.borrow_mut();
             match &state.tx_mode {
                 TxMode::NonBuffered(waker) => waker.wake(),
@@ -85,11 +85,15 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
             if ir.rfn(1) {
                 state.rx_mode.on_interrupt::<T>(1, state.ns_per_timer_tick);
             }
+
+            state.automatic_bus_off_recovery
         });
 
         if ir.bo() {
             regs.ir().write(|w| w.set_bo(true));
-            if regs.psr().read().bo() {
+            if let Some(true) = recover_from_bo
+                && regs.psr().read().bo()
+            {
                 // Initiate bus-off recovery sequence by resetting CCCR.INIT
                 regs.cccr().modify(|w| w.set_init(false));
             }
@@ -263,7 +267,9 @@ impl<'d> CanConfigurator<'d> {
     pub fn start(self, mode: OperatingMode) -> Can<'d> {
         let ns_per_timer_tick = calc_ns_per_timer_tick(&self.info, self.periph_clock, self.config.frame_transmit);
         self.info.state.lock(|s| {
-            s.borrow_mut().ns_per_timer_tick = ns_per_timer_tick;
+            let mut state = s.borrow_mut();
+            state.ns_per_timer_tick = ns_per_timer_tick;
+            state.automatic_bus_off_recovery = Some(self.config.automatic_bus_off_recovery);
         });
         self.info.regs.into_mode(self.config, mode);
         Can {
@@ -861,7 +867,7 @@ struct State {
     sender_instance_count: usize,
     tx_pin_port: Option<u8>,
     rx_pin_port: Option<u8>,
-
+    automatic_bus_off_recovery: Option<bool>, // controlled by CanConfigurator::start()
     pub err_waker: AtomicWaker,
 }
 
@@ -876,6 +882,7 @@ impl State {
             sender_instance_count: 0,
             tx_pin_port: None,
             rx_pin_port: None,
+            automatic_bus_off_recovery: None,
         }
     }
 }
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 01b6b8800..6f2d03bd1 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -70,6 +70,11 @@ fn debug_print_interrupts(isr: stm32_metapac::i2c::regs::Isr) {
 }
 
 pub(crate) unsafe fn on_interrupt<T: Instance>() {
+    // restore the clocks to their last configured state as
+    // much is lost in STOP modes
+    #[cfg(all(feature = "low-power", stm32wlex))]
+    crate::low_power::on_wakeup_irq();
+
     let regs = T::info().regs;
     let isr = regs.isr().read();
 
@@ -814,6 +819,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write.
     pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new();
         let timeout = self.timeout();
         if write.is_empty() {
             self.write_internal(address.into(), write, true, timeout)
@@ -828,6 +835,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     ///
     /// The buffers are concatenated in a single write transaction.
     pub async fn write_vectored(&mut self, address: Address, write: &[&[u8]]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new();
         let timeout = self.timeout();
 
         if write.is_empty() {
@@ -851,6 +860,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Read.
     pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new();
         let timeout = self.timeout();
 
         if buffer.is_empty() {
@@ -863,6 +874,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write, restart, read.
     pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new();
         let timeout = self.timeout();
 
         if write.is_empty() {
@@ -888,6 +901,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
     pub async fn transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new();
         let _ = addr;
         let _ = operations;
         todo!()
diff --git a/embassy-stm32/src/low_power.rs b/embassy-stm32/src/low_power.rs
index 1b66ca680..cde3153f6 100644
--- a/embassy-stm32/src/low_power.rs
+++ b/embassy-stm32/src/low_power.rs
@@ -43,8 +43,6 @@
 //!
 //!     // give the RTC to the executor...
 //!     let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
-//!     static RTC: StaticCell<Rtc> = StaticCell::new();
-//!     let rtc = RTC.init(rtc);
 //!     embassy_stm32::low_power::stop_with_rtc(rtc);
 //!
 //!     // your application here...
@@ -70,6 +68,39 @@ use crate::rtc::Rtc;
 
 static mut EXECUTOR: Option<Executor> = None;
 
+#[cfg(stm32wlex)]
+pub(crate) use self::busy::DeviceBusy;
+#[cfg(stm32wlex)]
+mod busy {
+    use core::sync::atomic::{AtomicU32, Ordering};
+
+    // Count of devices blocking STOP
+    static STOP_BLOCKED: AtomicU32 = AtomicU32::new(0);
+
+    /// Check if STOP1 is blocked.
+    pub(crate) fn stop_blocked() -> bool {
+        STOP_BLOCKED.load(Ordering::SeqCst) > 0
+    }
+
+    /// When ca device goes busy it will construct one of these where it will be dropped when the device goes idle.
+    pub(crate) struct DeviceBusy {}
+
+    impl DeviceBusy {
+        /// Create a new DeviceBusy.
+        pub(crate) fn new() -> Self {
+            STOP_BLOCKED.fetch_add(1, Ordering::SeqCst);
+            trace!("low power: device busy: Stop:{}", STOP_BLOCKED.load(Ordering::SeqCst));
+            Self {}
+        }
+    }
+
+    impl Drop for DeviceBusy {
+        fn drop(&mut self) {
+            STOP_BLOCKED.fetch_sub(1, Ordering::SeqCst);
+            trace!("low power: device idle: Stop:{}", STOP_BLOCKED.load(Ordering::SeqCst));
+        }
+    }
+}
 #[cfg(not(stm32u0))]
 foreach_interrupt! {
     (RTC, rtc, $block:ident, WKUP, $irq:ident) => {
@@ -94,14 +125,22 @@ foreach_interrupt! {
 
 #[allow(dead_code)]
 pub(crate) unsafe fn on_wakeup_irq() {
-    EXECUTOR.as_mut().unwrap().on_wakeup_irq();
+    if EXECUTOR.is_some() {
+        trace!("low power: wakeup irq");
+        EXECUTOR.as_mut().unwrap().on_wakeup_irq();
+    }
 }
 
 /// Configure STOP mode with RTC.
-pub fn stop_with_rtc(rtc: &'static Rtc) {
+pub fn stop_with_rtc(rtc: Rtc) {
     unsafe { EXECUTOR.as_mut().unwrap() }.stop_with_rtc(rtc)
 }
 
+/// Reconfigure the RTC, if set.
+pub fn reconfigure_rtc(f: impl FnOnce(&mut Rtc)) {
+    unsafe { EXECUTOR.as_mut().unwrap() }.reconfigure_rtc(f);
+}
+
 /// Get whether the core is ready to enter the given stop mode.
 ///
 /// This will return false if some peripheral driver is in use that
@@ -124,10 +163,10 @@ pub enum StopMode {
     Stop2,
 }
 
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32u0))]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32wlex, stm32u0))]
 use stm32_metapac::pwr::vals::Lpms;
 
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32u0))]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32wlex, stm32u0))]
 impl Into<Lpms> for StopMode {
     fn into(self) -> Lpms {
         match self {
@@ -177,22 +216,53 @@ impl Executor {
     }
 
     unsafe fn on_wakeup_irq(&mut self) {
+        #[cfg(stm32wlex)]
+        {
+            let extscr = crate::pac::PWR.extscr().read();
+            if extscr.c1stop2f() || extscr.c1stopf() {
+                // when we wake from any stop mode we need to re-initialize the rcc
+                crate::rcc::apply_resume_config();
+                if extscr.c1stop2f() {
+                    // when we wake from STOP2, we need to re-initialize the time driver
+                    critical_section::with(|cs| crate::time_driver::init_timer(cs));
+                    // reset the refcounts for STOP2 and STOP1 (initializing the time driver will increment one of them for the timer)
+                    // and given that we just woke from STOP2, we can reset them
+                    crate::rcc::REFCOUNT_STOP2 = 0;
+                    crate::rcc::REFCOUNT_STOP1 = 0;
+                }
+            }
+        }
         self.time_driver.resume_time();
         trace!("low power: resume");
     }
 
-    pub(self) fn stop_with_rtc(&mut self, rtc: &'static Rtc) {
+    pub(self) fn stop_with_rtc(&mut self, rtc: Rtc) {
         self.time_driver.set_rtc(rtc);
-
-        rtc.enable_wakeup_line();
+        self.time_driver.reconfigure_rtc(|rtc| rtc.enable_wakeup_line());
 
         trace!("low power: stop with rtc configured");
     }
 
+    pub(self) fn reconfigure_rtc(&mut self, f: impl FnOnce(&mut Rtc)) {
+        self.time_driver.reconfigure_rtc(f);
+    }
+
+    fn stop1_ok_to_enter(&self) -> bool {
+        #[cfg(stm32wlex)]
+        if self::busy::stop_blocked() {
+            return false;
+        }
+        unsafe { crate::rcc::REFCOUNT_STOP1 == 0 }
+    }
+
+    fn stop2_ok_to_enter(&self) -> bool {
+        self.stop1_ok_to_enter() && unsafe { crate::rcc::REFCOUNT_STOP2 == 0 }
+    }
+
     fn stop_mode(&self) -> Option<StopMode> {
-        if unsafe { crate::rcc::REFCOUNT_STOP2 == 0 } && unsafe { crate::rcc::REFCOUNT_STOP1 == 0 } {
+        if self.stop2_ok_to_enter() {
             Some(StopMode::Stop2)
-        } else if unsafe { crate::rcc::REFCOUNT_STOP1 == 0 } {
+        } else if self.stop1_ok_to_enter() {
             Some(StopMode::Stop1)
         } else {
             None
@@ -201,7 +271,7 @@ impl Executor {
 
     #[allow(unused_variables)]
     fn configure_stop(&mut self, stop_mode: StopMode) {
-        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0, stm32wba))]
+        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0, stm32wba, stm32wlex))]
         crate::pac::PWR.cr1().modify(|m| m.set_lpms(stop_mode.into()));
         #[cfg(stm32h5)]
         crate::pac::PWR.pmcr().modify(|v| {
@@ -213,6 +283,11 @@ impl Executor {
 
     fn configure_pwr(&mut self) {
         self.scb.clear_sleepdeep();
+        // Clear any previous stop flags
+        #[cfg(stm32wlex)]
+        crate::pac::PWR.extscr().modify(|w| {
+            w.set_c1cssf(true);
+        });
 
         compiler_fence(Ordering::SeqCst);
 
@@ -266,6 +341,19 @@ impl Executor {
                 executor.inner.poll();
                 self.configure_pwr();
                 asm!("wfe");
+                #[cfg(stm32wlex)]
+                {
+                    let es = crate::pac::PWR.extscr().read();
+                    match (es.c1stopf(), es.c1stop2f()) {
+                        (true, false) => debug!("low power: wake from STOP1"),
+                        (false, true) => debug!("low power: wake from STOP2"),
+                        (true, true) => debug!("low power: wake from STOP1 and STOP2 ???"),
+                        (false, false) => trace!("low power: stop mode not entered"),
+                    };
+                    crate::pac::PWR.extscr().modify(|w| {
+                        w.set_c1cssf(false);
+                    });
+                }
             };
         }
     }
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 2e1cbd702..584957c6d 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -1,3 +1,6 @@
+#[cfg(all(feature = "low-power", stm32wlex))]
+use core::mem::MaybeUninit;
+
 #[cfg(any(stm32l0, stm32l1))]
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
 use crate::pac::rcc::regs::Cfgr;
@@ -11,6 +14,42 @@ use crate::time::Hertz;
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
+/// Saved RCC Config
+///
+/// Used when exiting STOP2 to re-enable clocks to their last configured state
+/// for chips that need it.
+#[cfg(all(feature = "low-power", stm32wlex))]
+static mut RESUME_RCC_CONFIG: MaybeUninit<Config> = MaybeUninit::uninit();
+
+/// Set the rcc config to be restored when exiting STOP2
+///
+/// Safety: Sets a mutable global.
+#[cfg(all(feature = "low-power", stm32wlex))]
+pub(crate) unsafe fn set_resume_config(config: Config) {
+    trace!("rcc set_resume_config()");
+    RESUME_RCC_CONFIG = MaybeUninit::new(config);
+}
+
+/// Get the rcc config to be restored when exiting STOP2
+///
+/// Safety: Reads a mutable global.
+#[cfg(all(feature = "low-power", stm32wlex))]
+pub(crate) unsafe fn get_resume_config() -> Config {
+    *(*core::ptr::addr_of_mut!(RESUME_RCC_CONFIG)).assume_init_ref()
+}
+
+#[cfg(all(feature = "low-power", stm32wlex))]
+/// Safety: should only be called from low power executable just after resuming from STOP2
+pub(crate) unsafe fn apply_resume_config() {
+    trace!("rcc apply_resume_config()");
+
+    while RCC.cfgr().read().sws() != Sysclk::MSI {}
+
+    let config = get_resume_config();
+
+    init(config);
+}
+
 #[derive(Clone, Copy, Eq, PartialEq)]
 pub enum HseMode {
     /// crystal/ceramic oscillator (HSEBYP=0)
@@ -154,6 +193,10 @@ fn msi_enable(range: MSIRange) {
 }
 
 pub(crate) unsafe fn init(config: Config) {
+    // save the rcc config because if we enter stop 2 we need to re-apply it on wakeup
+    #[cfg(all(feature = "low-power", stm32wlex))]
+    set_resume_config(config);
+
     // Switch to MSI to prevent problems with PLL configuration.
     if !RCC.cr().read().msion() {
         // Turn on MSI and configure it to 4MHz.
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index addfca3c3..c817dd4b7 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -390,7 +390,7 @@ pub fn disable<T: RccPeripheral>() {
 ///
 /// This should only be called after `init`.
 #[cfg(not(feature = "_dual-core"))]
-pub fn reinit<'a>(config: Config, _rcc: &'a mut crate::Peri<'a, crate::peripherals::RCC>) {
+pub fn reinit(config: Config, _rcc: &'_ mut crate::Peri<'_, crate::peripherals::RCC>) {
     critical_section::with(|cs| init_rcc(cs, config))
 }
 
diff --git a/embassy-stm32/src/rtc/low_power.rs b/embassy-stm32/src/rtc/low_power.rs
index 999f24714..e09d5afb0 100644
--- a/embassy-stm32/src/rtc/low_power.rs
+++ b/embassy-stm32/src/rtc/low_power.rs
@@ -68,7 +68,7 @@ pub(crate) enum WakeupPrescaler {
 }
 
 #[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba
+    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba, stm32wlex
 ))]
 impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
     fn from(val: WakeupPrescaler) -> Self {
@@ -84,7 +84,7 @@ impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
 }
 
 #[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba
+    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba, stm32wlex
 ))]
 impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
     fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
@@ -127,7 +127,7 @@ impl Rtc {
     /// start the wakeup alarm and with a duration that is as close to but less than
     /// the requested duration, and record the instant the wakeup alarm was started
     pub(crate) fn start_wakeup_alarm(
-        &self,
+        &mut self,
         requested_duration: embassy_time::Duration,
         cs: critical_section::CriticalSection,
     ) {
@@ -179,7 +179,10 @@ impl Rtc {
 
     /// stop the wakeup alarm and return the time elapsed since `start_wakeup_alarm`
     /// was called, otherwise none
-    pub(crate) fn stop_wakeup_alarm(&self, cs: critical_section::CriticalSection) -> Option<embassy_time::Duration> {
+    pub(crate) fn stop_wakeup_alarm(
+        &mut self,
+        cs: critical_section::CriticalSection,
+    ) -> Option<embassy_time::Duration> {
         let instant = self.instant().unwrap();
         if RTC::regs().cr().read().wute() {
             trace!("rtc: stop wakeup alarm at {}", instant);
diff --git a/embassy-stm32/src/rtc/v2.rs b/embassy-stm32/src/rtc/v2.rs
index 23f6ccb0c..8ac022536 100644
--- a/embassy-stm32/src/rtc/v2.rs
+++ b/embassy-stm32/src/rtc/v2.rs
@@ -93,7 +93,7 @@ impl super::Rtc {
         })
     }
 
-    pub(super) fn write<F, R>(&self, init_mode: bool, f: F) -> R
+    pub(super) fn write<F, R>(&mut self, init_mode: bool, f: F) -> R
     where
         F: FnOnce(crate::pac::rtc::Rtc) -> R,
     {
diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs
index 01da5d70a..f7ebea73e 100644
--- a/embassy-stm32/src/rtc/v3.rs
+++ b/embassy-stm32/src/rtc/v3.rs
@@ -95,7 +95,7 @@ impl super::Rtc {
         })
     }
 
-    pub(super) fn write<F, R>(&self, init_mode: bool, f: F) -> R
+    pub(super) fn write<F, R>(&mut self, init_mode: bool, f: F) -> R
     where
         F: FnOnce(crate::pac::rtc::Rtc) -> R,
     {
@@ -131,7 +131,7 @@ impl SealedInstance for crate::peripherals::RTC {
 
     #[cfg(feature = "low-power")]
     cfg_if::cfg_if!(
-        if #[cfg(stm32g4)] {
+        if #[cfg(any(stm32g4, stm32wlex))] {
             const EXTI_WAKEUP_LINE: usize = 20;
         } else if #[cfg(stm32g0)] {
             const EXTI_WAKEUP_LINE: usize = 19;
@@ -142,7 +142,7 @@ impl SealedInstance for crate::peripherals::RTC {
 
     #[cfg(feature = "low-power")]
     cfg_if::cfg_if!(
-        if #[cfg(stm32g4)] {
+        if #[cfg(any(stm32g4, stm32wlex))] {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC_WKUP;
         } else if #[cfg(any(stm32g0, stm32u0))] {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC_TAMP;
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index 408d1b764..e05131040 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -1032,12 +1032,13 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
     /// Wait for a previously started datapath transfer to complete from an interrupt.
     #[inline]
+    #[allow(unused)]
     async fn complete_datapath_transfer(block: bool) -> Result<(), Error> {
-        let regs = T::regs();
-
         let res = poll_fn(|cx| {
+            // Compiler might not be sufficiently constrained here
+            // https://github.com/embassy-rs/embassy/issues/4723
             T::state().register(cx.waker());
-            let status = regs.star().read();
+            let status = T::regs().star().read();
 
             if status.dcrcfail() {
                 return Poll::Ready(Err(Error::Crc));
@@ -1052,10 +1053,13 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             if status.stbiterr() {
                 return Poll::Ready(Err(Error::StBitErr));
             }
+            #[cfg(sdmmc_v1)]
             let done = match block {
                 true => status.dbckend(),
                 false => status.dataend(),
             };
+            #[cfg(sdmmc_v2)]
+            let done = status.dataend();
             if done {
                 return Poll::Ready(Ok(()));
             }
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 74b10a183..4956d1f68 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -1,6 +1,8 @@
 #![allow(non_snake_case)]
 
 use core::cell::{Cell, RefCell};
+#[cfg(all(feature = "low-power", stm32wlex))]
+use core::sync::atomic::AtomicU16;
 use core::sync::atomic::{AtomicU32, Ordering, compiler_fence};
 
 use critical_section::CriticalSection;
@@ -213,7 +215,10 @@ pub(crate) struct RtcDriver {
     period: AtomicU32,
     alarm: Mutex<CriticalSectionRawMutex, AlarmState>,
     #[cfg(feature = "low-power")]
-    rtc: Mutex<CriticalSectionRawMutex, Cell<Option<&'static Rtc>>>,
+    rtc: Mutex<CriticalSectionRawMutex, RefCell<Option<Rtc>>>,
+    /// Saved count for the timer (its value is lost when entering STOP2)
+    #[cfg(all(feature = "low-power", stm32wlex))]
+    saved_count: AtomicU16,
     queue: Mutex<CriticalSectionRawMutex, RefCell<Queue>>,
 }
 
@@ -221,12 +226,16 @@ embassy_time_driver::time_driver_impl!(static DRIVER: RtcDriver = RtcDriver {
     period: AtomicU32::new(0),
     alarm: Mutex::const_new(CriticalSectionRawMutex::new(), AlarmState::new()),
     #[cfg(feature = "low-power")]
-    rtc: Mutex::const_new(CriticalSectionRawMutex::new(), Cell::new(None)),
+    rtc: Mutex::const_new(CriticalSectionRawMutex::new(), RefCell::new(None)),
+    #[cfg(all(feature = "low-power", stm32wlex))]
+    saved_count: AtomicU16::new(0),
     queue: Mutex::new(RefCell::new(Queue::new()))
 });
 
 impl RtcDriver {
-    fn init(&'static self, cs: critical_section::CriticalSection) {
+    /// initialize the timer, but don't start it.  Used for chips like stm32wle5
+    /// for low power where the timer config is lost in STOP2.
+    fn init_timer(&'static self, cs: critical_section::CriticalSection) {
         let r = regs_gp16();
 
         rcc::enable_and_reset_with_cs::<T>(cs);
@@ -259,10 +268,16 @@ impl RtcDriver {
             w.set_ccie(0, true);
         });
 
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        r.cnt().write(|w| w.set_cnt(self.saved_count.load(Ordering::SeqCst)));
+
         <T as GeneralInstance1Channel>::CaptureCompareInterrupt::unpend();
         unsafe { <T as GeneralInstance1Channel>::CaptureCompareInterrupt::enable() };
+    }
 
-        r.cr1().modify(|w| w.set_cen(true));
+    fn init(&'static self, cs: CriticalSection) {
+        self.init_timer(cs);
+        regs_gp16().cr1().modify(|w| w.set_cen(true));
     }
 
     fn on_interrupt(&self) {
@@ -379,7 +394,7 @@ impl RtcDriver {
     #[cfg(feature = "low-power")]
     /// Stop the wakeup alarm, if enabled, and add the appropriate offset
     fn stop_wakeup_alarm(&self, cs: CriticalSection) {
-        if let Some(offset) = self.rtc.borrow(cs).get().unwrap().stop_wakeup_alarm(cs) {
+        if let Some(offset) = self.rtc.borrow(cs).borrow_mut().as_mut().unwrap().stop_wakeup_alarm(cs) {
             self.add_time(offset, cs);
         }
     }
@@ -389,7 +404,7 @@ impl RtcDriver {
     */
     #[cfg(feature = "low-power")]
     /// Set the rtc but panic if it's already been set
-    pub(crate) fn set_rtc(&self, rtc: &'static Rtc) {
+    pub(crate) fn set_rtc(&self, mut rtc: Rtc) {
         critical_section::with(|cs| {
             rtc.stop_wakeup_alarm(cs);
 
@@ -398,6 +413,12 @@ impl RtcDriver {
     }
 
     #[cfg(feature = "low-power")]
+    /// Set the rtc but panic if it's already been set
+    pub(crate) fn reconfigure_rtc(&self, f: impl FnOnce(&mut Rtc)) {
+        critical_section::with(|cs| f(self.rtc.borrow(cs).borrow_mut().as_mut().unwrap()));
+    }
+
+    #[cfg(feature = "low-power")]
     /// The minimum pause time beyond which the executor will enter a low-power state.
     pub(crate) const MIN_STOP_PAUSE: embassy_time::Duration = embassy_time::Duration::from_millis(250);
 
@@ -414,16 +435,24 @@ impl RtcDriver {
 
             let time_until_next_alarm = self.time_until_next_alarm(cs);
             if time_until_next_alarm < Self::MIN_STOP_PAUSE {
+                trace!(
+                    "time_until_next_alarm < Self::MIN_STOP_PAUSE ({})",
+                    time_until_next_alarm
+                );
                 Err(())
             } else {
                 self.rtc
                     .borrow(cs)
-                    .get()
+                    .borrow_mut()
+                    .as_mut()
                     .unwrap()
                     .start_wakeup_alarm(time_until_next_alarm, cs);
 
                 regs_gp16().cr1().modify(|w| w.set_cen(false));
-
+                // save the count for the timer as its lost in STOP2 for stm32wlex
+                #[cfg(stm32wlex)]
+                self.saved_count
+                    .store(regs_gp16().cnt().read().cnt() as u16, Ordering::SeqCst);
                 Ok(())
             }
         })
@@ -521,3 +550,8 @@ pub(crate) fn get_driver() -> &'static RtcDriver {
 pub(crate) fn init(cs: CriticalSection) {
     DRIVER.init(cs)
 }
+
+#[cfg(all(feature = "low-power", stm32wlex))]
+pub(crate) fn init_timer(cs: CriticalSection) {
+    DRIVER.init_timer(cs)
+}
diff --git a/embassy-stm32/src/vrefbuf/mod.rs b/embassy-stm32/src/vrefbuf/mod.rs
index b061306a0..43dd9c800 100644
--- a/embassy-stm32/src/vrefbuf/mod.rs
+++ b/embassy-stm32/src/vrefbuf/mod.rs
@@ -14,10 +14,10 @@ pub struct VoltageReferenceBuffer<'d, T: Instance> {
 #[cfg(rcc_wba)]
 fn get_refbuf_trim(voltage_scale: Vrs) -> usize {
     match voltage_scale {
-        Vrs::VREF0 => 0x0BFA_07A8usize,
-        Vrs::VREF1 => 0x0BFA_07A9usize,
-        Vrs::VREF2 => 0x0BFA_07AAusize,
-        Vrs::VREF3 => 0x0BFA_07ABusize,
+        Vrs::VREF0 => 0x0BFA_07ABusize,
+        Vrs::VREF1 => 0x0BFA_07AAusize,
+        Vrs::VREF2 => 0x0BFA_07A9usize,
+        Vrs::VREF3 => 0x0BFA_07A8usize,
         _ => panic!("Incorrect Vrs setting!"),
     }
 }
diff --git a/examples/rp/src/bin/pio_onewire.rs b/examples/rp/src/bin/pio_onewire.rs
index 102f13c45..6432edb8a 100644
--- a/examples/rp/src/bin/pio_onewire.rs
+++ b/examples/rp/src/bin/pio_onewire.rs
@@ -61,7 +61,7 @@ async fn main(_spawner: Spawner) {
             let mut data = [0; 9];
             onewire.read_bytes(&mut data).await;
             if crc8(&data) == 0 {
-                let temp = ((data[1] as u32) << 8 | data[0] as u32) as f32 / 16.;
+                let temp = ((data[1] as i16) << 8 | data[0] as i16) as f32 / 16.;
                 info!("Read device {:x}: {} deg C", device, temp);
             } else {
                 warn!("Reading device {:x} failed", device);
diff --git a/examples/rp/src/bin/pio_onewire_parasite.rs b/examples/rp/src/bin/pio_onewire_parasite.rs
index fd076dee0..78fb94b18 100644
--- a/examples/rp/src/bin/pio_onewire_parasite.rs
+++ b/examples/rp/src/bin/pio_onewire_parasite.rs
@@ -63,7 +63,7 @@ async fn main(_spawner: Spawner) {
             let mut data = [0; 9];
             onewire.read_bytes(&mut data).await;
             if crc8(&data) == 0 {
-                let temp = ((data[1] as u32) << 8 | data[0] as u32) as f32 / 16.;
+                let temp = ((data[1] as i16) << 8 | data[0] as i16) as f32 / 16.;
                 info!("Read device {:x}: {} deg C", device, temp);
             } else {
                 warn!("Reading device {:x} failed. {:02x}", device, data);
diff --git a/examples/rp235x/src/bin/pio_onewire.rs b/examples/rp235x/src/bin/pio_onewire.rs
index 102f13c45..6432edb8a 100644
--- a/examples/rp235x/src/bin/pio_onewire.rs
+++ b/examples/rp235x/src/bin/pio_onewire.rs
@@ -61,7 +61,7 @@ async fn main(_spawner: Spawner) {
             let mut data = [0; 9];
             onewire.read_bytes(&mut data).await;
             if crc8(&data) == 0 {
-                let temp = ((data[1] as u32) << 8 | data[0] as u32) as f32 / 16.;
+                let temp = ((data[1] as i16) << 8 | data[0] as i16) as f32 / 16.;
                 info!("Read device {:x}: {} deg C", device, temp);
             } else {
                 warn!("Reading device {:x} failed", device);
diff --git a/examples/rp235x/src/bin/pio_onewire_parasite.rs b/examples/rp235x/src/bin/pio_onewire_parasite.rs
index fd076dee0..78fb94b18 100644
--- a/examples/rp235x/src/bin/pio_onewire_parasite.rs
+++ b/examples/rp235x/src/bin/pio_onewire_parasite.rs
@@ -63,7 +63,7 @@ async fn main(_spawner: Spawner) {
             let mut data = [0; 9];
             onewire.read_bytes(&mut data).await;
             if crc8(&data) == 0 {
-                let temp = ((data[1] as u32) << 8 | data[0] as u32) as f32 / 16.;
+                let temp = ((data[1] as i16) << 8 | data[0] as i16) as f32 / 16.;
                 info!("Read device {:x}: {} deg C", device, temp);
             } else {
                 warn!("Reading device {:x} failed. {:02x}", device, data);
diff --git a/examples/stm32f4/src/bin/adc_dma.rs b/examples/stm32f4/src/bin/adc_dma.rs
index c24f01753..f8da91336 100644
--- a/examples/stm32f4/src/bin/adc_dma.rs
+++ b/examples/stm32f4/src/bin/adc_dma.rs
@@ -4,7 +4,7 @@ use cortex_m::singleton;
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::Peripherals;
-use embassy_stm32::adc::{Adc, RingBufferedAdc, SampleTime, Sequence};
+use embassy_stm32::adc::{Adc, AdcChannel, RingBufferedAdc, SampleTime};
 use embassy_time::Instant;
 use {defmt_rtt as _, panic_probe as _};
 
@@ -15,7 +15,7 @@ async fn main(spawner: Spawner) {
 }
 
 #[embassy_executor::task]
-async fn adc_task(mut p: Peripherals) {
+async fn adc_task(p: Peripherals) {
     const ADC_BUF_SIZE: usize = 1024;
     let adc_data: &mut [u16; ADC_BUF_SIZE] = singleton!(ADCDAT : [u16; ADC_BUF_SIZE] = [0u16; ADC_BUF_SIZE]).unwrap();
     let adc_data2: &mut [u16; ADC_BUF_SIZE] = singleton!(ADCDAT2 : [u16; ADC_BUF_SIZE] = [0u16; ADC_BUF_SIZE]).unwrap();
@@ -23,13 +23,24 @@ async fn adc_task(mut p: Peripherals) {
     let adc = Adc::new(p.ADC1);
     let adc2 = Adc::new(p.ADC2);
 
-    let mut adc: RingBufferedAdc<embassy_stm32::peripherals::ADC1> = adc.into_ring_buffered(p.DMA2_CH0, adc_data);
-    let mut adc2: RingBufferedAdc<embassy_stm32::peripherals::ADC2> = adc2.into_ring_buffered(p.DMA2_CH2, adc_data2);
-
-    adc.set_sample_sequence(Sequence::One, &mut p.PA0, SampleTime::CYCLES112);
-    adc.set_sample_sequence(Sequence::Two, &mut p.PA2, SampleTime::CYCLES112);
-    adc2.set_sample_sequence(Sequence::One, &mut p.PA1, SampleTime::CYCLES112);
-    adc2.set_sample_sequence(Sequence::Two, &mut p.PA3, SampleTime::CYCLES112);
+    let mut adc: RingBufferedAdc<embassy_stm32::peripherals::ADC1> = adc.into_ring_buffered(
+        p.DMA2_CH0,
+        adc_data,
+        [
+            (&mut p.PA0.degrade_adc(), SampleTime::CYCLES112),
+            (&mut p.PA2.degrade_adc(), SampleTime::CYCLES112),
+        ]
+        .into_iter(),
+    );
+    let mut adc2: RingBufferedAdc<embassy_stm32::peripherals::ADC2> = adc2.into_ring_buffered(
+        p.DMA2_CH2,
+        adc_data2,
+        [
+            (&mut p.PA1.degrade_adc(), SampleTime::CYCLES112),
+            (&mut p.PA3.degrade_adc(), SampleTime::CYCLES112),
+        ]
+        .into_iter(),
+    );
 
     // Note that overrun is a big consideration in this implementation. Whatever task is running the adc.read() calls absolutely must circle back around
     // to the adc.read() call before the DMA buffer is wrapped around > 1 time. At this point, the overrun is so significant that the context of
diff --git a/examples/stm32g0/src/bin/onewire_ds18b20.rs b/examples/stm32g0/src/bin/onewire_ds18b20.rs
index 62f8711a6..43ecca8c4 100644
--- a/examples/stm32g0/src/bin/onewire_ds18b20.rs
+++ b/examples/stm32g0/src/bin/onewire_ds18b20.rs
@@ -267,7 +267,7 @@ where
         }
 
         match Self::crc8(&data) == 0 {
-            true => Ok(((data[1] as u16) << 8 | data[0] as u16) as f32 / 16.),
+            true => Ok(((data[1] as i16) << 8 | data[0] as i16) as f32 / 16.),
             false => Err(()),
         }
     }
diff --git a/examples/stm32h5/src/bin/stop.rs b/examples/stm32h5/src/bin/stop.rs
index 3c4f49f64..2026d8f99 100644
--- a/examples/stm32h5/src/bin/stop.rs
+++ b/examples/stm32h5/src/bin/stop.rs
@@ -12,7 +12,6 @@ use embassy_stm32::rcc::{HSIPrescaler, LsConfig};
 use embassy_stm32::rtc::{Rtc, RtcConfig};
 use embassy_stm32::{Config, Peri};
 use embassy_time::Timer;
-use static_cell::StaticCell;
 use {defmt_rtt as _, panic_probe as _};
 
 #[cortex_m_rt::entry]
@@ -39,8 +38,6 @@ async fn async_main(spawner: Spawner) {
 
     // give the RTC to the executor...
     let rtc = Rtc::new(p.RTC, RtcConfig::default());
-    static RTC: StaticCell<Rtc> = StaticCell::new();
-    let rtc = RTC.init(rtc);
     embassy_stm32::low_power::stop_with_rtc(rtc);
 
     spawner.spawn(unwrap!(blinky(p.PB4.into())));
diff --git a/examples/stm32l4/src/bin/adc_dma.rs b/examples/stm32l4/src/bin/adc_dma.rs
new file mode 100644
index 000000000..7a9200edd
--- /dev/null
+++ b/examples/stm32l4/src/bin/adc_dma.rs
@@ -0,0 +1,51 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::Config;
+use embassy_stm32::adc::{Adc, AdcChannel, SampleTime};
+use {defmt_rtt as _, panic_probe as _};
+
+const DMA_BUF_LEN: usize = 512;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    info!("Hello World!");
+
+    let mut config = Config::default();
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.mux.adcsel = mux::Adcsel::SYS;
+    }
+    let p = embassy_stm32::init(config);
+
+    let mut adc = Adc::new(p.ADC1);
+    let mut adc_pin0 = p.PA0.degrade_adc();
+    let mut adc_pin1 = p.PA1.degrade_adc();
+    let mut adc_dma_buf = [0u16; DMA_BUF_LEN];
+    let mut measurements = [0u16; DMA_BUF_LEN / 2];
+    let mut ring_buffered_adc = adc.into_ring_buffered(
+        p.DMA1_CH1,
+        &mut adc_dma_buf,
+        [
+            (&mut adc_pin0, SampleTime::CYCLES640_5),
+            (&mut adc_pin1, SampleTime::CYCLES640_5),
+        ]
+        .into_iter(),
+    );
+
+    info!("starting measurement loop");
+    loop {
+        match ring_buffered_adc.read(&mut measurements).await {
+            Ok(_) => {
+                //note: originally there was a print here showing all the samples,
+                //but even that takes too much time and would cause adc overruns
+                info!("adc1 first 10 samples: {}", measurements[0..10]);
+            }
+            Err(e) => {
+                warn!("Error: {:?}", e);
+            }
+        }
+    }
+}
diff --git a/examples/stm32l5/src/bin/stop.rs b/examples/stm32l5/src/bin/stop.rs
index c34053190..7662dbfa8 100644
--- a/examples/stm32l5/src/bin/stop.rs
+++ b/examples/stm32l5/src/bin/stop.rs
@@ -9,7 +9,6 @@ use embassy_stm32::rcc::LsConfig;
 use embassy_stm32::rtc::{Rtc, RtcConfig};
 use embassy_stm32::{Config, Peri};
 use embassy_time::Timer;
-use static_cell::StaticCell;
 use {defmt_rtt as _, panic_probe as _};
 
 #[cortex_m_rt::entry]
@@ -30,8 +29,6 @@ async fn async_main(spawner: Spawner) {
 
     // give the RTC to the executor...
     let rtc = Rtc::new(p.RTC, RtcConfig::default());
-    static RTC: StaticCell<Rtc> = StaticCell::new();
-    let rtc = RTC.init(rtc);
     embassy_stm32::low_power::stop_with_rtc(rtc);
 
     spawner.spawn(unwrap!(blinky(p.PC7.into())));
diff --git a/examples/stm32wle5/.cargo/config.toml b/examples/stm32wle5/.cargo/config.toml
new file mode 100644
index 000000000..0178d377c
--- /dev/null
+++ b/examples/stm32wle5/.cargo/config.toml
@@ -0,0 +1,9 @@
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# replace your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip STM32WLE5JCIx --connect-under-reset"
+
+[build]
+target = "thumbv7em-none-eabi"
+
+[env]
+DEFMT_LOG = "info"
diff --git a/examples/stm32wle5/Cargo.toml b/examples/stm32wle5/Cargo.toml
new file mode 100644
index 000000000..f2fc4dd3d
--- /dev/null
+++ b/examples/stm32wle5/Cargo.toml
@@ -0,0 +1,38 @@
+[package]
+edition = "2024"
+name = "embassy-stm32wl-examples"
+version = "0.1.0"
+license = "MIT OR Apache-2.0"
+publish = false
+
+[dependencies]
+# Change stm32wl55jc-cm4 to your chip name, if necessary.
+embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = ["defmt", "stm32wle5jc", "time-driver-any", "memory-x", "unstable-pac", "exti", "low-power"] }
+embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
+embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
+embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-1_000"] }
+embassy-embedded-hal = { version = "0.5.0", path = "../../embassy-embedded-hal" }
+
+defmt = "1.0.1"
+defmt-rtt = { version = "1.1.0", optional = true }
+defmt-serial = { version = "0.10.0", optional = true }
+
+cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.0"
+embedded-hal = "1.0.0"
+embedded-storage = "0.3.1"
+panic-probe = { version = "1.0.0", features = ["print-defmt"] }
+static_cell = { version = "2.1.1", default-features = false }
+
+[profile.release]
+debug = 2
+
+[package.metadata.embassy]
+build = [
+  { target = "thumbv7em-none-eabi", artifact-dir = "out/examples/stm32wl" }
+]
+
+[features]
+default = ["defmt-serial"]
+defmt-rtt = ["dep:defmt-rtt"]
+defmt-serial = ["dep:defmt-serial"]
diff --git a/examples/stm32wle5/README.md b/examples/stm32wle5/README.md
new file mode 100644
index 000000000..18c3b5071
--- /dev/null
+++ b/examples/stm32wle5/README.md
@@ -0,0 +1,52 @@
+# Low Power Examples for STM32WLEx family
+
+Examples in this repo should work with [LoRa-E5 Dev Board](https://www.st.com/en/partner-products-and-services/lora-e5-development-kit.html) board.
+
+## Prerequsits
+
+- Connect a usb serial adapter to LPUart1 (this is where ALL logging will go)
+- Optional: Connect an amp meter that ran measure down to 0.1uA to the power test pins
+- `cargo install defmt-print` so you can print log messahes from LPUart1
+
+## Example Notes
+
+All examples will set all pins to analog mode before configuring pins for the example, if any. This saves about 500uA!!!!
+
+- the `adc` example will sleep in STOP1 betwen samples and the chip will only draw about 13uA while sleeping
+- the `blinky` example will sleep in STOP2 and the chip will only draw 1uA or less while sleeping
+- the `button_exti` example will sleep in STOP2 and the chip will only draw 1uA or less while sleeping
+- the `i2c` examples will sleep in STOP1 between reads and the chip only draw about 10uA while sleeping
+
+For each example you will need to start `defmt-print` with the example binary and the correct serial port in a seperate terminal.  Example:
+```
+defmt-print -w -v -e target/thumbv7em-none-eabi/debug/<module-name> serial --path /dev/cu.usbserial-00000000 --baud 115200
+```
+
+Run individual examples with
+```
+cargo flash --chip STM32WLE5JCIx --connect-under-reset --bin <module-name>
+```
+for example
+```
+cargo flash --chip STM32WLE5JCIx --connect-under-reset --bin blinky
+```
+
+You can also run them with with `run`.  However in this case expect probe-rs to be disconnected as soon as flashing is done as all IO pins are set to analog input!
+```
+cargo run --bin blinky
+```
+
+## Checklist before running examples
+You might need to adjust `.cargo/config.toml`, `Cargo.toml` and possibly update pin numbers or peripherals to match the specific MCU or board you are using.
+
+* [ ] Update .cargo/config.toml with the correct probe-rs command to use your specific MCU. For example for L432KCU6 it should be `probe-rs run --chip STM32L432KCUx`. (use `probe-rs chip list` to find your chip)
+* [ ] Update Cargo.toml to have the correct `embassy-stm32` feature. For example for L432KCU6 it should be `stm32l432kc`. Look in the `Cargo.toml` file of the `embassy-stm32` project to find the correct feature flag for your chip.
+* [ ] If your board has a special clock or power configuration, make sure that it is set up appropriately.
+* [ ] If your board has different pin mapping, update any pin numbers or peripherals in the given example code to match your schematic
+
+If you are unsure, please drop by the Embassy Matrix chat for support, and let us know:
+
+* Which example you are trying to run
+* Which chip and board you are using
+
+Embassy Chat: https://matrix.to/#/#embassy-rs:matrix.org
diff --git a/examples/stm32wle5/build.rs b/examples/stm32wle5/build.rs
new file mode 100644
index 000000000..8cd32d7ed
--- /dev/null
+++ b/examples/stm32wle5/build.rs
@@ -0,0 +1,5 @@
+fn main() {
+    println!("cargo:rustc-link-arg-bins=--nmagic");
+    println!("cargo:rustc-link-arg-bins=-Tlink.x");
+    println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
+}
diff --git a/examples/stm32wle5/src/bin/adc.rs b/examples/stm32wle5/src/bin/adc.rs
new file mode 100644
index 000000000..ff1a5fa16
--- /dev/null
+++ b/examples/stm32wle5/src/bin/adc.rs
@@ -0,0 +1,100 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+#[cfg(feature = "defmt-rtt")]
+use defmt_rtt as _;
+use embassy_executor::Spawner;
+use embassy_stm32::adc::{Adc, SampleTime};
+use embassy_stm32::low_power::Executor;
+use embassy_stm32::rtc::{Rtc, RtcConfig};
+use embassy_time::Timer;
+use panic_probe as _;
+use static_cell::StaticCell;
+
+#[cortex_m_rt::entry]
+fn main() -> ! {
+    info!("main: Starting!");
+    Executor::take().run(|spawner| {
+        spawner.spawn(unwrap!(async_main(spawner)));
+    });
+}
+
+#[embassy_executor::task]
+async fn async_main(_spawner: Spawner) {
+    let mut config = embassy_stm32::Config::default();
+    // enable HSI clock
+    config.rcc.hsi = true;
+    // enable LSI clock for RTC
+    config.rcc.ls = embassy_stm32::rcc::LsConfig::default_lsi();
+    config.rcc.msi = Some(embassy_stm32::rcc::MSIRange::RANGE4M);
+    config.rcc.sys = embassy_stm32::rcc::Sysclk::MSI;
+    // enable ADC with HSI clock
+    config.rcc.mux.adcsel = embassy_stm32::pac::rcc::vals::Adcsel::HSI;
+    #[cfg(feature = "defmt-serial")]
+    {
+        // disable debug during sleep to reduce power consumption since we are
+        // using defmt-serial on LPUART1.
+        config.enable_debug_during_sleep = false;
+        // if we are using defmt-serial on LPUART1, we need to use HSI for the clock
+        // so that its registers are preserved during STOP modes.
+        config.rcc.mux.lpuart1sel = embassy_stm32::pac::rcc::vals::Lpuart1sel::HSI;
+    }
+    // Initialize STM32WL peripherals (use default config like wio-e5-async example)
+    let p = embassy_stm32::init(config);
+
+    // start with all GPIOs as analog to reduce power consumption
+    for r in [
+        embassy_stm32::pac::GPIOA,
+        embassy_stm32::pac::GPIOB,
+        embassy_stm32::pac::GPIOC,
+        embassy_stm32::pac::GPIOH,
+    ] {
+        r.moder().modify(|w| {
+            for i in 0..16 {
+                // don't reset these if probe-rs should stay connected!
+                #[cfg(feature = "defmt-rtt")]
+                if config.enable_debug_during_sleep && r == embassy_stm32::pac::GPIOA && [13, 14].contains(&i) {
+                    continue;
+                }
+                w.set_moder(i, embassy_stm32::pac::gpio::vals::Moder::ANALOG);
+            }
+        });
+    }
+    #[cfg(feature = "defmt-serial")]
+    {
+        use embassy_stm32::mode::Blocking;
+        use embassy_stm32::usart::Uart;
+        let config = embassy_stm32::usart::Config::default();
+        let uart = Uart::new_blocking(p.LPUART1, p.PC0, p.PC1, config).expect("failed to configure UART!");
+        static SERIAL: StaticCell<Uart<'static, Blocking>> = StaticCell::new();
+        defmt_serial::defmt_serial(SERIAL.init(uart));
+    }
+
+    // give the RTC to the low_power executor...
+    let rtc_config = RtcConfig::default();
+    let rtc = Rtc::new(p.RTC, rtc_config);
+    embassy_stm32::low_power::stop_with_rtc(rtc);
+
+    info!("Hello World!");
+
+    let mut adc = Adc::new(p.ADC1);
+    adc.set_sample_time(SampleTime::CYCLES79_5);
+    let mut pin = p.PA10;
+
+    let mut vrefint = adc.enable_vrefint();
+    let vrefint_sample = adc.blocking_read(&mut vrefint);
+    let convert_to_millivolts = |sample| {
+        // From https://www.st.com/resource/en/datasheet/stm32g031g8.pdf
+        // 6.3.3 Embedded internal reference voltage
+        const VREFINT_MV: u32 = 1212; // mV
+
+        (u32::from(sample) * VREFINT_MV / u32::from(vrefint_sample)) as u16
+    };
+
+    loop {
+        let v = adc.blocking_read(&mut pin);
+        info!("--> {} - {} mV", v, convert_to_millivolts(v));
+        Timer::after_secs(1).await;
+    }
+}
diff --git a/examples/stm32wle5/src/bin/blinky.rs b/examples/stm32wle5/src/bin/blinky.rs
new file mode 100644
index 000000000..1191a1157
--- /dev/null
+++ b/examples/stm32wle5/src/bin/blinky.rs
@@ -0,0 +1,90 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+#[cfg(feature = "defmt-rtt")]
+use defmt_rtt as _;
+use embassy_executor::Spawner;
+use embassy_stm32::gpio::{Level, Output, Speed};
+use embassy_stm32::low_power::Executor;
+use embassy_stm32::rtc::{Rtc, RtcConfig};
+use embassy_time::Timer;
+use panic_probe as _;
+use static_cell::StaticCell;
+
+#[cortex_m_rt::entry]
+fn main() -> ! {
+    info!("main: Starting!");
+    Executor::take().run(|spawner| {
+        spawner.spawn(unwrap!(async_main(spawner)));
+    });
+}
+
+#[embassy_executor::task]
+async fn async_main(_spawner: Spawner) {
+    let mut config = embassy_stm32::Config::default();
+    // enable HSI clock
+    config.rcc.hsi = true;
+    // enable LSI clock for RTC
+    config.rcc.ls = embassy_stm32::rcc::LsConfig::default_lsi();
+    config.rcc.msi = Some(embassy_stm32::rcc::MSIRange::RANGE4M);
+    config.rcc.sys = embassy_stm32::rcc::Sysclk::MSI;
+    #[cfg(feature = "defmt-serial")]
+    {
+        // disable debug during sleep to reduce power consumption since we are
+        // using defmt-serial on LPUART1.
+        config.enable_debug_during_sleep = false;
+        // if we are using defmt-serial on LPUART1, we need to use HSI for the clock
+        // so that its registers are preserved during STOP modes.
+        config.rcc.mux.lpuart1sel = embassy_stm32::pac::rcc::vals::Lpuart1sel::HSI;
+    }
+    // Initialize STM32WL peripherals (use default config like wio-e5-async example)
+    let p = embassy_stm32::init(config);
+
+    // start with all GPIOs as analog to reduce power consumption
+    for r in [
+        embassy_stm32::pac::GPIOA,
+        embassy_stm32::pac::GPIOB,
+        embassy_stm32::pac::GPIOC,
+        embassy_stm32::pac::GPIOH,
+    ] {
+        r.moder().modify(|w| {
+            for i in 0..16 {
+                // don't reset these if probe-rs should stay connected!
+                #[cfg(feature = "defmt-rtt")]
+                if config.enable_debug_during_sleep && r == embassy_stm32::pac::GPIOA && [13, 14].contains(&i) {
+                    continue;
+                }
+                w.set_moder(i, embassy_stm32::pac::gpio::vals::Moder::ANALOG);
+            }
+        });
+    }
+    #[cfg(feature = "defmt-serial")]
+    {
+        use embassy_stm32::mode::Blocking;
+        use embassy_stm32::usart::Uart;
+        let config = embassy_stm32::usart::Config::default();
+        let uart = Uart::new_blocking(p.LPUART1, p.PC0, p.PC1, config).expect("failed to configure UART!");
+        static SERIAL: StaticCell<Uart<'static, Blocking>> = StaticCell::new();
+        defmt_serial::defmt_serial(SERIAL.init(uart));
+    }
+
+    // give the RTC to the low_power executor...
+    let rtc_config = RtcConfig::default();
+    let rtc = Rtc::new(p.RTC, rtc_config);
+    embassy_stm32::low_power::stop_with_rtc(rtc);
+
+    info!("Hello World!");
+
+    let mut led = Output::new(p.PB5, Level::High, Speed::Low);
+
+    loop {
+        info!("low");
+        led.set_low();
+        Timer::after_millis(500).await;
+
+        info!("high");
+        led.set_high();
+        Timer::after_millis(500).await;
+    }
+}
diff --git a/examples/stm32wle5/src/bin/button_exti.rs b/examples/stm32wle5/src/bin/button_exti.rs
new file mode 100644
index 000000000..f07f9724d
--- /dev/null
+++ b/examples/stm32wle5/src/bin/button_exti.rs
@@ -0,0 +1,91 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+#[cfg(feature = "defmt-rtt")]
+use defmt_rtt as _;
+use embassy_executor::Spawner;
+use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::gpio::Pull;
+use embassy_stm32::low_power::Executor;
+use embassy_stm32::rtc::{Rtc, RtcConfig};
+use panic_probe as _;
+use static_cell::StaticCell;
+
+#[cortex_m_rt::entry]
+fn main() -> ! {
+    info!("main: Starting!");
+    Executor::take().run(|spawner| {
+        spawner.spawn(unwrap!(async_main(spawner)));
+    });
+}
+
+#[embassy_executor::task]
+async fn async_main(_spawner: Spawner) {
+    let mut config = embassy_stm32::Config::default();
+    // enable HSI clock
+    config.rcc.hsi = true;
+    // enable LSI clock for RTC
+    config.rcc.ls = embassy_stm32::rcc::LsConfig::default_lsi();
+    config.rcc.msi = Some(embassy_stm32::rcc::MSIRange::RANGE4M);
+    config.rcc.sys = embassy_stm32::rcc::Sysclk::MSI;
+    // enable ADC with HSI clock
+    config.rcc.mux.adcsel = embassy_stm32::pac::rcc::vals::Adcsel::HSI;
+    #[cfg(feature = "defmt-serial")]
+    {
+        // disable debug during sleep to reduce power consumption since we are
+        // using defmt-serial on LPUART1.
+        config.enable_debug_during_sleep = false;
+        // if we are using defmt-serial on LPUART1, we need to use HSI for the clock
+        // so that its registers are preserved during STOP modes.
+        config.rcc.mux.lpuart1sel = embassy_stm32::pac::rcc::vals::Lpuart1sel::HSI;
+    }
+    // Initialize STM32WL peripherals (use default config like wio-e5-async example)
+    let p = embassy_stm32::init(config);
+
+    // start with all GPIOs as analog to reduce power consumption
+    for r in [
+        embassy_stm32::pac::GPIOA,
+        embassy_stm32::pac::GPIOB,
+        embassy_stm32::pac::GPIOC,
+        embassy_stm32::pac::GPIOH,
+    ] {
+        r.moder().modify(|w| {
+            for i in 0..16 {
+                // don't reset these if probe-rs should stay connected!
+                #[cfg(feature = "defmt-rtt")]
+                if config.enable_debug_during_sleep && r == embassy_stm32::pac::GPIOA && [13, 14].contains(&i) {
+                    continue;
+                }
+                w.set_moder(i, embassy_stm32::pac::gpio::vals::Moder::ANALOG);
+            }
+        });
+    }
+    #[cfg(feature = "defmt-serial")]
+    {
+        use embassy_stm32::mode::Blocking;
+        use embassy_stm32::usart::Uart;
+        let config = embassy_stm32::usart::Config::default();
+        let uart = Uart::new_blocking(p.LPUART1, p.PC0, p.PC1, config).expect("failed to configure UART!");
+        static SERIAL: StaticCell<Uart<'static, Blocking>> = StaticCell::new();
+        defmt_serial::defmt_serial(SERIAL.init(uart));
+    }
+
+    // give the RTC to the low_power executor...
+    let rtc_config = RtcConfig::default();
+    let rtc = Rtc::new(p.RTC, rtc_config);
+    embassy_stm32::low_power::stop_with_rtc(rtc);
+
+    info!("Hello World!");
+
+    let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Up);
+
+    info!("Press the USER button...");
+
+    loop {
+        button.wait_for_falling_edge().await;
+        info!("Pressed!");
+        button.wait_for_rising_edge().await;
+        info!("Released!");
+    }
+}
diff --git a/examples/stm32wle5/src/bin/i2c.rs b/examples/stm32wle5/src/bin/i2c.rs
new file mode 100644
index 000000000..af07f911e
--- /dev/null
+++ b/examples/stm32wle5/src/bin/i2c.rs
@@ -0,0 +1,110 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+#[cfg(feature = "defmt-rtt")]
+use defmt_rtt as _;
+use embassy_executor::Spawner;
+use embassy_stm32::i2c::I2c;
+use embassy_stm32::low_power::Executor;
+use embassy_stm32::rtc::{Rtc, RtcConfig};
+use embassy_stm32::time::Hertz;
+use embassy_stm32::{bind_interrupts, i2c, peripherals};
+use embassy_time::{Duration, Timer};
+use panic_probe as _;
+use static_cell::StaticCell;
+
+bind_interrupts!(struct IrqsI2C{
+    I2C2_EV => i2c::EventInterruptHandler<peripherals::I2C2>;
+    I2C2_ER => i2c::ErrorInterruptHandler<peripherals::I2C2>;
+});
+
+#[cortex_m_rt::entry]
+fn main() -> ! {
+    info!("main: Starting!");
+    Executor::take().run(|spawner| {
+        spawner.spawn(unwrap!(async_main(spawner)));
+    });
+}
+
+#[embassy_executor::task]
+async fn async_main(_spawner: Spawner) {
+    let mut config = embassy_stm32::Config::default();
+    // enable HSI clock
+    config.rcc.hsi = true;
+    // enable LSI clock for RTC
+    config.rcc.ls = embassy_stm32::rcc::LsConfig::default_lsi();
+    config.rcc.msi = Some(embassy_stm32::rcc::MSIRange::RANGE4M);
+    config.rcc.sys = embassy_stm32::rcc::Sysclk::MSI;
+    // enable ADC with HSI clock
+    config.rcc.mux.i2c2sel = embassy_stm32::pac::rcc::vals::I2c2sel::HSI;
+    #[cfg(feature = "defmt-serial")]
+    {
+        // disable debug during sleep to reduce power consumption since we are
+        // using defmt-serial on LPUART1.
+        config.enable_debug_during_sleep = false;
+        // if we are using defmt-serial on LPUART1, we need to use HSI for the clock
+        // so that its registers are preserved during STOP modes.
+        config.rcc.mux.lpuart1sel = embassy_stm32::pac::rcc::vals::Lpuart1sel::HSI;
+    }
+    // Initialize STM32WL peripherals (use default config like wio-e5-async example)
+    let p = embassy_stm32::init(config);
+
+    // start with all GPIOs as analog to reduce power consumption
+    for r in [
+        embassy_stm32::pac::GPIOA,
+        embassy_stm32::pac::GPIOB,
+        embassy_stm32::pac::GPIOC,
+        embassy_stm32::pac::GPIOH,
+    ] {
+        r.moder().modify(|w| {
+            for i in 0..16 {
+                // don't reset these if probe-rs should stay connected!
+                #[cfg(feature = "defmt-rtt")]
+                if config.enable_debug_during_sleep && r == embassy_stm32::pac::GPIOA && [13, 14].contains(&i) {
+                    continue;
+                }
+                w.set_moder(i, embassy_stm32::pac::gpio::vals::Moder::ANALOG);
+            }
+        });
+    }
+    #[cfg(feature = "defmt-serial")]
+    {
+        use embassy_stm32::mode::Blocking;
+        use embassy_stm32::usart::Uart;
+        let config = embassy_stm32::usart::Config::default();
+        let uart = Uart::new_blocking(p.LPUART1, p.PC0, p.PC1, config).expect("failed to configure UART!");
+        static SERIAL: StaticCell<Uart<'static, Blocking>> = StaticCell::new();
+        defmt_serial::defmt_serial(SERIAL.init(uart));
+    }
+
+    // give the RTC to the low_power executor...
+    let rtc_config = RtcConfig::default();
+    let rtc = Rtc::new(p.RTC, rtc_config);
+    embassy_stm32::low_power::stop_with_rtc(rtc);
+
+    info!("Hello World!");
+    let en3v3 = embassy_stm32::gpio::Output::new(
+        p.PA9,
+        embassy_stm32::gpio::Level::High,
+        embassy_stm32::gpio::Speed::High,
+    );
+    core::mem::forget(en3v3); // keep the output pin enabled
+
+    let mut i2c = I2c::new(p.I2C2, p.PB15, p.PA15, IrqsI2C, p.DMA1_CH6, p.DMA1_CH7, {
+        let mut config = i2c::Config::default();
+        config.frequency = Hertz::khz(100);
+        config.timeout = Duration::from_millis(500);
+        config
+    });
+
+    loop {
+        let mut buffer = [0; 2];
+        // read the temperature register of the onboard lm75
+        match i2c.read(0x48, &mut buffer).await {
+            Ok(_) => info!("--> {:?}", buffer),
+            Err(e) => info!("--> Error: {:?}", e),
+        }
+        Timer::after_secs(5).await;
+    }
+}
diff --git a/examples/stm32wle5/stm32wle5.code-workspace b/examples/stm32wle5/stm32wle5.code-workspace
new file mode 100644
index 000000000..a7c4a0ebd
--- /dev/null
+++ b/examples/stm32wle5/stm32wle5.code-workspace
@@ -0,0 +1,13 @@
+{
+        "folders": [
+                {
+                        "path": "."
+                }
+        ],
+        "settings": {
+                "rust-analyzer.cargo.target": "thumbv7em-none-eabi",
+                "rust-analyzer.cargo.allTargets": false,
+                "rust-analyzer.cargo.targetDir": "target/rust-analyzer",
+                "rust-analyzer.checkOnSave": true,
+        }
+}
diff --git a/tests/stm32/src/bin/stop.rs b/tests/stm32/src/bin/stop.rs
index 833ca05d0..73580f0f2 100644
--- a/tests/stm32/src/bin/stop.rs
+++ b/tests/stm32/src/bin/stop.rs
@@ -14,7 +14,6 @@ use embassy_stm32::low_power::{Executor, StopMode, stop_ready, stop_with_rtc};
 use embassy_stm32::rcc::LsConfig;
 use embassy_stm32::rtc::{Rtc, RtcConfig};
 use embassy_time::Timer;
-use static_cell::StaticCell;
 
 #[entry]
 fn main() -> ! {
@@ -70,9 +69,6 @@ async fn async_main(spawner: Spawner) {
 
     rtc.set_datetime(now.into()).expect("datetime not set");
 
-    static RTC: StaticCell<Rtc> = StaticCell::new();
-    let rtc = RTC.init(rtc);
-
     stop_with_rtc(rtc);
 
     spawner.spawn(task_1().unwrap());