diff options
| author | Ulf Lilleengen <[email protected]> | 2021-12-07 09:40:45 +0100 |
|---|---|---|
| committer | Ulf Lilleengen <[email protected]> | 2021-12-07 09:40:45 +0100 |
| commit | f9ac0c80476db8cc33bd07beb7b48b6e96b053e7 (patch) | |
| tree | dc889c5ac3f997f6117ec25ab6e9e616ef1e3c3b | |
| parent | 56bcc824e093aef3d523adc3ac6f3fe7db9c347f (diff) | |
Add back MISO flush
| -rw-r--r-- | embassy-stm32/src/spi/v2.rs | 5 | ||||
| -rw-r--r-- | embassy-stm32/src/spi/v3.rs | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs index de78676c2..e24710dfe 100644 --- a/embassy-stm32/src/spi/v2.rs +++ b/embassy-stm32/src/spi/v2.rs | |||
| @@ -14,6 +14,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||
| 14 | T::regs().cr1().modify(|w| { | 14 | T::regs().cr1().modify(|w| { |
| 15 | w.set_spe(false); | 15 | w.set_spe(false); |
| 16 | }); | 16 | }); |
| 17 | |||
| 18 | // Flush the read buffer to avoid errornous data from being read | ||
| 19 | while T::regs().sr().read().rxne() { | ||
| 20 | let _ = T::regs().dr().read(); | ||
| 21 | } | ||
| 17 | } | 22 | } |
| 18 | self.set_word_size(WordSize::EightBit); | 23 | self.set_word_size(WordSize::EightBit); |
| 19 | 24 | ||
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs index ef0f23063..6d75de035 100644 --- a/embassy-stm32/src/spi/v3.rs +++ b/embassy-stm32/src/spi/v3.rs | |||
| @@ -15,6 +15,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||
| 15 | T::regs().cr1().modify(|w| { | 15 | T::regs().cr1().modify(|w| { |
| 16 | w.set_spe(false); | 16 | w.set_spe(false); |
| 17 | }); | 17 | }); |
| 18 | |||
| 19 | // Flush the read buffer to avoid errornous data from being read | ||
| 20 | while T::regs().sr().read().rxp() { | ||
| 21 | let _ = T::regs().rxdr().read(); | ||
| 22 | } | ||
| 18 | } | 23 | } |
| 19 | 24 | ||
| 20 | let request = self.txdma.request(); | 25 | let request = self.txdma.request(); |
