aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPiotr Esden-Tempski <[email protected]>2025-09-24 16:43:19 -0700
committerPiotr Esden-Tempski <[email protected]>2025-09-24 16:53:13 -0700
commitfc8c3e1e4babaa6344bdbab49a9542a29c88cc25 (patch)
treefc65db0d92a492b7c8fe3bc588f01bb9115e0525
parent56019ba197443e16b4f0b3a0fe3ff85985f6e45c (diff)
stm32-metapack: Corrects the RTC register map for l4p and l4q.
It also includes improvements in accuracy of the l412 and l422 RTC register map.
-rw-r--r--embassy-stm32/CHANGELOG.md2
-rw-r--r--embassy-stm32/Cargo.toml4
2 files changed, 4 insertions, 2 deletions
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 8fcc088fd..835d9c704 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -23,6 +23,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
23- feat: Allow OSPI DMA writes larger than 64kB using chunking 23- feat: Allow OSPI DMA writes larger than 64kB using chunking
24- feat: More ADC enums for g0 PAC, API change for oversampling, allow separate sample times 24- feat: More ADC enums for g0 PAC, API change for oversampling, allow separate sample times
25- feat: Add USB CRS sync support for STM32C071 25- feat: Add USB CRS sync support for STM32C071
26- fix: RTC register definition for STM32L4P5 and L4Q5 as they use v3 register map.
27- fix: Cut down the capabilities of the STM32L412 and L422 RTC as those are missing binary timer mode and underflow interrupt.
26 28
27## 0.4.0 - 2025-08-26 29## 0.4.0 - 2025-08-26
28 30
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 369fabc50..b029f33b0 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -174,7 +174,7 @@ futures-util = { version = "0.3.30", default-features = false }
174sdio-host = "0.9.0" 174sdio-host = "0.9.0"
175critical-section = "1.1" 175critical-section = "1.1"
176#stm32-metapac = { version = "18" } 176#stm32-metapac = { version = "18" }
177stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cf72eac610259fd78ef16f1c63be69a144d75f7" } 177stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-b46fcc32f329f05fbdca4c007ed4bc305b0ade85" }
178 178
179vcell = "0.1.3" 179vcell = "0.1.3"
180nb = "1.0.0" 180nb = "1.0.0"
@@ -204,7 +204,7 @@ proc-macro2 = "1.0.36"
204quote = "1.0.15" 204quote = "1.0.15"
205 205
206#stm32-metapac = { version = "18", default-features = false, features = ["metadata"]} 206#stm32-metapac = { version = "18", default-features = false, features = ["metadata"]}
207stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cf72eac610259fd78ef16f1c63be69a144d75f7", default-features = false, features = ["metadata"] } 207stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-b46fcc32f329f05fbdca4c007ed4bc305b0ade85", default-features = false, features = ["metadata"] }
208 208
209[features] 209[features]
210default = ["rt"] 210default = ["rt"]