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authorDario Nieuwenhuis <[email protected]>2023-07-06 13:49:19 +0200
committerDario Nieuwenhuis <[email protected]>2023-07-06 13:49:19 +0200
commitffeb40ff43ea52d0df5d5e6e807ecb87eafdf0c8 (patch)
tree3fe05abc65c6893889f6f53e9cb30cdae83ef62e
parent47305c2bf24c05b4956d9491478dfa53df09c47f (diff)
stm32/otg: change some info logs to trace.
-rw-r--r--embassy-stm32/src/usb_otg/usb.rs4
1 files changed, 2 insertions, 2 deletions
diff --git a/embassy-stm32/src/usb_otg/usb.rs b/embassy-stm32/src/usb_otg/usb.rs
index 6783db28d..492b77585 100644
--- a/embassy-stm32/src/usb_otg/usb.rs
+++ b/embassy-stm32/src/usb_otg/usb.rs
@@ -648,7 +648,7 @@ impl<'d, T: Instance> Bus<'d, T> {
648 648
649 let r = T::regs(); 649 let r = T::regs();
650 let core_id = r.cid().read().0; 650 let core_id = r.cid().read().0;
651 info!("Core id {:08x}", core_id); 651 trace!("Core id {:08x}", core_id);
652 652
653 // Wait for AHB ready. 653 // Wait for AHB ready.
654 while !r.grstctl().read().ahbidl() {} 654 while !r.grstctl().read().ahbidl() {}
@@ -1214,7 +1214,7 @@ impl<'d, T: Instance> embassy_usb_driver::EndpointIn for Endpoint<'d, T, In> {
1214 1214
1215 let diepctl = r.diepctl(index).read(); 1215 let diepctl = r.diepctl(index).read();
1216 let dtxfsts = r.dtxfsts(index).read(); 1216 let dtxfsts = r.dtxfsts(index).read();
1217 info!("diepctl {:08x} ftxfsts {:08x}", diepctl.0, dtxfsts.0); 1217 trace!("diepctl {:08x} ftxfsts {:08x}", diepctl.0, dtxfsts.0);
1218 if !diepctl.usbaep() { 1218 if !diepctl.usbaep() {
1219 trace!("write ep={:?} wait for prev: error disabled", self.info.addr); 1219 trace!("write ep={:?} wait for prev: error disabled", self.info.addr);
1220 Poll::Ready(Err(EndpointError::Disabled)) 1220 Poll::Ready(Err(EndpointError::Disabled))