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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2022-09-27 20:09:53 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2022-09-27 20:09:53 +0000 |
| commit | 9bb43ffe9adddb3497bb08d0730635fbd66cff94 (patch) | |
| tree | 89aa3e8c30251b666d4c932c7af7b44506d1e7ad /README.md | |
| parent | 5c882cf4faffe68dd376b90b6ce7504fd5d259c5 (diff) | |
| parent | bf1da0497ce1a591865f2bd8d0a29489079e710b (diff) | |
Merge #914
914: (embassy-rp): Add I2C master implementation r=Dirbaio a=MathiasKoch
This PR adds both blocking and DMA based async implementations of I2C master.
Both E-H 0.2 & E-H 1.0 abstractions are implemented as well.
### Questions & concerns:
- Do we need an I2C interrupt handler (for transfer done, abort & error handling?) (async only)
- Do we need to add some automatic attempt at unblocking an I2C bus in case of failures (see ref: https://github.com/fivdi/pico-i2c-dma/blob/7ebfd553f3ce5b5b210d53102b0ecca158172633/src/i2c_dma.c#L116-L142)
- Should I add `vectored_{read, write}` implementations?
Co-authored-by: Mathias <[email protected]>
Co-authored-by: Mathias Koch <[email protected]>
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