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authorAdam Greig <[email protected]>2023-10-15 00:57:25 +0100
committerAdam Greig <[email protected]>2023-10-15 01:30:12 +0100
commit0621e957a0ddc7010d46b3ea3ddc8b9852bc8333 (patch)
treef6caefe939109e55a73e9141c736d2f6c20f51e8 /cyw43
parent7559f9e5834799b041d899767ef4305dcfdf0181 (diff)
time: Update examples, tests, and other code to use new Timer::after_x convenience methods
Diffstat (limited to 'cyw43')
-rw-r--r--cyw43/src/bus.rs6
-rw-r--r--cyw43/src/control.rs24
-rw-r--r--cyw43/src/runner.rs4
3 files changed, 17 insertions, 17 deletions
diff --git a/cyw43/src/bus.rs b/cyw43/src/bus.rs
index 0b5632cf8..014109038 100644
--- a/cyw43/src/bus.rs
+++ b/cyw43/src/bus.rs
@@ -1,5 +1,5 @@
1use embassy_futures::yield_now; 1use embassy_futures::yield_now;
2use embassy_time::{Duration, Timer}; 2use embassy_time::Timer;
3use embedded_hal_1::digital::OutputPin; 3use embedded_hal_1::digital::OutputPin;
4use futures::FutureExt; 4use futures::FutureExt;
5 5
@@ -51,9 +51,9 @@ where
51 pub async fn init(&mut self) { 51 pub async fn init(&mut self) {
52 // Reset 52 // Reset
53 self.pwr.set_low().unwrap(); 53 self.pwr.set_low().unwrap();
54 Timer::after(Duration::from_millis(20)).await; 54 Timer::after_millis(20).await;
55 self.pwr.set_high().unwrap(); 55 self.pwr.set_high().unwrap();
56 Timer::after(Duration::from_millis(250)).await; 56 Timer::after_millis(250).await;
57 57
58 while self 58 while self
59 .read32_swapped(REG_BUS_TEST_RO) 59 .read32_swapped(REG_BUS_TEST_RO)
diff --git a/cyw43/src/control.rs b/cyw43/src/control.rs
index a6d1f0bf5..2585b31dc 100644
--- a/cyw43/src/control.rs
+++ b/cyw43/src/control.rs
@@ -2,7 +2,7 @@ use core::cmp::{max, min};
2 2
3use ch::driver::LinkState; 3use ch::driver::LinkState;
4use embassy_net_driver_channel as ch; 4use embassy_net_driver_channel as ch;
5use embassy_time::{Duration, Timer}; 5use embassy_time::Timer;
6 6
7pub use crate::bus::SpiBusCyw43; 7pub use crate::bus::SpiBusCyw43;
8use crate::consts::*; 8use crate::consts::*;
@@ -87,22 +87,22 @@ impl<'a> Control<'a> {
87 self.set_iovar("country", &country_info.to_bytes()).await; 87 self.set_iovar("country", &country_info.to_bytes()).await;
88 88
89 // set country takes some time, next ioctls fail if we don't wait. 89 // set country takes some time, next ioctls fail if we don't wait.
90 Timer::after(Duration::from_millis(100)).await; 90 Timer::after_millis(100).await;
91 91
92 // Set antenna to chip antenna 92 // Set antenna to chip antenna
93 self.ioctl_set_u32(IOCTL_CMD_ANTDIV, 0, 0).await; 93 self.ioctl_set_u32(IOCTL_CMD_ANTDIV, 0, 0).await;
94 94
95 self.set_iovar_u32("bus:txglom", 0).await; 95 self.set_iovar_u32("bus:txglom", 0).await;
96 Timer::after(Duration::from_millis(100)).await; 96 Timer::after_millis(100).await;
97 //self.set_iovar_u32("apsta", 1).await; // this crashes, also we already did it before...?? 97 //self.set_iovar_u32("apsta", 1).await; // this crashes, also we already did it before...??
98 //Timer::after(Duration::from_millis(100)).await; 98 //Timer::after_millis(100).await;
99 self.set_iovar_u32("ampdu_ba_wsize", 8).await; 99 self.set_iovar_u32("ampdu_ba_wsize", 8).await;
100 Timer::after(Duration::from_millis(100)).await; 100 Timer::after_millis(100).await;
101 self.set_iovar_u32("ampdu_mpdu", 4).await; 101 self.set_iovar_u32("ampdu_mpdu", 4).await;
102 Timer::after(Duration::from_millis(100)).await; 102 Timer::after_millis(100).await;
103 //self.set_iovar_u32("ampdu_rx_factor", 0).await; // this crashes 103 //self.set_iovar_u32("ampdu_rx_factor", 0).await; // this crashes
104 104
105 //Timer::after(Duration::from_millis(100)).await; 105 //Timer::after_millis(100).await;
106 106
107 // evts 107 // evts
108 let mut evts = EventMask { 108 let mut evts = EventMask {
@@ -121,17 +121,17 @@ impl<'a> Control<'a> {
121 121
122 self.set_iovar("bsscfg:event_msgs", &evts.to_bytes()).await; 122 self.set_iovar("bsscfg:event_msgs", &evts.to_bytes()).await;
123 123
124 Timer::after(Duration::from_millis(100)).await; 124 Timer::after_millis(100).await;
125 125
126 // set wifi up 126 // set wifi up
127 self.up().await; 127 self.up().await;
128 128
129 Timer::after(Duration::from_millis(100)).await; 129 Timer::after_millis(100).await;
130 130
131 self.ioctl_set_u32(110, 0, 1).await; // SET_GMODE = auto 131 self.ioctl_set_u32(110, 0, 1).await; // SET_GMODE = auto
132 self.ioctl_set_u32(142, 0, 0).await; // SET_BAND = any 132 self.ioctl_set_u32(142, 0, 0).await; // SET_BAND = any
133 133
134 Timer::after(Duration::from_millis(100)).await; 134 Timer::after_millis(100).await;
135 135
136 self.state_ch.set_ethernet_address(mac_addr); 136 self.state_ch.set_ethernet_address(mac_addr);
137 137
@@ -185,7 +185,7 @@ impl<'a> Control<'a> {
185 self.set_iovar_u32x2("bsscfg:sup_wpa2_eapver", 0, 0xFFFF_FFFF).await; 185 self.set_iovar_u32x2("bsscfg:sup_wpa2_eapver", 0, 0xFFFF_FFFF).await;
186 self.set_iovar_u32x2("bsscfg:sup_wpa_tmo", 0, 2500).await; 186 self.set_iovar_u32x2("bsscfg:sup_wpa_tmo", 0, 2500).await;
187 187
188 Timer::after(Duration::from_millis(100)).await; 188 Timer::after_millis(100).await;
189 189
190 let mut pfi = PassphraseInfo { 190 let mut pfi = PassphraseInfo {
191 len: passphrase.len() as _, 191 len: passphrase.len() as _,
@@ -297,7 +297,7 @@ impl<'a> Control<'a> {
297 if security != Security::OPEN { 297 if security != Security::OPEN {
298 self.set_iovar_u32x2("bsscfg:wpa_auth", 0, 0x0084).await; // wpa_auth = WPA2_AUTH_PSK | WPA_AUTH_PSK 298 self.set_iovar_u32x2("bsscfg:wpa_auth", 0, 0x0084).await; // wpa_auth = WPA2_AUTH_PSK | WPA_AUTH_PSK
299 299
300 Timer::after(Duration::from_millis(100)).await; 300 Timer::after_millis(100).await;
301 301
302 // Set passphrase 302 // Set passphrase
303 let mut pfi = PassphraseInfo { 303 let mut pfi = PassphraseInfo {
diff --git a/cyw43/src/runner.rs b/cyw43/src/runner.rs
index 1c187faa5..83aee6b40 100644
--- a/cyw43/src/runner.rs
+++ b/cyw43/src/runner.rs
@@ -555,14 +555,14 @@ where
555 555
556 self.bus.bp_write8(base + AI_RESETCTRL_OFFSET, 0).await; 556 self.bus.bp_write8(base + AI_RESETCTRL_OFFSET, 0).await;
557 557
558 Timer::after(Duration::from_millis(1)).await; 558 Timer::after_millis(1).await;
559 559
560 self.bus 560 self.bus
561 .bp_write8(base + AI_IOCTRL_OFFSET, AI_IOCTRL_BIT_CLOCK_EN) 561 .bp_write8(base + AI_IOCTRL_OFFSET, AI_IOCTRL_BIT_CLOCK_EN)
562 .await; 562 .await;
563 let _ = self.bus.bp_read8(base + AI_IOCTRL_OFFSET).await; 563 let _ = self.bus.bp_read8(base + AI_IOCTRL_OFFSET).await;
564 564
565 Timer::after(Duration::from_millis(1)).await; 565 Timer::after_millis(1).await;
566 } 566 }
567 567
568 async fn core_is_up(&mut self, core: Core) -> bool { 568 async fn core_is_up(&mut self, core: Core) -> bool {