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| author | Andres Vahter <[email protected]> | 2024-01-09 14:47:30 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2024-01-20 00:15:39 +0100 |
| commit | c936d66934225db8ddd283d7da2d7a158686df71 (patch) | |
| tree | 92d3a5e08658df7b7aa788581c2c4b47cc1dbddb /docs/modules/ROOT/examples/basic/Cargo.toml | |
| parent | 17d6e4eefeb9bdc9d7c3776afb815298be5b468c (diff) | |
stm32 uart: fix `flush` for non usart_v4 variants
Byte was written to TDR and right after that waker was called. This means `flush` would see that `tx_buf` is empty and can return Ready although actually hardware was still writing this last byte to the wire.
With this change non `usart_v4 ` variants would also use TC interrupt to check when last byte was sent out.
Diffstat (limited to 'docs/modules/ROOT/examples/basic/Cargo.toml')
0 files changed, 0 insertions, 0 deletions