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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2023-02-19 23:01:44 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-02-19 23:01:44 +0000 |
| commit | 1567e724f97cf271e7733430401cebcf3be841f7 (patch) | |
| tree | 7dc12939a7b4f4fc3e13bbe4e11f38d2ee752a04 /docs/modules/ROOT/examples | |
| parent | 4ad255b34b94f8526fa819f3b962aa43eccbdbcc (diff) | |
| parent | 7783e0ebb1a3870f3b180c87c1acd2807439f976 (diff) | |
| parent | a53f525f510de07e8c35d38ecc575cb8ea929dd9 (diff) | |
Merge #1218 #1219
1218: Lora: sx126x: Change timing window to match values found experimentally. r=Dirbaio a=CBJamo
As mentioned in #1188.
1219: stm32/sdmmc: Fix SDIOv1 writes r=Dirbaio a=chemicstry
This fixes writes on sdmmc v1 (SDIO). I'm pretty sure I tested writes in #669, but maybe I was just lucky or I just forgot.
There were two problems:
- Writes require DMA FIFO mode, otherwise SDIO FIFO is under/overrun depending on sdio/pclk2 clock ratio.
- Hardware flow control is broken for sdmmc v1 (I checked F1 and F4 erratas). This causes clock glitches above 12 MHz and results in write CRC errors.
Co-authored-by: Caleb Jamison <[email protected]>
Co-authored-by: chemicstry <[email protected]>