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authorEli Orona <[email protected]>2024-02-15 19:50:42 -0800
committerEli Orona <[email protected]>2024-02-15 19:50:42 -0800
commit169f1ce928177a6ff85ce7e9ff5a995063b6aace (patch)
treec54e5098a50e00edeb5aab1815fed34d6bddbe83 /docs/modules/ROOT/examples
parent26fc17e8a7db0957896db28cb2299ab9cf89aea5 (diff)
I believe that this enables the PLL clock input to different TIMs for the STM32F3xx Series of chips.
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