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| author | Timo Kröger <[email protected]> | 2022-12-27 10:20:51 +0100 |
|---|---|---|
| committer | Timo Kröger <[email protected]> | 2022-12-27 11:28:52 +0100 |
| commit | e4f457646f216f36cd86fcfe54af0d7956d17932 (patch) | |
| tree | d189e0e6f4e37cac576e722eaedc365df09feb70 /docs/modules | |
| parent | 3afb62d8d6d6f9737f3e2275e2bfb2a2f799b758 (diff) | |
rp: Fill and empty FIFOs in buffered uart interrupt
Fixes an issue where only the first byte was transmitted.
Should improve throughput aswell.
Diffstat (limited to 'docs/modules')
0 files changed, 0 insertions, 0 deletions