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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2022-03-04 17:07:04 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2022-03-04 17:07:04 +0000 |
| commit | 9ebf7eee6d4ec707699118b6bdc893ce9070ae5e (patch) | |
| tree | 3ccd309349e3b5af8f90419957f2b0986c61b823 /docs | |
| parent | 35636953b2048394733eaff95fad17970788d08a (diff) | |
| parent | 609975f8211c7256e82898297e020949eb8f9a52 (diff) | |
| parent | 265cd1115b5c2068452560054c28657cab060b4f (diff) | |
Merge #652 #653
652: Use new stm32-data registers and fix AHB clock calculation r=Dirbaio a=msamsonoff
This is the follow-on to my PR against stm32-data that added new register enums for the G0. I have updated the G0 RCC module to use those new enums.
I have also fixed an issue with the calculation of the AHB clock rate. 32 is not available as an AHB prescaler. The sequence jumps from 16 to 64. The original bit shifting math did not account for this gap. I have replaced it with a `match` instead.
653: Fixes for rustdoc building. r=Dirbaio a=Dirbaio
Co-authored-by: Matthew W. Samsonoff <[email protected]>
Co-authored-by: Dario Nieuwenhuis <[email protected]>