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authorDario Nieuwenhuis <[email protected]>2023-04-06 22:25:24 +0200
committerDario Nieuwenhuis <[email protected]>2023-04-06 22:41:50 +0200
commitbe37eee13dbd7833e0d74ea57d31d3e5c58cd47f (patch)
tree3e1d5a59409ea06fe34d97fdaf45642683332638 /embassy-embedded-hal/src/shared_bus/asynch/i2c.rs
parentf3ec6080bf9a39d9819195861e7b41e8a2081600 (diff)
Update embedded-hal crates.
Diffstat (limited to 'embassy-embedded-hal/src/shared_bus/asynch/i2c.rs')
-rw-r--r--embassy-embedded-hal/src/shared_bus/asynch/i2c.rs42
1 files changed, 19 insertions, 23 deletions
diff --git a/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs b/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs
index c5e1fd415..829554045 100644
--- a/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs
+++ b/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs
@@ -54,35 +54,35 @@ where
54 M: RawMutex + 'static, 54 M: RawMutex + 'static,
55 BUS: i2c::I2c + 'static, 55 BUS: i2c::I2c + 'static,
56{ 56{
57 async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> { 57 async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
58 let mut bus = self.bus.lock().await; 58 let mut bus = self.bus.lock().await;
59 bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?; 59 bus.read(address, read).await.map_err(I2cDeviceError::I2c)?;
60 Ok(()) 60 Ok(())
61 } 61 }
62 62
63 async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), I2cDeviceError<BUS::Error>> { 63 async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
64 let mut bus = self.bus.lock().await; 64 let mut bus = self.bus.lock().await;
65 bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?; 65 bus.write(address, write).await.map_err(I2cDeviceError::I2c)?;
66 Ok(()) 66 Ok(())
67 } 67 }
68 68
69 async fn write_read<'a>( 69 async fn write_read(
70 &'a mut self, 70 &mut self,
71 address: u8, 71 address: u8,
72 wr_buffer: &'a [u8], 72 write: &[u8],
73 rd_buffer: &'a mut [u8], 73 read: &mut [u8],
74 ) -> Result<(), I2cDeviceError<BUS::Error>> { 74 ) -> Result<(), I2cDeviceError<BUS::Error>> {
75 let mut bus = self.bus.lock().await; 75 let mut bus = self.bus.lock().await;
76 bus.write_read(address, wr_buffer, rd_buffer) 76 bus.write_read(address, write, read)
77 .await 77 .await
78 .map_err(I2cDeviceError::I2c)?; 78 .map_err(I2cDeviceError::I2c)?;
79 Ok(()) 79 Ok(())
80 } 80 }
81 81
82 async fn transaction<'a, 'b>( 82 async fn transaction(
83 &'a mut self, 83 &mut self,
84 address: u8, 84 address: u8,
85 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>], 85 operations: &mut [embedded_hal_async::i2c::Operation<'_>],
86 ) -> Result<(), I2cDeviceError<BUS::Error>> { 86 ) -> Result<(), I2cDeviceError<BUS::Error>> {
87 let _ = address; 87 let _ = address;
88 let _ = operations; 88 let _ = operations;
@@ -121,25 +121,25 @@ where
121 M: RawMutex + 'static, 121 M: RawMutex + 'static,
122 BUS: i2c::I2c + SetConfig + 'static, 122 BUS: i2c::I2c + SetConfig + 'static,
123{ 123{
124 async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> { 124 async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
125 let mut bus = self.bus.lock().await; 125 let mut bus = self.bus.lock().await;
126 bus.set_config(&self.config); 126 bus.set_config(&self.config);
127 bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?; 127 bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
128 Ok(()) 128 Ok(())
129 } 129 }
130 130
131 async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), I2cDeviceError<BUS::Error>> { 131 async fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
132 let mut bus = self.bus.lock().await; 132 let mut bus = self.bus.lock().await;
133 bus.set_config(&self.config); 133 bus.set_config(&self.config);
134 bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?; 134 bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
135 Ok(()) 135 Ok(())
136 } 136 }
137 137
138 async fn write_read<'a>( 138 async fn write_read(
139 &'a mut self, 139 &mut self,
140 address: u8, 140 address: u8,
141 wr_buffer: &'a [u8], 141 wr_buffer: &[u8],
142 rd_buffer: &'a mut [u8], 142 rd_buffer: &mut [u8],
143 ) -> Result<(), I2cDeviceError<BUS::Error>> { 143 ) -> Result<(), I2cDeviceError<BUS::Error>> {
144 let mut bus = self.bus.lock().await; 144 let mut bus = self.bus.lock().await;
145 bus.set_config(&self.config); 145 bus.set_config(&self.config);
@@ -149,11 +149,7 @@ where
149 Ok(()) 149 Ok(())
150 } 150 }
151 151
152 async fn transaction<'a, 'b>( 152 async fn transaction(&mut self, address: u8, operations: &mut [i2c::Operation<'_>]) -> Result<(), Self::Error> {
153 &'a mut self,
154 address: u8,
155 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
156 ) -> Result<(), I2cDeviceError<BUS::Error>> {
157 let _ = address; 153 let _ = address;
158 let _ = operations; 154 let _ = operations;
159 todo!() 155 todo!()