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authorHenrik Alsér <[email protected]>2022-07-06 03:31:21 +0200
committerHenrik Alsér <[email protected]>2022-07-06 03:31:21 +0200
commitd3d82ad87d9f170e4858ae30143fe44ab5ddd0bd (patch)
tree61bcfe93f82c5f123b21260f0a7875339a660f61 /embassy-embedded-hal/src
parent264b32d71baf471d0d36a34cc48aa10d429bed04 (diff)
Mutex
Diffstat (limited to 'embassy-embedded-hal/src')
-rw-r--r--embassy-embedded-hal/src/shared_bus/blocking/i2c.rs89
-rw-r--r--embassy-embedded-hal/src/shared_bus/blocking/spi.rs14
2 files changed, 59 insertions, 44 deletions
diff --git a/embassy-embedded-hal/src/shared_bus/blocking/i2c.rs b/embassy-embedded-hal/src/shared_bus/blocking/i2c.rs
index 2a6ea6dc8..2c762fe14 100644
--- a/embassy-embedded-hal/src/shared_bus/blocking/i2c.rs
+++ b/embassy-embedded-hal/src/shared_bus/blocking/i2c.rs
@@ -1,67 +1,82 @@
1//! Blocking shared I2C bus 1//! Blocking shared I2C bus
2use core::cell::RefCell; 2use core::cell::RefCell;
3use core::fmt::Debug;
4use core::future::Future;
5 3
6use embedded_hal_1::i2c; 4use embassy::blocking_mutex::raw::RawMutex;
5use embassy::blocking_mutex::Mutex;
6use embedded_hal_1::i2c::blocking::{I2c, Operation};
7use embedded_hal_1::i2c::ErrorType;
7 8
8#[derive(Copy, Clone, Eq, PartialEq, Debug)] 9use crate::shared_bus::i2c::I2cBusDeviceError;
9pub enum I2cBusDeviceError<BUS> {
10 I2c(BUS),
11}
12 10
13impl<BUS> i2c::Error for I2cBusDeviceError<BUS> 11pub struct I2cBusDevice<'a, M: RawMutex, BUS> {
14where 12 bus: &'a Mutex<M, RefCell<BUS>>,
15 BUS: i2c::Error + Debug,
16{
17 fn kind(&self) -> i2c::ErrorKind {
18 match self {
19 Self::I2c(e) => e.kind(),
20 }
21 }
22} 13}
23 14
24pub struct I2cBusDevice<'a, BUS> { 15impl<'a, M: RawMutex, BUS> I2cBusDevice<'a, M, BUS> {
25 bus: &'a RefCell<BUS>, 16 pub fn new(bus: &'a Mutex<M, RefCell<BUS>>) -> Self {
26}
27
28impl<'a, BUS> I2cBusDevice<'a, BUS> {
29 pub fn new(bus: &'a RefCell<BUS>) -> Self {
30 Self { bus } 17 Self { bus }
31 } 18 }
32} 19}
33 20
34impl<'a, BUS> i2c::ErrorType for I2cBusDevice<'a, BUS> 21impl<'a, M: RawMutex, BUS> ErrorType for I2cBusDevice<'a, M, BUS>
35where 22where
36 BUS: i2c::ErrorType, 23 BUS: ErrorType,
37{ 24{
38 type Error = I2cBusDeviceError<BUS::Error>; 25 type Error = I2cBusDeviceError<BUS::Error>;
39} 26}
40 27
41impl<M, BUS> i2c::I2c for I2cBusDevice<'_, BUS> 28impl<M, BUS> I2c for I2cBusDevice<'_, M, BUS>
42where 29where
43 BUS: i2c::I2c, 30 M: RawMutex,
31 BUS: I2c,
44{ 32{
45 fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> { 33 fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
46 let mut bus = self.bus.borrow_mut(); 34 self.bus
47 bus.read(address, buffer).map_err(I2cBusDeviceError::I2c)?; 35 .lock(|bus| bus.borrow_mut().read(address, buffer).map_err(I2cBusDeviceError::I2c))
48 Ok(())
49 } 36 }
50 37
51 fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> { 38 fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> {
52 let mut bus = self.bus.borrow_mut(); 39 self.bus
53 bus.write(address, bytes).map_err(I2cBusDeviceError::I2c)?; 40 .lock(|bus| bus.borrow_mut().write(address, bytes).map_err(I2cBusDeviceError::I2c))
54 Ok(())
55 } 41 }
56 42
57 fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> { 43 fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
58 let mut bus = self.bus.borrow_mut(); 44 self.bus.lock(|bus| {
59 bus.write_read(address, wr_buffer, rd_buffer) 45 bus.borrow_mut()
60 .map_err(I2cBusDeviceError::I2c)?; 46 .write_read(address, wr_buffer, rd_buffer)
61 Ok(()) 47 .map_err(I2cBusDeviceError::I2c)
48 })
49 }
50
51 fn transaction<'a>(&mut self, address: u8, operations: &mut [Operation<'a>]) -> Result<(), Self::Error> {
52 let _ = address;
53 let _ = operations;
54 todo!()
55 }
56
57 fn write_iter<B: IntoIterator<Item = u8>>(&mut self, addr: u8, bytes: B) -> Result<(), Self::Error> {
58 let _ = addr;
59 let _ = bytes;
60 todo!()
61 }
62
63 fn write_iter_read<B: IntoIterator<Item = u8>>(
64 &mut self,
65 addr: u8,
66 bytes: B,
67 buffer: &mut [u8],
68 ) -> Result<(), Self::Error> {
69 let _ = addr;
70 let _ = bytes;
71 let _ = buffer;
72 todo!()
62 } 73 }
63 74
64 fn transaction<'a>(&mut self, address: u8, operations: &mut [i2c::Operation<'a>]) -> Result<(), Self::Error> { 75 fn transaction_iter<'a, O: IntoIterator<Item = Operation<'a>>>(
76 &mut self,
77 address: u8,
78 operations: O,
79 ) -> Result<(), Self::Error> {
65 let _ = address; 80 let _ = address;
66 let _ = operations; 81 let _ = operations;
67 todo!() 82 todo!()
diff --git a/embassy-embedded-hal/src/shared_bus/blocking/spi.rs b/embassy-embedded-hal/src/shared_bus/blocking/spi.rs
index 0d01a590b..2583c699c 100644
--- a/embassy-embedded-hal/src/shared_bus/blocking/spi.rs
+++ b/embassy-embedded-hal/src/shared_bus/blocking/spi.rs
@@ -4,7 +4,7 @@ use core::fmt::Debug;
4 4
5use embedded_hal_1::digital::blocking::OutputPin; 5use embedded_hal_1::digital::blocking::OutputPin;
6use embedded_hal_1::spi; 6use embedded_hal_1::spi;
7use embedded_hal_1::spi::blocking::SpiDevice; 7use embedded_hal_1::spi::blocking::{SpiBusFlush, SpiDevice};
8 8
9#[derive(Copy, Clone, Eq, PartialEq, Debug)] 9#[derive(Copy, Clone, Eq, PartialEq, Debug)]
10pub enum SpiBusDeviceError<BUS, CS> { 10pub enum SpiBusDeviceError<BUS, CS> {
@@ -44,15 +44,15 @@ where
44 type Error = SpiBusDeviceError<BUS::Error, CS::Error>; 44 type Error = SpiBusDeviceError<BUS::Error, CS::Error>;
45} 45}
46 46
47impl<BUS, CS> spi::SpiDevice for SpiBusDevice<'_, BUS, CS> 47impl<BUS, CS> SpiDevice for SpiBusDevice<'_, BUS, CS>
48where 48where
49 BUS: spi::SpiBusFlush, 49 BUS: SpiBusFlush,
50 CS: OutputPin, 50 CS: OutputPin,
51{ 51{
52 type Bus = BUS; 52 type Bus = BUS;
53 fn transaction<R>(&mut self, f: impl FnOnce(&mut Self::Bus) -> Result<R, BUS::Error>) -> Result<R, Self::Error> { 53 fn transaction<R>(&mut self, f: impl FnOnce(&mut Self::Bus) -> Result<R, BUS::Error>) -> Result<R, Self::Error> {
54 let mut bus = self.bus.borrow_mut(); 54 let mut bus = self.bus.borrow_mut();
55 self.cs.set_low().map_err(SpiDeviceWithCsError::Cs)?; 55 self.cs.set_low().map_err(SpiBusDeviceError::Cs)?;
56 56
57 let f_res = f(&mut bus); 57 let f_res = f(&mut bus);
58 58
@@ -60,9 +60,9 @@ where
60 let flush_res = bus.flush(); 60 let flush_res = bus.flush();
61 let cs_res = self.cs.set_high(); 61 let cs_res = self.cs.set_high();
62 62
63 let f_res = f_res.map_err(SpiDeviceWithCsError::Spi)?; 63 let f_res = f_res.map_err(SpiBusDeviceError::Spi)?;
64 flush_res.map_err(SpiDeviceWithCsError::Spi)?; 64 flush_res.map_err(SpiBusDeviceError::Spi)?;
65 cs_res.map_err(SpiDeviceWithCsError::Cs)?; 65 cs_res.map_err(SpiBusDeviceError::Cs)?;
66 66
67 Ok(f_res) 67 Ok(f_res)
68 } 68 }