aboutsummaryrefslogtreecommitdiff
path: root/embassy-lora/src
diff options
context:
space:
mode:
authorDario Nieuwenhuis <[email protected]>2022-02-16 03:54:39 +0100
committerDario Nieuwenhuis <[email protected]>2022-03-11 00:38:07 +0100
commit9bad9365dcf31dd558aca05f60d244beb9e5e697 (patch)
tree3d54927ce409975c58dff4409b8a140a4b68abd1 /embassy-lora/src
parent828cdb295183b8733ec636a80e0d35e6f8e41827 (diff)
Update rust nightly, embedded-hal 1.0, embedded-hal-async.
Diffstat (limited to 'embassy-lora/src')
-rw-r--r--embassy-lora/src/stm32wl/mod.rs2
-rw-r--r--embassy-lora/src/sx127x/mod.rs18
-rw-r--r--embassy-lora/src/sx127x/sx127x_lora/mod.rs4
3 files changed, 11 insertions, 13 deletions
diff --git a/embassy-lora/src/stm32wl/mod.rs b/embassy-lora/src/stm32wl/mod.rs
index 783140cb3..7dc750cf9 100644
--- a/embassy-lora/src/stm32wl/mod.rs
+++ b/embassy-lora/src/stm32wl/mod.rs
@@ -78,7 +78,7 @@ impl<'a> SubGhzRadio<'a> {
78 // This is safe because we only get interrupts when configured for, so 78 // This is safe because we only get interrupts when configured for, so
79 // the radio will be awaiting on the signal at this point. If not, the ISR will 79 // the radio will be awaiting on the signal at this point. If not, the ISR will
80 // anyway only adjust the state in the IRQ signal state. 80 // anyway only adjust the state in the IRQ signal state.
81 let state = unsafe { &mut *(p as *mut StateInner<'a>) }; 81 let state = &mut *(p as *mut StateInner<'a>);
82 state.on_interrupt(); 82 state.on_interrupt();
83 }); 83 });
84 irq.set_handler_context(state_ptr as *mut ()); 84 irq.set_handler_context(state_ptr as *mut ());
diff --git a/embassy-lora/src/sx127x/mod.rs b/embassy-lora/src/sx127x/mod.rs
index 6a15dab82..c70f33582 100644
--- a/embassy-lora/src/sx127x/mod.rs
+++ b/embassy-lora/src/sx127x/mod.rs
@@ -20,7 +20,7 @@ pub trait RadioSwitch {
20/// Semtech Sx127x radio peripheral 20/// Semtech Sx127x radio peripheral
21pub struct Sx127xRadio<SPI, CS, RESET, E, I, RFS> 21pub struct Sx127xRadio<SPI, CS, RESET, E, I, RFS>
22where 22where
23 SPI: ReadWrite<u8, Error = E> + 'static, 23 SPI: SpiBus<u8, Error = E> + 'static,
24 E: 'static, 24 E: 'static,
25 CS: OutputPin + 'static, 25 CS: OutputPin + 'static,
26 RESET: OutputPin + 'static, 26 RESET: OutputPin + 'static,
@@ -42,7 +42,7 @@ pub enum State {
42 42
43impl<SPI, CS, RESET, E, I, RFS> Sx127xRadio<SPI, CS, RESET, E, I, RFS> 43impl<SPI, CS, RESET, E, I, RFS> Sx127xRadio<SPI, CS, RESET, E, I, RFS>
44where 44where
45 SPI: ReadWrite<u8, Error = E> + 'static, 45 SPI: SpiBus<u8, Error = E> + 'static,
46 CS: OutputPin + 'static, 46 CS: OutputPin + 'static,
47 RESET: OutputPin + 'static, 47 RESET: OutputPin + 'static,
48 I: Wait + 'static, 48 I: Wait + 'static,
@@ -64,7 +64,7 @@ where
64 64
65impl<SPI, CS, RESET, E, I, RFS> Timings for Sx127xRadio<SPI, CS, RESET, E, I, RFS> 65impl<SPI, CS, RESET, E, I, RFS> Timings for Sx127xRadio<SPI, CS, RESET, E, I, RFS>
66where 66where
67 SPI: ReadWrite<u8, Error = E> + 'static, 67 SPI: SpiBus<u8, Error = E> + 'static,
68 CS: OutputPin + 'static, 68 CS: OutputPin + 'static,
69 RESET: OutputPin + 'static, 69 RESET: OutputPin + 'static,
70 I: Wait + 'static, 70 I: Wait + 'static,
@@ -80,7 +80,7 @@ where
80 80
81impl<SPI, CS, RESET, E, I, RFS> PhyRxTx for Sx127xRadio<SPI, CS, RESET, E, I, RFS> 81impl<SPI, CS, RESET, E, I, RFS> PhyRxTx for Sx127xRadio<SPI, CS, RESET, E, I, RFS>
82where 82where
83 SPI: ReadWrite<u8, Error = E> + 'static, 83 SPI: SpiBus<u8, Error = E> + 'static,
84 CS: OutputPin + 'static, 84 CS: OutputPin + 'static,
85 E: 'static, 85 E: 'static,
86 RESET: OutputPin + 'static, 86 RESET: OutputPin + 'static,
@@ -89,15 +89,14 @@ where
89{ 89{
90 type PhyError = Sx127xError; 90 type PhyError = Sx127xError;
91 91
92 type TxFuture<'m> 92 type TxFuture<'m> = impl Future<Output = Result<u32, Self::PhyError>> + 'm
93 where 93 where
94 SPI: 'm, 94 SPI: 'm,
95 CS: 'm, 95 CS: 'm,
96 RESET: 'm, 96 RESET: 'm,
97 E: 'm, 97 E: 'm,
98 I: 'm, 98 I: 'm,
99 RFS: 'm, 99 RFS: 'm;
100 = impl Future<Output = Result<u32, Self::PhyError>> + 'm;
101 100
102 fn tx<'m>(&'m mut self, config: TxConfig, buf: &'m [u8]) -> Self::TxFuture<'m> { 101 fn tx<'m>(&'m mut self, config: TxConfig, buf: &'m [u8]) -> Self::TxFuture<'m> {
103 trace!("TX START"); 102 trace!("TX START");
@@ -137,15 +136,14 @@ where
137 } 136 }
138 } 137 }
139 138
140 type RxFuture<'m> 139 type RxFuture<'m> = impl Future<Output = Result<(usize, RxQuality), Self::PhyError>> + 'm
141 where 140 where
142 SPI: 'm, 141 SPI: 'm,
143 CS: 'm, 142 CS: 'm,
144 RESET: 'm, 143 RESET: 'm,
145 E: 'm, 144 E: 'm,
146 I: 'm, 145 I: 'm,
147 RFS: 'm, 146 RFS: 'm;
148 = impl Future<Output = Result<(usize, RxQuality), Self::PhyError>> + 'm;
149 147
150 fn rx<'m>(&'m mut self, config: RfConfig, buf: &'m mut [u8]) -> Self::RxFuture<'m> { 148 fn rx<'m>(&'m mut self, config: RfConfig, buf: &'m mut [u8]) -> Self::RxFuture<'m> {
151 trace!("RX START"); 149 trace!("RX START");
diff --git a/embassy-lora/src/sx127x/sx127x_lora/mod.rs b/embassy-lora/src/sx127x/sx127x_lora/mod.rs
index 6fbd3a4bd..62eaf0a95 100644
--- a/embassy-lora/src/sx127x/sx127x_lora/mod.rs
+++ b/embassy-lora/src/sx127x/sx127x_lora/mod.rs
@@ -8,7 +8,7 @@
8use bit_field::BitField; 8use bit_field::BitField;
9use embassy::time::{Duration, Timer}; 9use embassy::time::{Duration, Timer};
10use embedded_hal::digital::v2::OutputPin; 10use embedded_hal::digital::v2::OutputPin;
11use embedded_hal_async::spi::ReadWrite; 11use embedded_hal_async::spi::SpiBus;
12 12
13mod register; 13mod register;
14use self::register::PaConfig; 14use self::register::PaConfig;
@@ -48,7 +48,7 @@ const VERSION_CHECK: u8 = 0x09;
48 48
49impl<SPI, CS, RESET, E> LoRa<SPI, CS, RESET> 49impl<SPI, CS, RESET, E> LoRa<SPI, CS, RESET>
50where 50where
51 SPI: ReadWrite<u8, Error = E>, 51 SPI: SpiBus<u8, Error = E>,
52 CS: OutputPin, 52 CS: OutputPin,
53 RESET: OutputPin, 53 RESET: OutputPin,
54{ 54{